466 results about "Delay time" patented technology

A work load of a web server that is caused by sequence of requests sent by one or more client devices is reduced by blocking (such as discarding, delaying, or dropping) part of, or whole of, the requests in the sequence, so that the one or more client devices are not identified as causing a Denial- of-Service (DoS) attack or Distributed Denial-of-Service attack (DDoS attack). The blocking may be in response to metering, continuously or periodically, of a Round-Trip delay Time (RTT) to the web server, or metering a feature or amount of the sent sequence of requests, the received responses therefrom, or any combination thereof. The blocking may be in response to comparing the metered value to a threshold, or in response to a correlation between the metered values, where the blocking is performed in response to the metered value being above the threshold. The process may be repeated.

The invention provides a scene port entering and leaving aircraft joint optimization scheduling method. The method comprises the following steps: aiming at aircrafts which take off and land on a plurality of parallel runways in an airport, establishing a mixed integer programming model for a scene port entering and leaving aircraft IASP; setting a target function and a constraint condition of an IASTP problem by taking minimization of the total delay duration of the port entering and leaving aircrafts as a target; and based on the constraint conditions, solving a target function of the IASTP problem by adopting a heuristic algorithm based on VNS, and obtaining a comprehensive scheduling scheme of runway and sliding path distribution, take-off and landing sequence and time of the port entering and leaving aircraft. According to the method, actual operation constraints of various scenes are considered, runway distribution and sorting, taxiing path selection and taxiway scheduling of the port entering and leaving aircrafts, and a deducing sorting scheduling scheme of the port leaving aircrafts are planned and optimized as a whole, the take-off and landing delay time of the port entering and leaving aircrafts is shortened as much as possible, the hub airport operation efficiency is improved, and the airport landing time is shortened. And decision support is provided for efficient scheduling of aircrafts.

The invention provides a control method of a self-service washing machine door lock. The control method is applied to a server, and includes the following steps: the delay time of door opening sent bya client is received, wherein the delay time of door opening refers to the time after the washing process is finished; after a washing event is finished, whether the delay time of door opening expires or not is judged; if not, an unlocking instruction sent by the client is received, and a washing machine is controlled to open the door lock according to the instruction. According to the control method of the self-service washing machine door lock, washing machines in a washhouse can be efficiently utilized, and if users fail to take out clothes in time after washing is finished, the users needto reserve the delay time and pay for continued occupation of the washing machine.

A heel backer shaper comprises a case, a last-compressing ironing base, a last rotation mechanism, a shaping wheel, an automatic selector switch, and a footboard. One side of the upper half of the case is not closed. The last rotation mechanism is disposed on the upper half of the case. The last rotation mechanism comprises a cylinder and a rotary table; the rotary table is disposed at the top of the cylinder; the last-compressing ironing base is disposed on the top inner wall of the case and right faces the rotary table. During heel shaping, the heel backer shaper can adjust the operating performances, such as the position of the shaping wheel on a backer, knocking force, ironing temperature and delay time, according to the quality conditions of a shoe so as to acquire optimal shaping effect; during normal working, the heel backer shaper can operate in an automatic manner; an electrothermal plate on the last-compressing ironing base is controlled via a three-compartment closed-loop controlled silicon voltage regulator, temperature control precision is greatly improved, a temperature difference can be controlled within a 10 DEG C range, and the plane of the shaped backer is flat, with clear edge and smooth wrinkle-free surface.

The invention provides a knob dimming method which comprises the following steps: S1, when a falling edge is detected in each interruption of a program, performing input falling edge interruption on a pin A, and then starting a timer; s2, judging whether the timing time of the timer is up or not, if not, returning to S1, and if so, reading the signal level of the pin A; and S3, judging whether the signal level of the pin A read in S2 is a low level or not, if not, returning to S1, and if so, judging that the level of the pin A is valid. According to the invention, the effective level can be rapidly obtained after the level recovers to be stable, the maximum delay time or pulse period is not measured again by means of device replacement, the knob level is read by dynamically setting timing, misjudgment is greatly avoided, and in addition, the problem of pulse signal counting coverage caused by rapid rotation of the knob is also solved.

The invention discloses a motor control digital circuit and a driving system, and the circuit comprises a first delay time sequence module which transmits a secondary delay pulse to an acceleration and deceleration synchronization module based on a synchronization signal and delay time; the acceleration and deceleration synchronization module obtains path input after receiving the secondary delay pulse, and selects acceleration and deceleration path write-in and acceleration and deceleration position write-in sent to the acceleration and deceleration module; the stepping direction selection module receives the stepping and direction signals of the acceleration and deceleration module and the stepping and direction signals of the distance compensation module, and outputs stepping control and direction control of the motor according to the stepping direction selection signals; and the absolute position module outputs an absolute position based on stepping control and direction control of the motor. A synchronous control function and an absolute position function are added into an existing acceleration and deceleration function, so that a user can freely switch among three modes of acceleration and deceleration, synchronous acceleration and deceleration and distance compensation, an original complex algorithm is realized through a digital circuit, and the working efficiency and the integration degree are improved.

The invention provides a phased array ultrasonic interface debonding detection method for a multilayer curved surface bonding structure, which comprises the following steps of: accurately calculating delay time of each array element in a phased array ultrasonic probe to a target focus by designing a delay block attached to a solid engine and aiming at a cylindrical special structure; therefore, in-phase superposition of sound waves at the target focus is achieved, focusing of sound beams is achieved, the problem of delay time calculation of sound waves emitted by all array elements of a phased array probe of a cylindrical structure is solved, and the problem of control over the deflection angle and the focusing depth of the sound beams synthesized after the sound waves pass through a plurality of curved surface interfaces is solved. Accurate positioning and visual representation of the debonding defect of the deep interface are realized. The technology provides a new technical means for accurately judging the interface debonding defect, and has important significance for guaranteeing the structural integrity and the use safety of the interface debonding defect.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The invention relates to the technical field of equipment communication management, in particular to a signal processor access method and computer equipment, and the method comprises the steps that in response to system power-on, a first controller sets an access enable signal to be in an invalid state so as to limit a management controller to access a signal processor; obtaining the model of the signal processor, and determining fixed delay according to the model of the signal processor; starting timing in response to detection of completion of loading of the signal processor; acquiring environmental parameters of the signal processor and determining compensation delay according to the environmental parameters; determining target delay according to the fixed delay and the compensation delay; triggering the management controller to access the signal processor in response to the arrival of the target delay time; through the method, the chip access timeliness can be improved, and the chip communication interruption influence range can be reduced.

To provide a program production system that measures a delay time of a video image with respect to audio and auxiliary data by a simple method so as to realize synchronization among the video image, the audio and the auxiliary data generated at the same time.SOLUTION: The video time difference calculating unit 11 - 1 of the video delay measuring apparatus 2 extracts the time stamp V1 from the video RTP packet VTS1 and generates the video RTP packet V2 including the timing information. The video RTP packet V2 is transmitted to the video delay time difference measuring path. A video time difference calculation section 11-1 extracts a time stamp V3 from a video RTP packet VTS2 to obtain a video time difference VT. The audio time difference calculator 11-2 obtains the audio time difference ST, and the ancillary data time difference calculator 11 - 3 obtains the ancillary data time difference AT. The delay time calculating unit 13 subtracts the audio time difference ST from the video time difference VT to obtain the audio delay time SD, and subtracts the ancillary data time difference AT from the video time difference VT to obtain the ancillary data delay time AD.SELECTED DRAWING: Figure 5

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

A memory apparatus and an operation method of a memory system, the memory apparatus including a first counter that outputs a first count value corresponding to a first delay time of a data strobe signal on a first path; a second counter that outputs a second count value corresponding to a second delay time of a data signal on a second path; a first comparator that outputs a first difference value therebetween; a first register that stores a delay reference value; a second comparator that outputs a second difference value therebetween; and a delay chain that adjusts a phase difference between the data signal and the data strobe signal based on the second difference value.

By a communication device, a line delay time estimation method, a non-transitory computer-readable storage medium storing a line delay time estimation program, a communication packet is accumulated, a data amount of the communication packet is monitored, and a residence time, which is a duration and for which the communication packet remains in a transmission buffer, is estimated as an upstream buffer delay time from the communication device to a counterpart device.

The invention relates to a two-step time-to-digital converter and a method thereof, a phase-locked loop and an analog-to-digital converter. The method comprises the following steps of: performing N1-stage delay on a reference signal rs in sequence, and performing coarse quantization on the delayed signal of each stage relative to a feedback signal fb; when the two signals are different, after the time t1 is delayed, the first arriving signal is selected as a time starting signal Start and the fb is delayed for the time t1 and then serves as a time stopping signal Stop in the delayed period, and when the two signals are the same, the rs is selected as Start after the time t2 is delayed, and the fb is selected as Stop after the time t2 is delayed; performing fine quantization formation on the Start and the Stop; and decoding the code into n1-bit high-bit binary codes and decoding the code into n2-bit low-bit binary codes. The technical problem that the area and power consumption of an existing two-step TDC are increased due to the fact that the number of logic gates of a selector is greatly increased along with the increase of coarse quantization bits is solved.

The vehicle control system includes an abnormality diagnosis unit for determining whether a synchronization abnormality between a master ECU and a slave ECU has occurred. The abnormality diagnosis unit transmits and receives a signal between the master ECU and the slave ECU and acquires time information. The slave ECU calculates a delay time of transmission based on the acquired time information. Then, the abnormality diagnosis unit first determines whether or not there is a periodic shift. When determining that there is no periodic deviation, the abnormality diagnosis unit determines whether or not there is an offset deviation based on the difference obtained by subtracting the delay time from the second time and the first time. The abnormality diagnosis unit determines that a synchronization abnormality has occurred when it is determined that there is a periodic deviation or when it is determined that there is the offset deviation.

A trace of intensity versus time values is received for a series of samples produced by a mass spectrometer. Also, a series of ejections times corresponding to the series of samples produced by a sample introduction system is received. A series of expected peak times corresponding to the series of ejection times are calculated using a known delay time from ejection to mass analysis. At least one isolated peak of the trace is identified using the series of expected peak times. A peak profile is calculated by fitting a mixture of at least two different distribution functions to the at least one isolated peak. For at least one time of the series of expected peak times, an area of a peak at the one time is calculated by fitting the peak profile to the trace at the one time and calculating an area of the fitted peak profile.

The invention relates to the technical field of clinical test data acquisition and intelligent quality control, in particular to a clinical test data real-time acquisition and quality control management platform, which is characterized in that an operation starting time recording unit acquires a subject disinfection operation starting timestamp, an operation sequence delay calculation unit calculates actual operation delay based on standard consumed time, and a quality control unit calculates the actual operation delay based on the standard consumed time. The transmission delay processing unit separates transmission and operation delay through double timestamps, the actual collection time determining unit subtracts pure transmission delay time data and operation delay time data from the timestamps uploaded by the device through a reverse time restoration algorithm to obtain actual blood collection completion time, and the time window dynamic judging unit judges whether the time window dynamic judging unit is in real blood collection completion time or not through a dynamic offset boundary. The real time is compared with a preset time window to judge qualification, the physiological index correction unit corrects blood glucose and insulin values in real time through a layered framework and a correction rule base, and the dynamic association logic verification unit adjusts association rules and verifies index logic in combination with a three-dimensional decision matrix, so that support is provided for clinical tests.

The present invention provides a communication method that uses a cryptographic key and that is capable of performing time synchronization with high accuracy and preventing tampering.　In the communication method, a terminal (3) at an exchange, a plurality of relay stations (9a, 9b, 9c), and a terminal (11) of a transactor receive a cryptographic key (7d) from a space-time standard station (5), the plurality of relay stations (9a, 9b, 9c) transmit encrypted relay station information to the terminal (11) of the transactor, the terminal (11) of the transactor transmits, to a selected relay station (9a), transaction information to which the encrypted relay station information has been added, the selected relay station (9a) transmits, to the terminal (3) at the exchange, the transaction information to which reception time has been added, and, when time information at the standard time is within a predetermined delay time, the terminal (3) at the exchange receives the transaction information included in the transaction information to which the relay station information has been added.

The present disclosure provides a delay simulation method, which comprises: determining a delay buffer time of an event based on a preset delay time and a network-on-chip transmission delay time; wherein the event is pulse firing information between neurons; and writing the event into a delay slot of a delay buffer and placing it in a slot position corresponding to the delay buffer time. The present disclosure also provides a delay simulation device, an electronic device and a computer readable medium.

The invention relates to the technical field of geotechnical engineering numerical simulation, in particular to a tunnel blasting minimum delay time judgment method based on blasting effect evaluation, which comprises the following steps: acquiring a tunnel face surrounding rock breaking coefficient and basic mechanical parameters; establishing an equal-scale model of the tunnel face; the rock mass throwing volume in the unit time is counted, and the relation between the rock mass throwing volume in the unit time and the free face appearance volume in the unit time serves as the minimum delay time judgment basis; determining an optimal free face forming effect based on the minimum delay time judgment basis; according to the optimal free face forming effect, the minimum delay time of each row of blast holes is sequentially judged; and a blasting effect evaluation index is constructed, and if the blasting effect is larger than or equal to the blasting excavation qualification rate and smaller than or equal to the annular flatness, it is judged that the minimum delay time of each row of blast holes is the final blasting delay time. The closed-loop optimization of blasting parameters is realized, and the problems of serious back break, poor smoothness, non-ideal lumpiness and the like in tunnel smooth blasting are effectively solved.

The present disclosure provides a time compensation method and system for interference test equipment. The method includes: obtaining a first delay time and a second delay time; decomposing the first delay time and the second delay time to obtain a nanosecond scale delay time corresponding to the first delay time and a picosecond scale delay time corresponding to the second delay time; performing lead compensation for the nanosecond scale delay time by a configurable lead compensation and output module to obtain a nanosecond scale lead compensation time; performing lag compensation for the picosecond scale delay time by a delay compensation module to obtain a picosecond scale delay compensation time, and calculating a sum of the nanosecond scale lead compensation time and the picosecond scale delay compensation time to obtain a picosecond scale lead compensation time; and applying an interference signal on a controller area network, CAN, bus based on the picosecond scale lead compensation time. Therefore, by using a plurality of timing controllers connected in cascade in the delay compensation module, the picosecond scale delay compensation time is realized.

Systems and methods for regulating electronic messages transmissions. A message delay system is disposed between one or more first entities and a second entity within at least one network. Electronic messages are received from among at least one the first entities and the second entity at one or more message arrival times. A message delay component applies a delay to each received electronic message, based on a predefined delay time common to all of the first entities and a first entity delay offset associated with a first entity that is associated with the received message. The first entity delay offset is based on a geographical origin of the first entity relative to a geographical origin of the second entity. Each delayed message is transmitted to a designated recipient via the network, where the designated recipient is among the second entity and the first entities.

The invention relates to the technical field of network communication, and discloses an interrupt control method and device, equipment and a medium, and the method comprises the steps: if an interrupt event is monitored, determining a target register for controlling the interrupt event according to a preset mapping relation, and dividing the target register into a plurality of sub-registers; determining a target sub-register corresponding to the interrupt event based on the priority of the interrupt event; and timing based on the preset delay time of the target sub-register, and reporting the interrupt vector to a host based on the state of the interrupt vector after timing expires. According to the method, the interrupt control register is dynamically divided into a plurality of sub-registers capable of flexibly configuring the bit width, and the interrupt events are bound with the sub-registers according to the priorities of the interrupt events, so that the processing speed of the interrupt events with different priorities is adjusted on the premise that the hardware resource area is not changed, and the host performance is improved.

This invention provides a method and system for controlling the delay time of electronic detonators, comprising: configuring delay values ​​for each electronic detonator via an initiator; sending delay time calibration commands to all electronic detonators and calculating the total duration of the reference square wave of the delay time calibration commands to obtain T0; calculating T1 based on T0; upon receiving the delay initiation command, the electronic detonator calculates and writes the value to a delay timer based on T1, and decrements the timer; after the delay timer of the electronic detonator reaches zero, writing the value of T1mod div to the delay timer and decrementing the timer; and detonating the electronic detonator after the delay timer reaches zero. This invention uses a frequency-division clock to compensate for the delay time error caused by the delay, thus solving the problem of amplified delay time error caused by using only a frequency-division clock.

A signal processing apparatus includes circuitry configured to measure a relative displacement amount of the signal processing apparatus for each predetermined measurement period, measure a first delay time corresponding to a time period required for the signal processing apparatus to output a positioning solution, and estimate a position of the signal processing apparatus at a time after a current time by the first delay time, based on the positioning solution, the relative displacement amount for each measurement period, the first delay time, and a second delay time. A positioning server determines the positioning solution based on observation data related to a GNSS signal, and the second delay time corresponds to a time period from transmission of the observation data to the positioning server to reception of the positioning solution.

The present application belongs to the technical field of distributed cooperative control system, and discloses a multi-point high-precision cooperative ignition system for firework display, comprising: a central controller which non-timely distributes delay time stamps to a plurality of distributed ignition modules and broadcasts a content-neutral synchronization event at a starting moment; the distributed ignition module starts a local timer upon detecting the synchronization event and autonomously counts down according to the pre-stored delay time stamp to execute ignition, the present application decentralizes intelligent time decision to the terminal, avoids the interference of signal physical transmission delay on the overall ignition precision of the system, and replaces the complex real-time clock synchronization and delay compensation mechanism in the traditional control system, so that the architecture simplifies the physical design and deployment complexity of the system, and improves the synchronization robustness and scalability when a large number of nodes work cooperatively.

This disclosure provides a method for a user equipment to determine a radio wave delay time value, the method comprising the steps of: requesting a radio wave delay time from a base station; transmitting a time measurement signal via time measurement resources allocated by the base station; receiving a response from the base station including an extended timing advance command (extended TA command); and applying time information and starting a timer based on the received response. This disclosure also provides a method for a user equipment to perform communication in an unlicensed frequency band, the method comprising determining whether to transmit data via a configured license (CG), comparing the priority between the CG and uplink resources, and changing the priority of the CG based on a listen-before-tell (LBT) failure.

Disclosed are a method and apparatus for controlling a hardware accelerator. The method includes setting a delay time related to task performance of a specific hardware accelerator, switching to a sleep state during the set delay time from a request time point when making a request, to a central processing unit (CPU), for requesting the specific hardware accelerator to accelerate a task, polling the state of the specific hardware accelerator to the CPU by switching from the sleep state to an operating state after the delay time, not polling a state of the specific hardware accelerator to the CPU during the delay time when switching to the sleep state, and receiving result information corresponding to the polling from the CPU in response to the polling.

The invention discloses an integrator resetting method and device under flexible direct current partition co-frequency control and a medium, and relates to the technical field of co-frequency control, and the method comprises the steps: obtaining an output value of an integrator in a co-frequency control module; when the output value is saturated, judging whether a target parameter meets a reset starting condition within a target delay duration or not; and if yes, reducing the output value of the integrator at a target rate until a reset ending condition is met. According to the method, the output value of the integrator can be automatically and smoothly reset after the disturbance is relieved, so that the transmission capacity of the flexible direct current is released, the flexible direct current can respond to the subsequent disturbance at any time, and the utilization efficiency and the operation flexibility of regulation and control resources of a power system are improved.

To provide a quantum computer control device capable of improving accuracy of time synchronization to the same extent as accuracy of clock synchronization.SOLUTION: A control device 100 for controlling a quantum bit comprises: a time counter 160 which indicates a time; a clock distributor 130 which inputs a reference clock and distributes a clock which is synchronized to the reference clock to constituents inside and outside of the control device; and a trigger signal distributor 140 which inputs a reference trigger signal and distributes a trigger signal to the constituents inside and outside of the control device on the basis of a time indicated by the time counter to which the time is set on the basis of the reference trigger signal. The reference trigger signal is sampled at the timing of the clock and a time obtained by adding latency of the reference trigger signal to the time indicated by the time counter is set to the time counter at the timing when the reference trigger signal is sampled.SELECTED DRAWING: Figure 1