983 results about "Delay time" patented technology

The invention discloses a high-precision delay synchronization system with a phase jitter compensation function. The high-precision delay synchronization system comprises an upper computer, an external trigger module, a time reference module, a master control ZYNQ module, a frequency synthesis and trigger mode selection module, a jitter compensation module, a precise delay circuit and an output signal conditioning circuit. According to the invention, the pulse output with adjustable delay time, amplitude and polarity can be realized, the high-precision delay synchronization of signals is realized, and the stability is higher.

A communication system that achieves reduction in delay time or the like at the time of mobility includes: a base station that is applied to a fifth-generation wireless access system; and a communication terminal that connects to the base station. When a cell that is a connection destination of a communication terminal in communication via any one of a plurality of cells constituted by the base station is changed, the base station transmits, to the communication terminal, setting information for measuring communication quality in a physical layer of the cell, the communication terminal measures the communication quality in another cell different from a cell being connected based on the setting information received from the base station, and transmits a measurement result to the base station, and the base station determines a cell to be a new connection destination of the communication terminal based on the measurement result.

The invention provides an unmanned aerial vehicle visual servo intrusion target tracking and intercepting method based on time delay compensation. The method comprises the following steps: acquiring a latest image of a tracking target through a camera on an unmanned aerial vehicle; based on the latest image, determining the position of the tracking target in an image coordinate system of the latest image as a first position; determining a position error of the first position by adopting a prediction algorithm based on improved Kalman filtering based on the delay time of collecting the latest image; based on the position error, determining a control parameter used for visual servo tracking of the corresponding tracking target; and based on the first position and the control parameter, controlling the unmanned aerial vehicle to fly to track and intercept the corresponding tracking target. Therefore, the position error compensation is performed through the delay time of the latest image, and the unmanned aerial vehicle is controlled to track the corresponding target based on the position error, so that the tracking accuracy is improved, the tracking interception error is reduced, and the interception success rate is improved.

The embodiment of the invention discloses a cascade structure delay circuit, a signal delay method applied to a multi-stage delay unit, semiconductor test equipment and a time sequence generation chip, the circuit comprises a clock source, a signal input source and the multi-stage delay unit, and the multi-stage delay unit comprises at least two delay units connected in a cascade mode; the signal input end of the first-stage delay unit in the multiple stages of delay units is connected with a signal input source; and each delay unit in the multiple stages of delay units is used for delaying an input signal according to the delay configuration value received by the respective delay time configuration end, outputting a delayed output signal, and updating the delay configuration value according to the update interval time set by each delay unit. According to the embodiment of the invention, the overall delay precision and delay time range of the multi-stage delay unit is expanded, and the time precision of the synthetic waveform of the time sequence generation device of the semiconductor test equipment is improved.

The embodiment of the invention provides a key delay test method and system, and the method comprises the steps: capturing a hardware interrupt signal generated by each physical key response in real time through simulating a preset operation event, measuring first delay time, and evaluating the first delay time according to a preset performance threshold value, analyzing existing potential external interference factors and potential system internal anomalies, adjusting initial test environment parameters, obtaining an optimized test environment, repeatedly simulating operation events, capturing hardware interrupt signals generated by response of each physical key, and calculating average delay time as a response characteristic index of the physical key; predicting the use reliability and the aging effect of the physical key by responding to the change trend of the characteristic index, and generating a trend analysis report; according to the technical scheme provided by the embodiment of the invention, the test precision and reliability are improved, a user can take preventive measures in advance, and service interruption or equipment damage caused by key faults is avoided.

The invention discloses an instruction scheduling method, device and system, a product and a medium, and relates to the technical field of processor design. The invention provides an instruction scheduling method aiming at the problem that the dynamic change in the instruction transmitting time cannot be accurately scheduled by the existing out-of-order scheduling strategy. The historical delay information of each instruction is stored through the delay cache, and when the instruction execution delay corresponding to the instruction is dynamic delay, the dynamic delay is predicted through the historical delay information stored in the delay cache, so that instruction scheduling is performed. According to the method, the dynamic delay of which the delay time cannot be predetermined is included in the consideration range of instruction scheduling based on the dynamic delay prediction mechanism. On the basis of the method, for dynamic change scenes in instruction transmission time such as memory access delay and cache miss, the optimal instruction transmission opportunity can be accurately predicted, so that the effect of instruction scheduling on performance improvement of a processor is further improved.

Method includes receiving a first delay time and a first timing measurement by a TMV from a first receiver at a first node. The first timing measurement is generated by comparing a first time associated with a first signal to a first local clock time. The first signal is transmitted by a transmitter at a source. The TMV receives from a second receiver at a second node in a network, a second delay time and a second timing measurement. The second timing measurement is generated by comparing a second time associated with a second signal to a second local clock time. The second signal is transmitted by the transmitter at the source. The TMV generates a correction factor time based on the first timing measurement, the first delay time, the second timing measurement, and the second delay time. The TMV transmits the correction factor time to the second node.

The invention discloses a PUF (Physical Unclonable Function) structure based on delay difference quantization, and the structure comprises a PUF circuit which comprises two time delay circuits which are connected in parallel; a plurality of layers of differential tapped circuits TDC, and decoders connected with each layer of differential tapped circuit TDC; the delay data quantization unit is connected with the multi-layer decoder, and the delay data quantization unit is connected with the LFSR confusion structure; the two delay circuits are connected with the multi-layer differential tap circuit TDC through the signal selection structure, the signal selection structure inputs delay signals which respond first and then respond in the two delay circuits into a start end and a stop end of each layer of differential tap circuit TDC, the decoder determines delay time of the two delay circuits under corresponding delay resolution, and the decoder outputs the delay time to the multi-layer differential tap circuit TDC. The delay data quantization unit is used for averaging the delay time under different time delay resolutions to serve as final delay data, and the final response R is output after the final delay data is confused by the LFSR confusion structure. Signals of the two symmetrical delay paths are respectively input into a framework of a multi-layer TDC quantization circuit, so that delay difference digital code quantization is realized.

The invention provides a train cooperative operation prediction control method and system based on a dynamic interval model, and belongs to the technical field of train operation control, and the method comprises the steps: calculating a train minimum tracking interval based on the real-time estimation state information of a train according to a train relative distance braking model; the communication delay time of the train-to-train communication system is considered, an additional safety margin is added on the basis of the minimum tracking interval of the train, and the influence of communication delay on cooperative operation control of the train is compensated; a system state space model is constructed based on the safety margin, and a train optimization control problem is formed based on the control constraint and the control target; and solving a train optimization control problem, obtaining an acceleration sequence for controlling train operation, and acting a first item of the sequence on the train to realize train operation control. According to the invention, while the tracking interval between the trains is effectively reduced, the influence of communication delay on the train operation is compensated by adding the additional safety margin, so that the train operation safety is improved, and the line transportation efficiency is improved.

A terminal, as disclosed, includes a receiver that receives a channel state information reference signal (CSI-RS) in a downlink; and a controller that determines, in a higher layer measurement based on the CSI-RS, that a delay time based on at least one of a number of samples used in the measurement or a scaling factor indicating an overlap between a resource for the CSI-RS and a measurement gap is included in a measurement time. If the resource for the CSI-RS partially overlaps a periodicity of the measurement gap, the controller determines that the scaling factor indicating the overlap between the resource for the CSI-RS and the measurement gap is a value based on a periodicity of the resource for the CSI-RS and the periodicity of the measurement gap. In other aspects, a base station, a communication method, and a communication system are also disclosed.

The invention discloses a memory chip access control method and device, a storage medium and electronic equipment. Comprising the steps that first delay time for responding to an activation command when a memory chip conducts data access is obtained, and the first delay time is used for representing the time interval between sending of the activation command to the memory chip and responding of the activation command by the memory chip; second delay time for responding to a target command except the activation command when the memory chip performs data access is obtained, and the second delay time is used for representing a time interval between sending of the target command to the memory chip and response of the memory chip to the target command; a first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, and the first target timing parameter is used for determining the target time for accessing the memory chip. The technical problem that the data read-write efficiency of an operating system is low due to the fact that the time of the activation command is not adjusted when the line address is checked through the activation command in the prior art is solved.

A work load of a web server that is caused by sequence of requests sent by one or more client devices is reduced by blocking (such as discarding, delaying, or dropping) part of, or whole of, the requests in the sequence, so that the one or more client devices are not identified as causing a Denial- of-Service (DoS) attack or Distributed Denial-of-Service attack (DDoS attack). The blocking may be in response to metering, continuously or periodically, of a Round-Trip delay Time (RTT) to the web server, or metering a feature or amount of the sent sequence of requests, the received responses therefrom, or any combination thereof. The blocking may be in response to comparing the metered value to a threshold, or in response to a correlation between the metered values, where the blocking is performed in response to the metered value being above the threshold. The process may be repeated.

A method of selecting an accelerator includes, based on receiving a machine learning model, dividing the machine learning model into operations; verifying operation delay times of the operations for accelerators based on a delay timetable; and selecting, based on the operation delay times, one accelerator from among the accelerators per operation; and performing the operations by corresponding selected accelerators.

The invention discloses a simulation IC test method and system based on load transient response, and aims to improve the performance evaluation precision of a simulation IC under a complex load condition. The method comprises the following steps: firstly, acquiring transient response waveforms and response delay characteristics of an analog IC (Integrated Circuit) in various load jump modes, and constructing a mapping matrix between a load current step change rate and response delay time; in the real-time test, response delay time in a future preset time period is predicted according to the step change rate of the current load current. When the steady-state time window exists, a fixed sampling time sequence is set based on the window to generate a first test waveform; and if the steady-state window does not exist, correcting the transient waveform, and generating a compensated second test waveform. And then time sequence decomposition is carried out on the test waveform, and a load transient stability evaluation matrix is constructed, so that the dynamic performance of the simulation IC is accurately evaluated, and a detailed performance test report is output.

Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generato and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.

The invention discloses a digital-analog collaborative test method, which comprises the following steps of: in a parameter configuration stage, embedding a trigger mark into a preset vector row to generate a test vector, and writing the test vector into a digital board card; configuring a trigger event corresponding to the trigger signal and first delay time; in the test stage, the digital board card detects whether a to-be-executed vector line has a trigger mark or not; a trigger signal corresponding to the trigger mark is sent to the system board card; the system board card sends the trigger signal to a corresponding simulation board card, and the simulation board card determines first delay time and a trigger event according to the trigger signal; delaying the trigger event for a first delay time and then triggering; the digital board card delays a second delay time after sending the trigger signal and sends test data corresponding to the vector line to the to-be-tested device; in the triggering process of the triggering event, the end time of the second delay time is aligned with the end time of the first delay time. According to the invention, the efficiency of digital-analog collaborative testing can be improved.

The invention provides an electronic detonator delay calibration method, which comprises the following steps of: starting a first timer based on a high-speed clock, and setting a first calibration time threshold value; synchronously starting a second timer based on a low-speed clock in the chip, and setting a second calibration time threshold value which is greater than the first calibration time threshold value; when the first timer reaches a first calibration time threshold value, stopping the second timer and acquiring an actual count value of the second timer; calculating a theoretical count value corresponding to the first calibration time threshold value; generating a calibration factor based on the ratio of the actual count value to the theoretical count value; dynamically correcting the low-speed clock count value corresponding to the target delay time according to the calibration factor; configuring a second timer by adopting the corrected count value, and executing delay control; by means of high precision of the high-speed clock, the low-speed clock is calibrated before detonation, so that the low-speed clock is more accurate in the current environment, the standard that the delay error is smaller than 1% is achieved, and it is guaranteed that the detonation time of the electronic detonator is accurate and errorless.

The invention provides a target tracking detection method of a photoelectric pod, detection equipment, a program product and a storage medium. Tracking is carried out while target detection is carried out, and the delay time between detection and tracking is shortened. After the target detection result and the target tracking result are obtained, the positive sample and the negative sample are obtained according to the target detection result and the target tracking result and the video image, and in this way, target and non-target data can be accurately collected, so that training samples are more targeted and diversified. And training a target detection updating model by using positive and negative samples, so that the model can learn the change characteristics of the target in real time, and outputting more accurate characteristic data and a target model for detecting and tracking a new video image. And finally, a correct target is determined through confidence score, and the tracking detection precision of the autonomous or semi-autonomous aircraft on the target in a complex and changeable environment is improved by integrating the interaction of the technical characteristics.

The invention provides a scene port entering and leaving aircraft joint optimization scheduling method. The method comprises the following steps: aiming at aircrafts which take off and land on a plurality of parallel runways in an airport, establishing a mixed integer programming model for a scene port entering and leaving aircraft IASP; setting a target function and a constraint condition of an IASTP problem by taking minimization of the total delay duration of the port entering and leaving aircrafts as a target; and based on the constraint conditions, solving a target function of the IASTP problem by adopting a heuristic algorithm based on VNS, and obtaining a comprehensive scheduling scheme of runway and sliding path distribution, take-off and landing sequence and time of the port entering and leaving aircraft. According to the method, actual operation constraints of various scenes are considered, runway distribution and sorting, taxiing path selection and taxiway scheduling of the port entering and leaving aircrafts, and a deducing sorting scheduling scheme of the port leaving aircrafts are planned and optimized as a whole, the take-off and landing delay time of the port entering and leaving aircrafts is shortened as much as possible, the hub airport operation efficiency is improved, and the airport landing time is shortened. And decision support is provided for efficient scheduling of aircrafts.

The invention discloses a task processing method and device, electronic equipment and a storage medium. The method comprises the steps that a to-be-processed task and a node idle period are obtained, and the to-be-processed task carries task starting time and task allowed delay time; performing idle period matching on the to-be-processed task based on the task starting time, the task allowable delay time and the node idle period, and determining an idle period matching result of the to-be-processed task; when the idle period matching result is successful matching, acquiring an idle node corresponding to the node idle period, and determining a target node based on the idle node; and scheduling the to-be-processed task to the target node, and executing the to-be-processed task on the target node. According to the scheme, the node resources in the idle time period are determined for the to-be-processed task, the node processing task in the idle time period is fully utilized, independent application and resource occupation for the to-be-processed task are not needed, the task processing efficiency is improved, node resource waste is avoided, and the utilization rate of the node resources in the idle time period is improved.

By a communication device, a line delay time estimation method, a non-transitory computer-readable storage medium storing a line delay time estimation program, a communication packet is accumulated, a data amount of the communication packet is monitored, and a residence time, which is a duration and for which the communication packet remains in a transmission buffer, is estimated as an upstream buffer delay time from the communication device to a counterpart device.

The invention provides a control method of a self-service washing machine door lock. The control method is applied to a server, and includes the following steps: the delay time of door opening sent bya client is received, wherein the delay time of door opening refers to the time after the washing process is finished; after a washing event is finished, whether the delay time of door opening expires or not is judged; if not, an unlocking instruction sent by the client is received, and a washing machine is controlled to open the door lock according to the instruction. According to the control method of the self-service washing machine door lock, washing machines in a washhouse can be efficiently utilized, and if users fail to take out clothes in time after washing is finished, the users needto reserve the delay time and pay for continued occupation of the washing machine.

A control method in a control device that controls movement of a plurality of moving bodies includes: moving the plurality of moving bodies in accordance with movement plans that have been predetermined and defining one or more passageways where each of the plurality of moving bodies passes from a departure place to a destination; acquiring an actual delay time that is a delay time of each of the plurality of moving bodies, the delay time being generated in each of the one or more passageways; updating a model representing a length of the delay time defined for each of the one or more passageways using the actual delay time in a corresponding passageway among the one or more passageways; acquiring a current location of each of the plurality of moving bodies; and updating each of the movement plans based on the updated model, the destination, and the current location.

The embodiment of the invention discloses a PWM signal generation method. The generation method comprises the following steps: determining setting delay time and reset delay time of an nth PWM delay signal, and determining a first comparison result of the setting delay time and a preset clock period and a second comparison result of the reset delay time and the preset clock period, and allocating a first delay time to the delay module and allocating a first comparison threshold to the first comparator according to the first comparison result, and allocating a second delay time to the delay module and allocating a second comparison threshold to the second comparator according to the second comparison result. According to the embodiment of the invention, the method does not need to depend on a high-precision clock chip, can achieve the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit, can achieve the delay of the duty ratio, can also achieve the delay of the signal period, is higher in time resolution, and is higher in precision. And more accurate and stable PWM signals can be output.

The invention discloses a data access switching method and device, and relates to the technical field of storage. In the data access process, the host and different controllers in the storage system establish different paths, and the host stores upgrade waiting delay time of the controller on the currently accessed path. Under the condition that a current controller transmitting a data access request of a host in the storage system is about to be upgraded, the current controller notifies the host to switch to a path provided by other controllers in the storage system, and the other controllers execute the data access service of the host, so that the data access service of the host can be upgraded within the upgrade waiting delay time of the current controller. And the host can continue to access the data without waiting for a long time, so that the service interruption time in the host is reduced.

The present application discloses a frame synchronization method, device, equipment, storage medium and program product, which belongs to the field of computer technology. The method includes: obtaining a predicted network delay time, the predicted network delay time is the predicted network delay time of a data frame; based on the predicted network delay time and the remaining display time, updating the display interval of the client, the remaining display time is the playback time corresponding to at least one cached display frame, and the display interval is used to indicate the time corresponding to playing the cached display frame in a single refresh; based on the display interval, the cached display frame is played to refresh the game screen. Through the above method, the problem of game screen freeze caused by network delay within a period of time can be effectively combated. In addition, the number of cached display frames in the client can be dynamically adjusted based on the predicted network delay time and the remaining display time corresponding to the cached display frame, thereby reducing the player's operation feedback delay.

The invention discloses a multi-channel output pulse synchronization device with adjustable delay time, which relates to the field of power systems. The invention comprises an FPGA, an SMA connector, a host computer, a serial communication terminal, and an output channel. The FPGA serves as a central controller, and a pulse trigger input from the SMA connector terminal is given to the FPGA, and the output of the FPGA is given to the output channel. The FPGA communicates with the host computer via the serial port to set the delay data in each channel register. When the FPGA receives an input pulse signal, it reads the delay data stored in the register according to the setting of the program, and outputs the pulse to the PIN pin of each output channel. The multi-channel output pulse synchronization device with adjustable delay time of the invention has an adjustable minimum accuracy of 52ps, and each channel can independently adjust the output delay time, and has strong controllability and adaptability.

A heel backer shaper comprises a case, a last-compressing ironing base, a last rotation mechanism, a shaping wheel, an automatic selector switch, and a footboard. One side of the upper half of the case is not closed. The last rotation mechanism is disposed on the upper half of the case. The last rotation mechanism comprises a cylinder and a rotary table; the rotary table is disposed at the top of the cylinder; the last-compressing ironing base is disposed on the top inner wall of the case and right faces the rotary table. During heel shaping, the heel backer shaper can adjust the operating performances, such as the position of the shaping wheel on a backer, knocking force, ironing temperature and delay time, according to the quality conditions of a shoe so as to acquire optimal shaping effect; during normal working, the heel backer shaper can operate in an automatic manner; an electrothermal plate on the last-compressing ironing base is controlled via a three-compartment closed-loop controlled silicon voltage regulator, temperature control precision is greatly improved, a temperature difference can be controlled within a 10 DEG C range, and the plane of the shaped backer is flat, with clear edge and smooth wrinkle-free surface.

The present invention is configured so as to be capable of executing a press start process for rotating a crank shaft that is stopped at a prescribed start angle and starting a downward movement of a slide, and an interference check process for determining, when the crank shaft reaches a prescribed interference check angle, whether or not the first conveyance device is in a die interference area in which the first conveyance device interferes with a die. The press start process is executed after a prescribed delay time has elapsed after the first conveyance device has loaded a workpiece into a press device. The delay time is set on the basis of a departure time required for the first conveyance device to depart from the die interference area after loading the workpiece, and a check angle movement time taken for the crank shaft to move from the start angle to the interference check angle, and is shorter than at least the departure time.

The invention relates to the technical field of electromechanical control testing, in particular to an electromagnetic valve action response time transition state multi-section sampling testing method, which comprises the following steps of S1, monitoring electromagnetic valve driving current in real time, and generating an initial trigger signal; s2, generating a first-stage sub-trigger signal and a second-stage sub-trigger signal; s3, the action process of the electromagnetic valve is divided into a delay stage, an acceleration stage and a stable stage, and synchronous sampling is carried out on each stage; s4, extracting an electromagnetic starting point from the sampling data in the delay stage, and extracting a mechanical action point from the sampling data in the acceleration stage; s5, calculating mechanical delay time and mechanical motion time; and S6, accumulating to obtain the total action response time of the electromagnetic valve. According to the invention, through a multi-stage triggering and synchronous sampling mechanism, accurate extraction and accumulation calculation of response time of each stage in the whole action process of the electromagnetic valve are realized, and the accuracy and reliability of response characteristic testing are remarkably improved.