769 results about "Delay time" patented technology

A communication system that achieves reduction in delay time or the like at the time of mobility includes: a base station that is applied to a fifth-generation wireless access system; and a communication terminal that connects to the base station. When a cell that is a connection destination of a communication terminal in communication via any one of a plurality of cells constituted by the base station is changed, the base station transmits, to the communication terminal, setting information for measuring communication quality in a physical layer of the cell, the communication terminal measures the communication quality in another cell different from a cell being connected based on the setting information received from the base station, and transmits a measurement result to the base station, and the base station determines a cell to be a new connection destination of the communication terminal based on the measurement result.

The invention provides an unmanned aerial vehicle visual servo intrusion target tracking and intercepting method based on time delay compensation. The method comprises the following steps: acquiring a latest image of a tracking target through a camera on an unmanned aerial vehicle; based on the latest image, determining the position of the tracking target in an image coordinate system of the latest image as a first position; determining a position error of the first position by adopting a prediction algorithm based on improved Kalman filtering based on the delay time of collecting the latest image; based on the position error, determining a control parameter used for visual servo tracking of the corresponding tracking target; and based on the first position and the control parameter, controlling the unmanned aerial vehicle to fly to track and intercept the corresponding tracking target. Therefore, the position error compensation is performed through the delay time of the latest image, and the unmanned aerial vehicle is controlled to track the corresponding target based on the position error, so that the tracking accuracy is improved, the tracking interception error is reduced, and the interception success rate is improved.

The embodiment of the invention provides a key delay test method and system, and the method comprises the steps: capturing a hardware interrupt signal generated by each physical key response in real time through simulating a preset operation event, measuring first delay time, and evaluating the first delay time according to a preset performance threshold value, analyzing existing potential external interference factors and potential system internal anomalies, adjusting initial test environment parameters, obtaining an optimized test environment, repeatedly simulating operation events, capturing hardware interrupt signals generated by response of each physical key, and calculating average delay time as a response characteristic index of the physical key; predicting the use reliability and the aging effect of the physical key by responding to the change trend of the characteristic index, and generating a trend analysis report; according to the technical scheme provided by the embodiment of the invention, the test precision and reliability are improved, a user can take preventive measures in advance, and service interruption or equipment damage caused by key faults is avoided.

The invention discloses an instruction scheduling method, device and system, a product and a medium, and relates to the technical field of processor design. The invention provides an instruction scheduling method aiming at the problem that the dynamic change in the instruction transmitting time cannot be accurately scheduled by the existing out-of-order scheduling strategy. The historical delay information of each instruction is stored through the delay cache, and when the instruction execution delay corresponding to the instruction is dynamic delay, the dynamic delay is predicted through the historical delay information stored in the delay cache, so that instruction scheduling is performed. According to the method, the dynamic delay of which the delay time cannot be predetermined is included in the consideration range of instruction scheduling based on the dynamic delay prediction mechanism. On the basis of the method, for dynamic change scenes in instruction transmission time such as memory access delay and cache miss, the optimal instruction transmission opportunity can be accurately predicted, so that the effect of instruction scheduling on performance improvement of a processor is further improved.

Method includes receiving a first delay time and a first timing measurement by a TMV from a first receiver at a first node. The first timing measurement is generated by comparing a first time associated with a first signal to a first local clock time. The first signal is transmitted by a transmitter at a source. The TMV receives from a second receiver at a second node in a network, a second delay time and a second timing measurement. The second timing measurement is generated by comparing a second time associated with a second signal to a second local clock time. The second signal is transmitted by the transmitter at the source. The TMV generates a correction factor time based on the first timing measurement, the first delay time, the second timing measurement, and the second delay time. The TMV transmits the correction factor time to the second node.

The invention discloses a PUF (Physical Unclonable Function) structure based on delay difference quantization, and the structure comprises a PUF circuit which comprises two time delay circuits which are connected in parallel; a plurality of layers of differential tapped circuits TDC, and decoders connected with each layer of differential tapped circuit TDC; the delay data quantization unit is connected with the multi-layer decoder, and the delay data quantization unit is connected with the LFSR confusion structure; the two delay circuits are connected with the multi-layer differential tap circuit TDC through the signal selection structure, the signal selection structure inputs delay signals which respond first and then respond in the two delay circuits into a start end and a stop end of each layer of differential tap circuit TDC, the decoder determines delay time of the two delay circuits under corresponding delay resolution, and the decoder outputs the delay time to the multi-layer differential tap circuit TDC. The delay data quantization unit is used for averaging the delay time under different time delay resolutions to serve as final delay data, and the final response R is output after the final delay data is confused by the LFSR confusion structure. Signals of the two symmetrical delay paths are respectively input into a framework of a multi-layer TDC quantization circuit, so that delay difference digital code quantization is realized.

A work load of a web server that is caused by sequence of requests sent by one or more client devices is reduced by blocking (such as discarding, delaying, or dropping) part of, or whole of, the requests in the sequence, so that the one or more client devices are not identified as causing a Denial- of-Service (DoS) attack or Distributed Denial-of-Service attack (DDoS attack). The blocking may be in response to metering, continuously or periodically, of a Round-Trip delay Time (RTT) to the web server, or metering a feature or amount of the sent sequence of requests, the received responses therefrom, or any combination thereof. The blocking may be in response to comparing the metered value to a threshold, or in response to a correlation between the metered values, where the blocking is performed in response to the metered value being above the threshold. The process may be repeated.

A method of selecting an accelerator includes, based on receiving a machine learning model, dividing the machine learning model into operations; verifying operation delay times of the operations for accelerators based on a delay timetable; and selecting, based on the operation delay times, one accelerator from among the accelerators per operation; and performing the operations by corresponding selected accelerators.

The invention discloses a simulation IC test method and system based on load transient response, and aims to improve the performance evaluation precision of a simulation IC under a complex load condition. The method comprises the following steps: firstly, acquiring transient response waveforms and response delay characteristics of an analog IC (Integrated Circuit) in various load jump modes, and constructing a mapping matrix between a load current step change rate and response delay time; in the real-time test, response delay time in a future preset time period is predicted according to the step change rate of the current load current. When the steady-state time window exists, a fixed sampling time sequence is set based on the window to generate a first test waveform; and if the steady-state window does not exist, correcting the transient waveform, and generating a compensated second test waveform. And then time sequence decomposition is carried out on the test waveform, and a load transient stability evaluation matrix is constructed, so that the dynamic performance of the simulation IC is accurately evaluated, and a detailed performance test report is output.

The invention provides an electronic detonator delay calibration method, which comprises the following steps of: starting a first timer based on a high-speed clock, and setting a first calibration time threshold value; synchronously starting a second timer based on a low-speed clock in the chip, and setting a second calibration time threshold value which is greater than the first calibration time threshold value; when the first timer reaches a first calibration time threshold value, stopping the second timer and acquiring an actual count value of the second timer; calculating a theoretical count value corresponding to the first calibration time threshold value; generating a calibration factor based on the ratio of the actual count value to the theoretical count value; dynamically correcting the low-speed clock count value corresponding to the target delay time according to the calibration factor; configuring a second timer by adopting the corrected count value, and executing delay control; by means of high precision of the high-speed clock, the low-speed clock is calibrated before detonation, so that the low-speed clock is more accurate in the current environment, the standard that the delay error is smaller than 1% is achieved, and it is guaranteed that the detonation time of the electronic detonator is accurate and errorless.

The invention provides a scene port entering and leaving aircraft joint optimization scheduling method. The method comprises the following steps: aiming at aircrafts which take off and land on a plurality of parallel runways in an airport, establishing a mixed integer programming model for a scene port entering and leaving aircraft IASP; setting a target function and a constraint condition of an IASTP problem by taking minimization of the total delay duration of the port entering and leaving aircrafts as a target; and based on the constraint conditions, solving a target function of the IASTP problem by adopting a heuristic algorithm based on VNS, and obtaining a comprehensive scheduling scheme of runway and sliding path distribution, take-off and landing sequence and time of the port entering and leaving aircraft. According to the method, actual operation constraints of various scenes are considered, runway distribution and sorting, taxiing path selection and taxiway scheduling of the port entering and leaving aircrafts, and a deducing sorting scheduling scheme of the port leaving aircrafts are planned and optimized as a whole, the take-off and landing delay time of the port entering and leaving aircrafts is shortened as much as possible, the hub airport operation efficiency is improved, and the airport landing time is shortened. And decision support is provided for efficient scheduling of aircrafts.

The invention provides a control method of a self-service washing machine door lock. The control method is applied to a server, and includes the following steps: the delay time of door opening sent bya client is received, wherein the delay time of door opening refers to the time after the washing process is finished; after a washing event is finished, whether the delay time of door opening expires or not is judged; if not, an unlocking instruction sent by the client is received, and a washing machine is controlled to open the door lock according to the instruction. According to the control method of the self-service washing machine door lock, washing machines in a washhouse can be efficiently utilized, and if users fail to take out clothes in time after washing is finished, the users needto reserve the delay time and pay for continued occupation of the washing machine.

A control method in a control device that controls movement of a plurality of moving bodies includes: moving the plurality of moving bodies in accordance with movement plans that have been predetermined and defining one or more passageways where each of the plurality of moving bodies passes from a departure place to a destination; acquiring an actual delay time that is a delay time of each of the plurality of moving bodies, the delay time being generated in each of the one or more passageways; updating a model representing a length of the delay time defined for each of the one or more passageways using the actual delay time in a corresponding passageway among the one or more passageways; acquiring a current location of each of the plurality of moving bodies; and updating each of the movement plans based on the updated model, the destination, and the current location.

The embodiment of the invention discloses a PWM signal generation method. The generation method comprises the following steps: determining setting delay time and reset delay time of an nth PWM delay signal, and determining a first comparison result of the setting delay time and a preset clock period and a second comparison result of the reset delay time and the preset clock period, and allocating a first delay time to the delay module and allocating a first comparison threshold to the first comparator according to the first comparison result, and allocating a second delay time to the delay module and allocating a second comparison threshold to the second comparator according to the second comparison result. According to the embodiment of the invention, the method does not need to depend on a high-precision clock chip, can achieve the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit, can achieve the delay of the duty ratio, can also achieve the delay of the signal period, is higher in time resolution, and is higher in precision. And more accurate and stable PWM signals can be output.

The invention discloses a data access switching method and device, and relates to the technical field of storage. In the data access process, the host and different controllers in the storage system establish different paths, and the host stores upgrade waiting delay time of the controller on the currently accessed path. Under the condition that a current controller transmitting a data access request of a host in the storage system is about to be upgraded, the current controller notifies the host to switch to a path provided by other controllers in the storage system, and the other controllers execute the data access service of the host, so that the data access service of the host can be upgraded within the upgrade waiting delay time of the current controller. And the host can continue to access the data without waiting for a long time, so that the service interruption time in the host is reduced.

A heel backer shaper comprises a case, a last-compressing ironing base, a last rotation mechanism, a shaping wheel, an automatic selector switch, and a footboard. One side of the upper half of the case is not closed. The last rotation mechanism is disposed on the upper half of the case. The last rotation mechanism comprises a cylinder and a rotary table; the rotary table is disposed at the top of the cylinder; the last-compressing ironing base is disposed on the top inner wall of the case and right faces the rotary table. During heel shaping, the heel backer shaper can adjust the operating performances, such as the position of the shaping wheel on a backer, knocking force, ironing temperature and delay time, according to the quality conditions of a shoe so as to acquire optimal shaping effect; during normal working, the heel backer shaper can operate in an automatic manner; an electrothermal plate on the last-compressing ironing base is controlled via a three-compartment closed-loop controlled silicon voltage regulator, temperature control precision is greatly improved, a temperature difference can be controlled within a 10 DEG C range, and the plane of the shaped backer is flat, with clear edge and smooth wrinkle-free surface.

The invention relates to the technical field of electromechanical control testing, in particular to an electromagnetic valve action response time transition state multi-section sampling testing method, which comprises the following steps of S1, monitoring electromagnetic valve driving current in real time, and generating an initial trigger signal; s2, generating a first-stage sub-trigger signal and a second-stage sub-trigger signal; s3, the action process of the electromagnetic valve is divided into a delay stage, an acceleration stage and a stable stage, and synchronous sampling is carried out on each stage; s4, extracting an electromagnetic starting point from the sampling data in the delay stage, and extracting a mechanical action point from the sampling data in the acceleration stage; s5, calculating mechanical delay time and mechanical motion time; and S6, accumulating to obtain the total action response time of the electromagnetic valve. According to the invention, through a multi-stage triggering and synchronous sampling mechanism, accurate extraction and accumulation calculation of response time of each stage in the whole action process of the electromagnetic valve are realized, and the accuracy and reliability of response characteristic testing are remarkably improved.

The invention provides a knob dimming method which comprises the following steps: S1, when a falling edge is detected in each interruption of a program, performing input falling edge interruption on a pin A, and then starting a timer; s2, judging whether the timing time of the timer is up or not, if not, returning to S1, and if so, reading the signal level of the pin A; and S3, judging whether the signal level of the pin A read in S2 is a low level or not, if not, returning to S1, and if so, judging that the level of the pin A is valid. According to the invention, the effective level can be rapidly obtained after the level recovers to be stable, the maximum delay time or pulse period is not measured again by means of device replacement, the knob level is read by dynamically setting timing, misjudgment is greatly avoided, and in addition, the problem of pulse signal counting coverage caused by rapid rotation of the knob is also solved.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generator and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.

The invention discloses a motor control digital circuit and a driving system, and the circuit comprises a first delay time sequence module which transmits a secondary delay pulse to an acceleration and deceleration synchronization module based on a synchronization signal and delay time; the acceleration and deceleration synchronization module obtains path input after receiving the secondary delay pulse, and selects acceleration and deceleration path write-in and acceleration and deceleration position write-in sent to the acceleration and deceleration module; the stepping direction selection module receives the stepping and direction signals of the acceleration and deceleration module and the stepping and direction signals of the distance compensation module, and outputs stepping control and direction control of the motor according to the stepping direction selection signals; and the absolute position module outputs an absolute position based on stepping control and direction control of the motor. A synchronous control function and an absolute position function are added into an existing acceleration and deceleration function, so that a user can freely switch among three modes of acceleration and deceleration, synchronous acceleration and deceleration and distance compensation, an original complex algorithm is realized through a digital circuit, and the working efficiency and the integration degree are improved.

The invention provides a phased array ultrasonic interface debonding detection method for a multilayer curved surface bonding structure, which comprises the following steps of: accurately calculating delay time of each array element in a phased array ultrasonic probe to a target focus by designing a delay block attached to a solid engine and aiming at a cylindrical special structure; therefore, in-phase superposition of sound waves at the target focus is achieved, focusing of sound beams is achieved, the problem of delay time calculation of sound waves emitted by all array elements of a phased array probe of a cylindrical structure is solved, and the problem of control over the deflection angle and the focusing depth of the sound beams synthesized after the sound waves pass through a plurality of curved surface interfaces is solved. Accurate positioning and visual representation of the debonding defect of the deep interface are realized. The technology provides a new technical means for accurately judging the interface debonding defect, and has important significance for guaranteeing the structural integrity and the use safety of the interface debonding defect.

The invention is suitable for the technical field of evaluation of external impact response capability of an airport, and provides an airport flight time toughness index calculation method, which comprises the following steps of: obtaining delay time sequences of a flight plan time in a certain season and an actual execution time in different days in a certain period of time; identifying the mode characteristics of the delay time sequence of a certain flight plan moment in the period of time; dividing the period of time of a certain flight plan moment into a plurality of periods, and identifying a flight delay normal stage, a delay increase stage, a stable delay stage and a delay decrease recovery stage of each period; calculating a normality index, a resistance index, a robustness index and a restorability index of a certain flight time in the period of time; and dynamically evaluating the toughness index of a certain flight time in the period of time. The method provides theoretical basis and decision reference for airport flight time delay prevention and control, recovery and toughness level improvement under different random interferences, thereby providing data support for reasonable planning and adjustment of flight time resources.

Embodiments of the present disclosure provide a message processing method, a cloud platform, a computing device, a computer readable storage medium, and a computer program product. The method comprises: acquiring a first timed message; on the basis of a current delay time of the first timed message, searching for a first storage file corresponding to a first time dimension to which the current delay time belongs, wherein the current delay time refers to a delay processing time of the first timed message relative to a current time point, and a plurality of mutually independent storage files are correspondingly set for each level of time dimension; and writing the first timed message into the first storage file. On the basis of the current delay time of the first timed message, the first storage file is searched for in the order of levels of time dimensions from low to high, so as to store timed messages according to time dimensions and expand the time range for storing the timed messages; and by writing the first timed message into the first storage file, the timed messages can be sequentially read on the basis of storage files, thereby improving the delivery efficiency of the timed messages.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

To provide a signal processing device, a control method for the signal processing device, and a program capable of synchronizing time information with sound signals even when the sound signals do not contain time codes.SOLUTION: A signal processing device includes: signal processing means for processing a sound signal; measuring means for measuring a delay time caused by signal processing by the signal processing means based on first time information output from timing means and second time information output from the signal processing means; and synchronizing means for synchronizing the time information output from the timing means with the sound signal processed by the signal processing means based on the delay time measured by the measuring means.SELECTED DRAWING: Figure 1

The invention relates to the technical field of equipment communication management, in particular to a signal processor access method and computer equipment, and the method comprises the steps that in response to system power-on, a first controller sets an access enable signal to be in an invalid state so as to limit a management controller to access a signal processor; obtaining the model of the signal processor, and determining fixed delay according to the model of the signal processor; starting timing in response to detection of completion of loading of the signal processor; acquiring environmental parameters of the signal processor and determining compensation delay according to the environmental parameters; determining target delay according to the fixed delay and the compensation delay; triggering the management controller to access the signal processor in response to the arrival of the target delay time; through the method, the chip access timeliness can be improved, and the chip communication interruption influence range can be reduced.

To provide a program production system that measures a delay time of a video image with respect to audio and auxiliary data by a simple method so as to realize synchronization among the video image, the audio and the auxiliary data generated at the same time.SOLUTION: The video time difference calculating unit 11 - 1 of the video delay measuring apparatus 2 extracts the time stamp V1 from the video RTP packet VTS1 and generates the video RTP packet V2 including the timing information. The video RTP packet V2 is transmitted to the video delay time difference measuring path. A video time difference calculation section 11-1 extracts a time stamp V3 from a video RTP packet VTS2 to obtain a video time difference VT. The audio time difference calculator 11-2 obtains the audio time difference ST, and the ancillary data time difference calculator 11 - 3 obtains the ancillary data time difference AT. The delay time calculating unit 13 subtracts the audio time difference ST from the video time difference VT to obtain the audio delay time SD, and subtracts the ancillary data time difference AT from the video time difference VT to obtain the ancillary data delay time AD.SELECTED DRAWING: Figure 5

The invention discloses an implementation method of a high-precision time-to-digital converter, and relates to the technical field of time mode signal processing. The delay chain comprises a Start signal channel and a plurality of Stop signal channels, each delay chain corresponds to one channel, each delay chain is formed by cascading a circuit with a delay function as a delay unit, the chain structure is divided into an integral chain and a differential chain, the integral chain is that one channel corresponds to one independent delay chain, and the differential chain is that one channel corresponds to one independent delay chain. The difference chain regards two delay chains corresponding to two adjacent channels as a group, and the time difference of signals reaching the input ends of the two delay chains is maintained for 1 / 2 of the delay duration of a single-stage delay unit through a back-end constraint physical layout wiring rule, so that difference is formed. According to the invention, the maximum time resolution of TDC can reach about 12ps, and the test precision is lt; and the dynamic range is about 67 ms, so that high-precision time interval measurement capable of being dynamically calibrated is realized.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.