31 results about "Reference counting" patented technology

In some implementations, a computer system includes one or more processors and a non-transitory computer-readable medium storing programming for execution by the one or more processors. The programming includes instructions to receive a request to create a second air-gapped backup corresponding to a second transient backup. The second transient backup is subsequent to a first transient backup corresponding to a first air-gapped backup. The programming includes instructions to determine, in response to the request, whether the second transient backup matches the first transient backup, and to create, in response to determining that the second transient backup matches the first transient backup, a database entry for the second air-gapped backup that references the first air-gapped backup. The programming includes instructions to increment, in response to determining that the second transient backup matches the first transient backup, a reference counter for the first air-gapped backup.

In some implementations, a memory apparatus may receive a command to write data to volatile memory of the memory system. The memory apparatus may compare the data to one or more data patterns to identify whether the data matches a data pattern of the one or more data patterns. The memory apparatus may increment a reference counter associated with the data pattern based on identifying that the data matches the data pattern. The memory apparatus may write, based on identifying that a measure flag associated with the data pattern is set, the data to the volatile memory.

The invention discloses a GPU dynamic memory resource management method and system based on time sequence historical analysis. According to the method, a CUDAAPI function during running of a deep learning model is intercepted, and an execution history table containing a kernel execution sequence, a memory block size and an address is generated. By comparing two latest execution history tables, calculating a consistency ratio to judge whether a memory access mode is stable or not, so that a memory prefetch strategy is started; and when the GPU memory is insufficient, the memory blocks are exchanged to the CPU memory based on an expelling strategy of reference counting, so that sufficient GPU memory can be available during kernel execution. The system comprises a memory extraction module, a prefetching module and a dynamic decision module, supports dynamic asynchronous memory exchange, and optimizes GPU memory utilization efficiency. The method is suitable for deep learning model training in a GPU memory resource limited environment, a larger-scale deep learning model and training batches can be supported on the GPU with the same configuration, memory waste is reduced, and operation performance is improved.

The present disclosure relates to a request-level consistency control method and system for dynamic configuration hot update. The method comprises: organizing configuration content into multiple versioned configuration snapshots, establishing a corresponding reference count for each versioned configuration snapshot, and setting a candidate version; enhancing a configuration reading path in a service node by plugging so as to be able to perform a configuration reading operation according to a bound version; in response to receiving a service request, creating an activation token for the service request, obtaining a current candidate version as the bound version, writing the bound version into the activation token, and increasing the reference count of the bound version; during processing of the service request, when configuration needs to be read, reading a configuration value from a corresponding versioned configuration snapshot according to the bound version in the activation token; and in response to the processing of the service request being completed, decreasing the reference count of the bound version by one.

The embodiment of the invention provides a dynamic shared memory control method and device, a medium and a program product, and relates to the technical field of databases. The method comprises the following steps: setting an initial reference count and an initial fixed mark of a dynamic shared memory block; updating the reference count and / or the fixed mark according to the association operation or the disassociation operation of the process on the dynamic shared memory block; under the condition that the reference count is a first preset value and the fixed mark is in a first state, the operation of releasing the dynamic shared memory block is triggered, the first preset value is a preset reference count threshold value used for triggering the memory release operation, and the first state is a preset fixed mark state used for triggering the memory release operation. Based on the method, high flexibility and safety can be taken into account, so that the dynamic shared memory block is flexibly and safely released, and the requirements in an actual application scene are met.

A system can maintain a copy-on-write b+ tree for a data storage system that is configured to store data as chunks, and a mapping between tree page identifiers of the b+ tree and first in-use chunk identifiers. The system can perform reference count validation, comprising iterating over the mapping, wherein the iterating over the mapping comprises, based on a first tree page identifier of the tree page identifiers being present in the mapping, loading second in-use chunk identifiers that correspond to the first tree page identifier directly from the mapping; and based on the first tree page identifier of the tree page identifiers being absent, loading corresponding content, extracting third in-use chunk identifiers from object metadata of the content, and updating the mapping based on the third in-use chunk identifiers, to produce an updated mapping. The system can perform garbage collection of the data storage system based on the validation.

Embodiments of the present application disclose a reference counting method and a related apparatus. The method comprises: acquiring an idle target data block from a storage space; establishing a plurality of counters in the target data block, the number of the plurality of counters corresponding to the grouping situation of a plurality of cores of a central processing unit (CPU); in response to a Pin / Unpin operation performed on the target data block, determining a target core corresponding to the Pin / Unpin operation, the target core belonging to the plurality of cores; on the basis of the target core, determining a corresponding target counter, the target counter belonging to the plurality of counters; and performing, by means of the target counter, reference counting corresponding to the Pin / Unpin operation. The method can be used for increasing the speed of Pin / Unpin on a multi-core CPU, thereby improving the overall performance of a system.

This application discloses a reference counting method and related apparatus. The method includes: acquiring a free target data block in storage space; establishing multiple counters in the target data block, the number of counters corresponding to the grouping of multiple cores of a central processing unit (CPU); determining the target core corresponding to the pin / unpin operation in response to a pin / unpin operation on the target data block, wherein the target core belongs to multiple cores; determining the corresponding target counter based on the target core, wherein the target counter belongs to multiple counters; and performing reference counting corresponding to the pin / unpin operation using the target counter. This method can be used to improve the speed of pin / unpin on multi-core CPUs, thereby improving the overall system performance.

The present application belongs to the technical field of machine learning, and particularly relates to an inference service system and method supporting multi-model hybrid deployment. A plurality of inference instances and a scheduler are communicatively connected, and each inference instance is configured with a local storage space for caching model weight files. The scheduler analyzes a model set required by an inference request, and the local cache state and load condition of each inference instance, intelligently assigns the request to an optimal target inference instance; the target inference instance uses a dynamic downloading mechanism for a model not stored locally, and directly obtains a local model path through the cache for a locally stored model; and fine cache life cycle management is realized through reference counting and LRU strategy, so as to combine cache-aware scheduling and dynamic model loading, solve the problem that a traditional single-instance single-model deployment mode cannot well support multi-model hybrid deployment, and realize efficient use of resources and rapid response of requests.

An apparatus includes a processing means configured to maintain a deduplicated data structure including sub-sections of data block identifiers associated with different compression ratio ranges and having different numbers of data block identifiers. The processing means is further configured to identify a given data block identifier and a given compression ratio for a given data block to be stored, and to determine whether the given data block identifier is in a given sub-section having a given compression ratio range including the given compression ratio. The processing means is further configured to write the given data block to a physical space block of a storage system in response to determining that the given data block identifier is not in the given sub-section, and to increment a deduplication reference count of the given data block identifier in response to determining that the given data block identifier is in the given sub-section.

In some implementations, a memory apparatus may receive a command to write data to volatile memory of the memory system. The memory apparatus may compare the data to one or more data patterns to identify whether the data matches a data pattern of the one or more data patterns. The memory apparatus may increment a reference counter associated with the data pattern based on identifying that the data matches the data pattern. The memory apparatus may write, based on identifying that a measure flag associated with the data pattern is set, the data to the volatile memory.