40 results about "Lower priority" patented technology

A processing system including processing cores, a shared memory, a shift table that stores a maximum number of reservations to locations in the memory, and an exclusive monitor that uses the shift table and an eviction policy to enforce core synchronization. The eviction policy is based on priority, age of valid reservations, shift table fullness state, and reservation memory conflict. The shift table may include a memory address and a size value indicative of a flexible amount of reserved memory at the memory address. The exclusive monitor evicts an oldest reservation in the shift table having a same or lower priority level as the new reservation. The exclusive monitor rejects the new reservation when the shift table is full of higher priority reservations. Reservations are shifted to maintain age status. Stale reservations may be invalidated or have their priority lowered. Conflicting reservations may be made with the same priority level.

The application provides a lightweight log generation method, system and electronic equipment, and relates to the technical field of computer software.The method comprises the following steps: creating a running log management task and an operation log management task with lower priority than an application task, and establishing a message queue; when a log event is generated by the application task, a formatted log message containing a timestamp, a log level, a module identifier and content is generated and sent to the message queue; the log management task asynchronously acquires the log message, and distributes the log message to a running log folder or an operation log folder according to the log level and type; and the size of the log file is monitored, and when the capacity threshold is reached, a cover writing mechanism is enabled to recycle the file storage area.The application realizes asynchronous decoupling of log recording and the application task, supports hierarchical classified storage and cyclic coverage, significantly improves the maintainability and debugging efficiency of the embedded system while ensuring real-time performance, and meets the lightweight log demand in a resource-limited environment.

The application provides a GPU Warp scheduling method and device based on a chessboard scheduling strategy, and the method comprises the following steps: a stream multiprocessor assigns a Warp number to each task of different task types received through a facing Warp numbering mechanism, the priority of each Warp is determined according to the task type and the Warp number, the Warp with high priority is preferentially executed, if the current Warp execution is overdue, the priority of the Warp is dynamically adjusted, and the Warp with low priority is executed in turn. The facing Warp numbering mechanism is used to realize the priority ordering of the Warps of different task types, and the dynamic priority adjustment mechanism based on the execution time threshold can guarantee that the high-priority task is preferentially executed, also take into account that the low-priority task can be executed in a hidden manner, ensure fairness, and improve resource utilization.

Methods, systems, and devices for increased file loads using file based optimization (FBO) and prefetch within a memory system are described. A system may support using a prefetch command to prioritize prefetching for artificial intelligence (AI) related data (or other high priority data). A host system may transmit a prefetch command for the AI-related data before performing one or more AI operations that use the data. In response, the memory system may prefetch the AI-related data and store the data in a cache. The storage of the AI-related data in the cache may be prioritized over other data types associated with lower priorities. The host system may transmit an FBO command to defragment the AI-related data in the memory system prior to the prefetch, which may reduce latency of the prefetch.

This invention discloses a collaborative scheduling method, device, and medium for decoupling parameters and computation, applied to an AIGC inference system containing at least one computing node. The method includes: receiving a user inference request, the inference request indicating a target model; in response to determining that computing resources need to be allocated to the target model, performing a resource allocation operation on the target computing node based on a preset collaborative tidal scheduling strategy, the resource allocation operation including an atomically executed ebb and flow operation; wherein: the ebb operation includes: releasing computing resources on the target computing node that have been allocated to one or more low-priority tasks; the flow operation includes: allocating the released computing resources to the target model to process the user inference request. This invention enables high resource utilization, low-latency model switching, and intelligent resource scheduling for AIGC inference services.

This invention provides a quantitative assessment method for nuclear power equipment data quality, comprising: acquiring multiple business objects in the nuclear power production field; ranking each business object by importance to obtain high-priority, medium-priority, and low-priority business objects; determining quality assessment rules according to the business objects in descending order of priority; verifying the data corresponding to the business objects according to the quality assessment rules to obtain quality problem records; classifying and judging the quality problem records to determine and output the corresponding level of each quality problem record; acquiring the rectified data corresponding to the quality problem records; verifying the data quality and determining compliance of the rectified data to obtain a compliance confirmation result. This invention achieves a quantitative and systematic assessment of nuclear power equipment data quality through priority ranking, six-dimensional quality assessment, graded judgment, and closed-loop rectification.

The application provides a security policy matching method and device, a storage medium and a computing device. When any security policy tree is constructed, a node priority is set for each tree node, which can accurately reflect the highest policy priority of the subordinate sub-tree of each tree node, thereby providing a core basis for pruning low-priority nodes during security policy matching, ensuring the order of dynamic maintenance of the node priority, and improving the security policy matching efficiency. Furthermore, the early stop attribute is set for the security policy of the leaf node in the multi-security policy tree in stages, which realizes the fast marking of the absolute high-priority security policy and the accurate marking of the non-absolute high-priority security policy without intersection, and the combination of the two realizes the accurate setting of the early stop attribute of the security policy. In this way, the large-scale security policy matching efficiency is improved, the optimal matching result is ensured, the computing cost is reduced, and the matching performance of the security policy tree is significantly improved.

This invention discloses a multi-priority hardware timer in the field of real-time applications, comprising a timer unit and a priority control unit. The timer unit includes a timing module and multiple comparison registers. The timing module and each comparison register constitute a hardware timer, and an interrupt signal is generated when the value in the timing module is greater than or equal to the value in the comparison register. The priority control unit includes an interrupt arbitration module, a low-priority mask register, a timing enable register, a timer ID register, and a priority configuration register. The timing enable register enables the timing module. The priority configuration register is used to configure the priority of the comparison registers. The low-priority mask register is used to mask low-priority interrupt signals. The interrupt arbitration module is used to arbitrate the interrupt signals of the hardware timer. After interrupt arbitration, the content of the timer ID register is updated to the ID number of the highest-priority hardware timer, and the interrupt signal is forwarded to the processor.

Disclosed is an approach to autonomously abort a lower priority transaction that is blocking a higher priority transaction, where the lower priority transaction is holding a lock on a resource for which there is contention. Some approaches also provide an efficient way to implement identification of a blocker transaction, which drastically reduces the response time to abort the blocker transaction.

The disclosure relates to a fifth generation (5G) or sixth generation (6G) communication system. Embodiments herein disclose methods for maintaining priority of a VPLMN during a PLMN selection procedure by a UE. The method includes ignoring a pre-configured priority for a VPLMN and considering the VPLMN as a lowest priority in response to determining that the UE has entered a state and the second SOR information is not received before the UE enters the state or the received second SOR information security check is not successful. The method includes considering a priority of the VPLMN as the pre-configured priority by not considering the VPLMN as a lowest priority and stopping the timer associated with the “first SOR security check not successful” in response to determining that the UE receives the second SOR information and a second SOR security check is successful before the UE enters the state.

The application provides an SDN controller multi-stage orderly closing method and device, including: setting the state of a node to be closed to a DRAINING state, activating a folding priority queue and low priority task preemption module; in the DRAINING state, switching the folding priority queue from a first comparator based on task priority value ordering to a second comparator through an atomic replacement comparator, and only scheduling the highest priority task; when a working thread executing a low priority task executes to a safe breakpoint, migrating the low priority task to other nodes and releasing the working thread for executing the highest priority task; after all the highest priority tasks are executed, performing a closing operation on the node to be closed. The application can guarantee task migration data consistency and reduce end-to-end scheduling delay of high priority tasks in the DRAINING state.

A management device includes processing circuitry configured to perform arbitration processing when the processing circuitry receives a plurality of requests, and to activate an actuator based on a request value of a selected request in the arbitration processing. When a low-priority request with a low-priority flag turned on is included in the received plurality of requests, the low-priority flag indicating a priority lower than other requests, the processing circuitry excludes the low-priority request from an arbitration target in the arbitration processing when the low-priority request is a request that can be implemented without control of the actuator. The processing circuitry does not exclude the low-priority request from the arbitration target in the arbitration processing when the low-priority request is a request that is implemented by controlling the actuator.

This control device (20) comprises a control unit (21) that transmits a GCL (11) defining a plurality of time slots and a fixed transmission period flow that passes through a corresponding port in each time slot, to a transfer device having the corresponding port. When, in accordance with the GCL (11) transmitted to at least one transfer device having a first port and a second port, a frame of a first flow of the fixed transmission period is being transmitted from the first port and a frame of a second flow having a lower priority than the first flow is being transmitted from the second port, if a failure of the first port is detected, the control unit (21) controls the at least one transfer device to cause the frame of the first flow to be transmitted from the second port.

This application provides a method and system for preventing task starvation. The method includes: acquiring a set of tasks in kernel mode that hold critical section resources awaiting high-priority tasks; performing execution flow truncation on the tasks in the task set, including: dynamically counting based on the length of the critical section release instruction, determining the address of the core execution instruction for critical section release corresponding to the task, constructing the minimum kernel stack of the task, and modifying the program counter pointer and stack pointer of the task to interrupt the original execution flow of the task; and performing targeted release of critical section resources of the task after execution flow truncation based on the dynamic counting of the length of the critical section release instruction. By separating the task execution flow from the resource release operation, this application enables low-priority tasks to release critical section resources without being dependent on the advancement of their own complete business logic, thus achieving batch release of resources for multiple low-priority tasks holding different critical section resources.

A priority based prefetch by a memory controller is disclosed. A prefetch of data of a low priority master is suspended when a data request associated with a high priority master indicated by a master identification is to be performed. The suspension includes storing a saved state of the prefetch, performing the prefetch of data of the high priority master, and resuming the prefetch of data of the low priority master when the prefetch of data of the high priority master is completed.

This invention relates to the field of computer programming technology, and in particular to a resource interception and dynamic adaptation method, system, electronic device, and medium. The dynamic resource loading management method includes: when the application starts, obtaining relevant information about the corresponding resource package; setting interceptors on the resource call path; when a resource call request is detected, parsing the request and obtaining the information of the resource to be called; obtaining current environment information and comparing it with preset environment information; if they are inconsistent, generating a path list including resource search paths sorted by priority based on the relevant information, the information of the resource to be called, and the current environment information; traversing the path list from high to low priority; if a resource can be obtained, it is used as the target resource and traversal stops; reading the binary data stream of the target resource, parsing it into an application-adaptive format, and returning it to the requester. This invention can simultaneously meet the application's dual requirements for architectural compatibility and intelligent resource adaptation.

The application discloses a data communication method and device based on a core isolation architecture, equipment and a medium, and belongs to the technical field of multi-core heterogeneous data communication. The method comprises the following steps: acquiring uploaded data packets through a first data processing core, classifying each data frame according to an instruction type identifier and a file type identifier configured for each data frame, writing an instruction frame carrying the instruction type identifier into a high-priority queue, and writing a file frame carrying the file type identifier into a low-priority queue; reading the instruction frame in the high-priority queue through a second data processing core and sending the instruction frame to an embroidery machine; and when it is determined that the high-priority queue has been emptied, reading the file frame in the low-priority queue and sending the file frame to the embroidery machine. Through the core isolation architecture between the first and second data processing cores, the application not only meets the quick response requirement of the control instruction frame of the embroidery machine, but also meets the efficient transmission requirement of the file frame, and can adapt to the operation requirement of the high-precision and high-efficiency embroidery machine.

The application discloses a method for constructing a MAC protocol of a UAV network, a transmission process of data packets with different priorities is modeled by a finite state Markov chain, and a cross-level priority promotion mechanism based on failure counting is introduced. The method aims to solve the problem of long-term blocking of low-priority services caused by traditional fixed-priority protocols in post-disaster emergency communication scenarios, thereby improving the overall throughput, reducing the average delay, and enhancing the fairness among multiple types of services while ensuring the strict service quality of high-priority services.

The application relates to a network traffic dynamic control method and system based on priority scheduling, which comprises the following steps: collecting real-time network traffic data packets and extracting real-time traffic feature vectors, generating a queue based on initial priority weight matching of a historical database; obtaining a basic dynamic adjustment factor by calculating a real-time load state, and generating a timeout risk compensation value according to the proportion of the queuing waiting time and the protocol timeout threshold of low-priority data packets, and superimposing the two to obtain a target priority weight; generating a scheduling instruction set according to the weight proportion and distributing the scheduling instruction set to network equipment for execution; finally, extracting an actual transmission delay according to the returned performance log, calculating the deviation value of the actual transmission delay and an expected delay to generate a weight update parameter, and feeding back the weight update parameter to the historical database to update the matching logic. The application takes into account the global link load balancing and the timeout retransmission risk prevention and control of low-priority traffic, and realizes the precision and adaptive dynamic optimization of the network traffic scheduling strategy.

A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

A wireless transmit / receive unit (WTRU) may comprise a processor. The processor may be configured to handle data collection procedures, wherein the data has more than one priority associated with it. For example, the WTRU may be configured to collect data for a first data collection and a second data collection, wherein the first data collection is associated with a first priority and the second data collection is associated with a second priority. The WTRU may make and store measurements for each data collection. The WTRU may store the measurements in a buffer and may mark the data with the appropriate priority. The WTRU may detect when the buffer is full and perform buffer management, for example, by deleting data of lower priority, and / or reporting data.

The application relates to the technical field of data platform scheduling control, cloud native resource arrangement and intelligent operation and maintenance, and discloses a high-concurrency heterogeneous computing power preemptive scheduling method and system based on an internalized intelligent agent. The method receives standardized event loads, identifies emergency fault tasks based on a composite emergency judgment rule, executes suspension, freezing or checkpoint saving on low-priority tasks, recycles and remaps heterogeneous resources such as video memory slices, execution queues, cache areas and high-speed interconnection channels, and generates a treatment result in combination with an open diagnostic model; meanwhile, recovery, feedback and preemptive scheduling audit objects are made explicit under the constraints of a tenant security namespace and a resource isolation boundary.

This application provides a task scheduling method and electronic device, relating to the field of computer technology. It can improve the utilization efficiency of scheduling resources in a multi-core processing system and increase task processing speed. For example, in a vehicle intelligent driving scenario, when a high-priority task such as collision warning is activated, it can quickly locate the core currently running the lowest-priority task and send a targeted notification, allowing high-priority safety tasks to be executed first, thereby ensuring driving safety. The task scheduling method includes: in response to the activation of a first task on a first core in the multi-core processing system, determining a second task; the second task is the lowest-priority task among all running tasks in the multi-core processing system; if the priority of the first task is greater than the priority of the second task, and the first task is not bound to a first core, controlling the first core to send an inter-core interrupt to the second core in the multi-core processing system, where the second core is the core running the second task.

The application discloses a kind of intelligent network card abnormal flow real-time monitoring and defense method and system based on light model, benchmark abnormal detection model is executed to forward load sensing compression, each layer of model is divided into micro-computing block according to computing amount, and the execution time of each micro-computing block does not exceed the preset quantile value of packet processing gap duration distribution, using hardware flow table matching engine, traffic is pre-screened into three levels of trusted release, high-risk block and detection, maintain inference state context for detection data stream, and execute micro-inference in packet processing gap stage by stage, trigger graded defense action according to abnormal probability score, drift detection is scheduled as low-priority microtask in gap and triggers incremental update when divergence value is out of limit.The application realizes abnormal flow real-time detection and active defense under the premise of guaranteeing line-speed forwarding.

The embodiment of the application relates to the technical field of communication, and provides a flow detection method, a node device and a flow detection system, for an entry node device, two ACL entries with different priorities are configured on a switching chip in advance, the ACL entry with a high priority and the ACL entry with a low priority are respectively associated with odd measurement periods and even measurement periods of flow detection, a processor controls the ACL entry with the high priority to be in an activated state only in the odd measurement periods, and controls the ACL entry with the low priority to be in an activated state all the time, after receiving a traffic message, the switching chip identifies a target traffic message through the ACL entry with the high priority if the current is in the odd measurement period, and identifies the target traffic message through the ACL entry with the low priority if the current is in the even measurement period; in this way, by alternately using the two ACL entries with different priorities and cooperating with a periodic switching mechanism, zero-packet-loss measurement in switch flow detection can be realized without increasing hardware burden.

A verification method and system for connecting a single-port SRAM module by a double AHB interface, comprising the following steps: step 1, judging the rising edge of the AHB clock; step 2, obtaining the state of the transmission start signal and the delay signal, and judging whether there is a data transmission operation; step 3, judging whether the temporary storage queue Q is empty; step 4, temporarily storing or performing data operation when the temporary storage queue is empty; step 5, if the temporary storage queue Q is not empty, taking out the information of the temporary storage queue Q, and then directly entering step 6 when the AHB interface operation is performed; step 6, performing the read-write operation of the high-priority and low-priority AHB interface on the simulation model and verifying the result. By setting the high-priority and low-priority read-write agent modules, the present application simulates the simultaneous operation of multiple AHB interfaces on the single-port SRAM by test cases, realizes the verification of the double AHB interface read-write single-port SRAM, and improves the reliability of the verification.

Methods and systems of using an approximate duplicate event filter are disclosed. Event processing systems of a service provider network such as a security service may receive a large volume of events to analyze. Events that have previously occurred can be given a lower priority for analysis than new events. Events that are similar to previous events can likely also be given a lower priority for analysis. These non-exact match events can be detected by comparing token representations of new events to token representations of previous events. Events may be considered according to the context in which the events occur.

The application discloses an application exception automatic isolation method, system, medium and equipment, and belongs to the technical field of power grid dispatching. The method comprises the following steps: if any exception exists in the basic hardware and software exception flag, the node platform layer and application layer exception flag, and the cross-node platform layer and application layer exception flag, the application is set to a fault state and is automatically isolated; when the application returns to normal, the application priority is reduced to the lowest priority; when the application data of the current node and the application host node data are inconsistent or the operating system basic hardware and software index of the node where the application is located is in a warning state, the application priority is reduced to the lowest priority; and when the application stably runs for a preset time interval, the application data of the current node and the application host data are consistent, and the operating system basic hardware and software index is not in the warning state, the initial preset priority is restored. The application solves the problems that the application fault isolation is not complete, the system is prone to jitter, and the system cannot be smoothly recovered in the prior art.