The invention relates to an optimization scheme for an intermediate layer architecture of a 2.5 D multi-core-particle integrated
system, and aims to improve the communication efficiency among core particles and improve the expandability of the multi-core-particle integrated
system. The invention provides an intermediary layer architecture based on a routing-free network, which is used for replacing a traditional network-on-
chip (NoC) solution based on a
router on an intermediary layer. According to the architecture, the core particles are connected through the well-designed loop structure, so that the complexity and
power consumption of the
router are eliminated, the communication
delay among the core particles is reduced, and the
data transmission efficiency is improved. The partition construction method provided by the invention can effectively optimize intermediary layer wiring and ensure efficient communication between the core particles.
Hardware structure design is simplified, an injection module, a pop-up module, an input module, an output module and an expansion buffer area module are included, and efficient transmission of data packets is achieved through a pre-calculated
routing table. The scheme has the advantages of excellent expandability,
low delay, low
power consumption and the like, and can support integration of more core particles.