72 results about "Exclusive access" patented technology

A method for creating and exchanging tokenized assets combines a dual ownership structure with a tiered exchange system. The method involves issuing membership non-fungible tokens to cooperative members, creating a tokenized asset through a legal entity and property ownership non-fungible token, and implementing a smart contract to generate property tokens representing fractional ownership. The exchange system for these property tokens implements sequential buying windows, providing initial exclusive access to non-token holders, followed by access to regional cooperative members, then global cooperative members, and finally institutional buyers. This approach may promote progressive decentralization of ownership while maintaining secure blockchain-based transfers within the cooperative framework. The method may enable fractional ownership of various assets, automated distribution of benefits, and a controlled secondary market structure that balances liquidity provision with ownership diversification.

Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.

An access method of exclusive equipment is applied to the technical field of computers. In the access method of the exclusive equipment, aiming at a scene with two independent operating systems, an access request which is sent by an application program in a first operating system and aims at the exclusive equipment is converted into an auxiliary access request sent to an application program in a second operating system; requesting an application program in the second operating system to assist in accessing the exclusive equipment; moreover, a controller is arranged in the second operating system to control the exclusive access of the application program in the second operating system to the exclusive device, and finally, the access requests for the exclusive device in the first operating system and the second operating system pass through the controller arranged in the second operating system. Concurrent access of the application program to the exclusive equipment can be limited in a dual-operating system scene, and normal use of the exclusive equipment is prevented from being affected.

A new approach is proposed to support hardware-based update of a software (e.g., a firmware) of an electronic device in a non-functional state. Under the proposed approach, the software is stored securely on a resource (e.g., a non-volatile storge) protected by a hardware-based lock mechanism. A first agent acquires a lock and authenticate the software. When a boot failure (e.g. authentication of the software fails) of the electronic device happens, an alert indicating the failure is generated and sent to a second agent (e.g., a sideband master) through an alert mechanism. The second agent then acquires a lock from the hardware-based lock mechanism to obtain exclusive excess to the resource and update the software stored in the non-volatile storage through, e.g., block write and / or read operations. The second agent then verifies that the software has been updated successfully so that the electronic device becomes functionally again.

This disclosure provides systems, methods, and devices for memory systems that support enhanced exclusive access fairness operations for scalable exclusive monitor architectures. In a first aspect, device includes a processing system that includes one or more shared memory devices and one or more request nodes. The processing system also includes one or more network interface units (NIUs), each NIU including an exclusive monitor configured to monitor exclusive accesses to shared memory addresses for a corresponding request node and including a timeout register for the exclusive monitor configured to control exclusive access fairness. The processing system includes one or more home nodes coupled to a corresponding shared memory device of the one or more shared memory devices. The processing system further includes an interconnect configured to couple the one or more request nodes to the one or more shared memory devices. Other aspects and features are also claimed and described.

A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.

Disclosed is a method for implementing a Zero Trust Architecture (ZTA) to secure network resources by eliminating lateral threat movement and minimizing attack surfaces. A zero trust policy engine, positioned inline between user devices and network resources, receives and evaluates access requests by verifying user and device identities along with context information. Based on dynamic risk scores derived from these evaluations, the engine enforces least-privileged, identity-based access policies, selectively granting access exclusively to authorized resources. Connections are terminated and re-established through secure proxy techniques, with continuous inspection of traffic for threats and data loss. Adaptive security measures, including isolation through pixel-streaming and context-aware access adjustments, further enhance protection. This architecture integrates seamlessly with cloud-based security service platforms, supporting workload-to-workload security, external entity integration, and comprehensive compliance reporting through audit trails and dashboards.

Systems and methods for an eBPF general allocator for an eBPF program is provided. The method includes receiving, by a first eBPF program, a first entry based on an atomic operation. The first entry is from a number of entries in a free list that indicates available space in a buffer. The available space is indexed by the number of entries in the free list. The method further includes identifying, based on the first entry, a pointer to the buffer. The pointer is associated with an allocation of the available space in the buffer based on the first entry. The allocation of the available space is to the first eBPF program. The method further includes executing, by a processing device, the first eBPF program with exclusive access to the allocation of the available space in the buffer during an execution instance of the first eBPF program.

The invention discloses a method and equipment for accessing a memory, relates to the technical field of terminals, and can solve the problem that a terminal device with a multiprocessor architecture cannot realize scientific and ordered memory access. In the application, the plurality of processors of the terminal equipment share the same memory, so that any processor can be ensured to normally store data, modify or read stored data and the like in any use scene. Moreover, any one of the plurality of processors can realize mutual exclusion access of the plurality of processors to the memory based on the acquired condition that whether other processors are accessing the memory or not, so that more scientific and ordered memory sharing is realized. According to the scheme that the processors of the terminal equipment share the same memory, the production cost of the terminal equipment can be reduced, and support is provided for miniaturization of the terminal equipment.

An example relates to managing mutually exclusive access to network slices in a communications network. A unified data management (UDM) node implementing a unified data management (UDM) network function of the communications network receives, from a session management function (SMF) node, a session registration request for accessing a first network slice that a user equipment (UE) seeks to access. In response to receiving the session registration request, the UDM node determines whether the UE has an active session registration for a second network slice. In response to determining that the UE has an active session registration for the second network slice, the UDM node selectively denies the session registration request for accessing the first network slice based on a policy.

A system may include: a plurality of processing cores including at least a first processing core and a second processing core; a shared memory communicatively coupled to each of the plurality of processing cores, and accessible by each of the plurality of processing cores; a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive access to the memory by each of the plurality of processing cores; and a software architecture embodied in a non-transitory computer readable medium and configured to divide a plurality of processing tasks between the first processing core and the second processing core when read and executed by the multi-core processor.

The invention provides a data processing method and device, and relates to the field of storage. The data processing method is applied to an object storage service and comprises the steps that a server side firstly receives an object access request, and the object access request comprises a target object; the server determines a lock attribute corresponding to the object access request, the metadata of the target object comprises the lock attribute of the target object, the metadata of the target object is distributed and stored in at least one object storage device, and the lock attribute is used for indicating the locking state of the target object; the server obtains the lock according to the lock attribute; and the server executes a data operation corresponding to the object access request on the data of the target object according to the lock. Therefore, the lock attribute is newly added to the object stored in the object storage service, and the semantic operation object based on the lock attribute is supported, so that mutual exclusion access of multiple clients to the same object is realized, data synchronization of the object is completed, and data consistency of concurrent writing and concurrent reading in object storage is ensured.

The application discloses a configurable read-write priority strategy read-write lock implementation method of an MMU-free embedded real-time operating system, and comprises the following steps: S1, performing strategy binding in a read-write lock creation stage; S2, realizing atomic operation in a middle-off mode; S3, actively eliminating writer starvation in a write priority mode; S4, performing priority inheritance when a write lock is applied; S5, adopting a double-waiting queue separation design; S6, adopting static memory pool zero dynamic allocation; and S7, adopting single-field tri-state encoding to mark a lock state. The configurable read-write priority strategy read-write lock implementation method of the MMU-free embedded real-time operating system realizes lightweight configurable read-write locks of the MMU-free embedded real-time operating system, can support flexible configuration of read / write priority strategies and has zero runtime switching overhead in the whole process, does not need special hardware instructions and MMU context support, and is perfectly compatible with low-end MCUs without exclusive access capability, such as Cortex-M0 / M0+.

A system for remote interview and assessment proctoring is disclosed. The system includes a proctoring server configured to identify interviewers and interviewees from among participants of an online meeting based on a role type parameter received from a first user device from which the online meeting is initiated. Further, two different types of meeting links are generated to access the same online meeting. A first type of meeting link is configured to provide exclusive access to a first type of participant identities associated with the identified interviewers. A second type of meeting link is configured to provide exclusive access to a second type of participant identities associated with the identified interviewees. The system selectively controls information flow among participant devices. Specifically, devices linked to interviewers are alerted if anti-proctoring applications are detected on devices associated with interviewees during the online meeting.

A computing system (102), comprises a system memory (116) including a lock array (204), a processor (112) coupled to the system memory (116), a peripheral bus (115) coupled to the system memory (116), and a hardware accelerator (122). The hardware accelerator (102) comprises a bus interface (141) coupled to the peripheral bus (115), a lock circuit (140) coupled to the bus interface (141), and a plurality of kernel circuits (138) coupled to the lock circuit (140) and the bus interface (141). The plurality of kernel circuits (138) provide lock requests to the lock circuit (140), the lock requests for data (202) stored in system memory (116) of the computing system (102). The lock circuit (140) is configured to process the lock requests from the plurality of kernel circuits (138) and to issue atomic transactions over the peripheral bus (115) through the bus interface (141) based on the lock requests. The lock circuit (140) is further configured to issue atomic transactions in competition with competing threads (139) executed by the processor (112) to check the lock array (204) in the system memory (116) for exclusive access to the data (202). The lock array (204) is indexed by identifiers for certain portions of the data (202) stored in the system memory (116). The lock circuit (140) provides a single source of atomic transactions over the bus interface (141) and maintains a kernel lock array (206) indexed by identifiers for the data (202) stored in the system memory (116).

In one embodiment, an apparatus includes: a fabric circuit to couple between a plurality of managers and a memory; and multi-bank memory control circuitry coupled to the fabric circuit and to couple to a plurality of banks of the memory and including a plurality of first ports to receive memory requests from the plurality of managers, The multi-bank memory control circuitry is to enable each of the plurality of managers to access the memory in parallel. A global monitor is coupled to the multi-bank memory control circuitry and includes a plurality of second ports and a plurality of state machines, each of the plurality of state machines to be associated with one of the plurality of managers. Each of the plurality of state machines is configured to enforce exclusivity of a memory region on behalf of a manager and concurrently enable non-exclusive access to the memory region.

This application discloses an information processing method, device, and system. The method comprises: obtaining status information of a storage device on a physical machine, wherein the status information is used to determine whether the storage device is being used by a virtual machine, the virtual machine being obtained by virtualizing the physical machine, and the virtual machine having exclusive access to the storage device; selecting a corresponding information collection method based on the status information to obtain information collection results; and reporting the information collection results to a cloud server. This application solves the technical problem in the prior art of being unable to implement full-time and full-state monitoring and management of NVMe storage devices.

A graphics processing unit (GPU)-based logic rewriting acceleration method comprising parallelizing sub-procedures of And-Inverter Graph (AIG)-based logic rewriting. A recursive sub-procedure of the AIG-based logic rewriting is redesigned to be non-recursive, to provide sufficient parallelism for a GPU. In order to parallelize a replacement step on the GPU, the present disclosure uses a lock to ensure mutually exclusive access, which inevitably damages scalability of inter-node parallelism. In order to fully utilize the inter-node parallelism on a large scale, the present disclosure proposes a work scheduler that adds nodes with non-overlapping maximum fan-out-free cones (MFFCs) to a group, such that nodes in an MFFC can be deleted simultaneously without a conflict. In order to simultaneously create and delete a same node, the present disclosure also proposes a GPU-friendly graphical data structure to support these concurrent operations.

A critical resource access method and apparatus, and a computing device are applied to a processor of the computing device. The method comprises the steps that in the process of executing a first kernel operation of a first task request, in response to a second interrupt request, execution of the first kernel operation is stopped, the second interrupt request comprises a second kernel operation, and the first kernel operation and the second kernel operation are used for accessing the same critical resource or different critical resources of the computing device; adding the second kernel operation into the first-in first-out channel, and continuing to execute the first kernel operation; after the first kernel operation is executed, kernel operation in the first-in first-out channel is executed, and the kernel operation in the first-in first-out channel comprises the second kernel operation. According to the scheme, in the process of executing the kernel operation of accessing the critical resources, the kernel operation of the interrupt request is added into the first-in first-out channel delay processing, so that the critical resources can be accessed in a mutually exclusive manner under the condition that the interrupt is not closed, and the problem that the interrupt response time is prolonged due to the fact that the interrupt is closed is solved.

A computer-implemented method, according to one embodiment, includes receiving, from a plurality of initiators, a plurality of reservation requests for logical unit numbers (LUNs) of a storage target. Exclusive type network paths between the initiators and the LUNs requested in the reservation requests are caused to be added to a restricted path list. The method further includes determining the initiators of the plurality of initiators, that have access to at least one of the exclusive type network paths in the restricted path list. Session logout commands are caused to be sent to the determined initiators. The session logout commands instruct the determined initiators to thereafter re-log in to sessions that are logged out of as a result the determined initiators adhering to the session logout commands. The method further includes allocating a first session that a first of the determined initiators re-logs in to, to a first fiber.

This disclosure provides systems, methods, and devices for memory systems that support enhanced exclusive read and write operations and scalable exclusive monitor architectures. In one aspect, device includes a processing system that includes one or more shared memory devices and one or more request nodes. The processing system also includes one or more network interface units (NIUs), each NIU of the one or more NIUs including an exclusive monitor configured to monitor exclusive accesses to shared memory addresses for a corresponding request node. The processing system includes one or more home nodes coupled to a corresponding shared memory device of the one or more shared memory devices. The processing system further includes an interconnect coupled to each NIU and to each home node and configured to couple the one or more request nodes to the one or more shared memory devices. Other aspects and features are also claimed and described.

Atomic memory access across consecutive granule boundaries is supported in a processor-based device. In this regard, the processor-based device includes a plurality of processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute consecutive granule ("cogran") pair atomic access (CPAA) tokens. To perform an atomic memory access on a cogran pair, a PE must hold a CPAA token for an address block containing one of the cogran pair before the PE can acquire exclusive state on each cogran in the cogran pair. Because a CPAA token must be acquired before exclusive access to at least one of the cogran pair is obtained, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlock and livelock between PEs seeking access to the same cogran can be avoided.

The present application provides a data distribution method, device, storage medium and product, relating to the field of streaming media technology. The data distribution method includes receiving a target instruction, where the target instruction includes any one of a push stream instruction and a pull stream instruction; if it is determined that the target instruction is a pull stream instruction, obtaining a target thread corresponding to the target instruction, and obtaining data corresponding to the target instruction based on the lock-free queue of the target thread. Embodiments of the present application ensure mutually exclusive access through a lock-free queue and can avoid frequent execution of lock addition and unlocking operations, effectively reducing performance loss and latency, and improving the user experience.

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.

The invention relates to the technical field of computers, and discloses a reset function arbitration method and device for a multi-host system, the method is executed by a PCIe switch in the system comprising the PCIe switch and a plurality of hosts, and the method comprises the following steps: receiving a lock request sent by a certain host for obtaining a reset function exclusive access right; judging the request according to a lock state inside the equipment, wherein the lock state reflects whether the exclusive access right is occupied or not; and after the access right is decided to be granted, correspondingly updating the lock state to record the current access right holder. According to the method, the request and arbitration process is established at the shared device end, the concurrent reset requests of the multiple hosts are subjected to ordered management, it is ensured that only one host obtains the operation authority at any moment, and therefore the conflict of reset operation is avoided.

The invention discloses a network access method and device based on a conference system, equipment and a storage medium, and relates to the technical field of communication, and the method comprises the steps: carrying out the authority verification of a conference access request of a to-be-accessed terminal; isolating the mutually exclusive access to-be-accessed terminals passing verification in different networks through IP address switching; performing resource allocation on all the terminals to be accessed in the same network according to the transmission power, and performing delay compensation on a network resource allocation result according to the transmission delay information; and accessing the to-be-accessed terminal to the conference system for data interaction based on the network resource allocation result and the transmission compensation information. According to the invention, the plurality of terminals to be accessed are isolated in different networks, and are accessed to the conference system after the delay compensation is carried out according to the network resource allocation results of different networks, so that the situation that the communication stability is reduced due to the transmission delay information of different networks is avoided, and the communication stability is improved through the scheduling of the network resources. And the communication reliability and stability of the conference system are improved.

The present application provides a mutual exclusion (mutex) device, a mutually exclusive access method and system for a shared resource, and a host. The method is performed by a target host, where the target host is any host among multiple hosts, and the multiple hosts are connected to the mutex device and the shared resource through a bus. The mutex device includes a mutex status register and a mutex set register; the mutex set register includes multiple first fields, the multiple first fields are in one-to-one correspondence with the multiple hosts, and each first field is used for identifying a request status of the multiple hosts for a mutex. The mutex status register includes multiple second fields, the multiple second fields are in one-to-one correspondence with the multiple hosts and each second field is used for identifying a hold status of the multiple hosts for the mutex. The method includes: setting a first field corresponding to the target host in the mutex set register to a first value in case of a determination that the target host has transmitted a mutex request; and setting a second field corresponding to the target host in the mutex status register to a second value and accessing the shared resource in case of a determination that the target host has successfully requested the mutex. In the method, by means of the register group in the mutex device, multiple hosts are identified by the mutex set register and the mutex status register respectively and the shared resource may be simply and effectively accessed without relying on strong algorithms and at low costs, which has strong universality

The application discloses a self-service check-in equipment counter mode adaptive detection switching method and system, relates to the technical field of check-in equipment, and comprises the following steps: defining multiple counter service modes in the central processing unit of the self-service check-in equipment, wherein the counter service modes have mutually exclusive access conditions and exit conditions; collecting multi-dimensional state signals of an air information host, a programmable logic controller, an application execution agent and a passenger interactive terminal; performing hierarchical priority mode trigger judgment on the multi-dimensional state signals, sequentially responding to safety events, air information host instructions, equipment and business states and passenger interactive behaviors, and determining a target counter service mode; after safety verification and process cleaning steps before mode switching, performing mode switching of the target counter service mode; and after completing the mode switching, synchronously updating man-machine interactive interfaces and external system state information. The application improves the autonomy, safety and service continuity of the self-service check-in system.

Systems and methods for providing cross-partition preemption analysis and prevention. The computing device generally includes a main central processing unit (CPU) having multiple cores to execute instructions independently, collaboratively, or in other suitable ways. In some examples, one or more cores are partitioned and dedicated to a particular application, where exclusive access of the cores in the partition is intended for running processes of the application. In some examples, some "noise" may be introduced into a partition, where preemption associated with other processes may interrupt execution of a particular application. A preemption diagnostic system and method identifies and prevents a source of cross-partition preemption events from running in a dedicated CPU partition. Thus, a particular application uses a dedicated core in a partition. Accordingly, the delay of the application is reduced, and bounded delay corresponding to the service level agreement may be achieved.