287results about "Data resetting" patented technology

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The present application relates to the technical field of computer communications. Disclosed are a method and apparatus for link reestablishment after a PCIe link equalization failure. The method comprises: determining a current state of a state machine and a state previous to the current state; when the current state is a speed recovery state and the previous state is an equalization recovery state, generating an initial reset request signal; after the initial reset request signal is generated, assigning a preset non-zero count value to a predefined counter, and starting decrement counting; and when the count value is not zero, generating a target reset pulse signal, wherein the target reset pulse signal is used for enabling the state machine to jump to a reset state. The present application uses direct hardware control, without the need for scheduling by a central processing unit; therefore, central processing unit and memory resources are not consumed, the impact on the overall system performance is relatively small, and a higher link reestablishment speed and a higher efficiency are achieved.

A method for recording data and an apparatus, an electronic device and a non-transitory computer readable storage medium is provided, and relates to the field of computer technologies. The method includes: configuring a BIOS and a BMC to share a shared memory of a CPU respectively, wherein the shared memory is a preset area of a memory mounted by the CPU; establishing a rule for using the shared memory for the BIOS and the BMC; when a server is started, checking a shared channel for the shared memory to determine whether the shared memory is successfully initialized; and transferring data related to RAS collected by the BIOS to the BMC via the shared memory based on the rule for using the shared memory, in a case where the shared memory is successfully initialized.

To provide a system that implements a state suspension for optimizing a start-up process of an autonomous vehicle.SOLUTION: Diagnostics and boot up for AV hardware and software of a computer system of an autonomous vehicle may be performed based at least on receiving a shutdown or power off indication, then a computing state of the computer system may be suspended with the computer system entering a low-power mode. The suspended computing state can be rapidly restored without requiring a reboot and diagnostics for key-on. To ensure integrity of the saved computing state, the computer system may exit the low-power mode, rerun the diagnostics, reload the programs, and then reenter the low-power mode. Restoring the suspended computing state may be triggered by a user inserting an ignition key, pressing a button to turn on the vehicle, opening a door to the vehicle, remotely unlocking the vehicle, remotely starting the vehicle, etc.SELECTED DRAWING: Figure 1

The application discloses a reset circuit and a vehicle-mounted Ethernet PHY chip reset system. The reset circuit comprises an Ethernet SWITCH unit, an MCU unit, a PHY chip unit and a reset chip unit. The Ethernet SWITCH unit is connected with a plurality of the PHY chip units. The plurality of the PHY chip units are connected with the reset chip unit. The Ethernet SWITCH unit is connected with the MCU unit. The MCU unit is connected with the reset chip unit. The reset circuit provided by the application can be reset in multiple ways. The reset circuit provided by the application has improved reliability, functionality and flexibility in a vehicle-mounted environment.

Embodiments of this application disclose an electronic device and a related reset restoring method. The electronic device includes a first processor core, a second processor core, and a power management unit. A first output pin of the first processor core is connected to a first input pin of the second processor core, a first reset pin of the first processor core is connected to a first control pin of the second processor core, and a second reset pin of the second processor core is separately connected to a second control pin of the first processor core and a third control pin of the power management unit. The second processor core is configured to: enter, by the second processor core, a reset state after the second reset pin of the second processor core receives a reset signal; and determine whether the first input pin is in a first state, and if the first input pin is in the first state, send a reset signal to the first reset pin by using the first control pin, for the first processor core to enter a reset state. According to embodiments of this application, a reset operation can be implemented when the electronic device is not completely powered off.

The application provides a PCIe data link recovery method and a PCIe system, and relates to the technical field of PCIe communication technology.When it is determined that the current board card is an EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is a low level; wherein the MODprel signal is used to indicate whether an optical module is in place; if the MODprel signal is a low level, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is a low level; wherein the first RXLOS signal is used to indicate whether an optical signal is in place; if yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so that the data link is recovered; wherein the RSSI signal is used to represent the size of optical power. The application has the effect that the PCIe system can automatically re-establish a chain after the optical module or the optical fiber line is plugged in or unplugged.

The present application belongs to the chip verification technical field, and particularly relates to a controllable clock reset signal generation module and method based on SV and UVM. The function module is used for providing the required clock reset signal as an excitation signal in a test platform. The module architecture comprises an rcc interface, an rcc configuration class, an rcc environment top layer, a sequence library, and an rcc transaction class. The rcc interface contains N virtual clock group interfaces. The rcc configuration class defines a clock reset group agent number variable and N clock group configurations. The rcc environment top layer declares an rcc virtual interface handle, an rcc configuration handle, and N clock reset group agents. The sequence library contains four function sequences for controlling the clock signal and the reset release signal in the excitation signal. The rcc transaction class creates N clk transaction classes and encapsulates the attribute configuration of the corresponding clock reset. The present application overcomes the problems of the traditional verification platform, such as the clock reset signal being unable to be flexibly edited, low verification efficiency, high error rate and the like.

An apparatus, system, and method are provided that improve communication between a memory device and a controller. A data communication apparatus includes a transceiver coupled to a data path and configured to send or receive data over the data path, and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether any device is allowed to occupy the data path. The interrupt circuit generates an interrupt signal to prevent another device from accessing the data path in response to an activation signal to send or receive data by the transceiver.

The invention discloses a power station arc discharge data acquisition control method, which comprises the following steps of: after equipment is electrified, carrying out equipment self-inspection to ensure that each piece of equipment in a system can operate normally and the equipment is accurately positioned when the equipment is abnormal, and ensuring that the abnormal equipment is quickly positioned and repaired; by automatically matching an actual data acquisition scene according to the current environment, the data acquisition efficiency and accuracy are improved, meanwhile, in order to protect equipment, a time interval is increased when an impedance network is set, and due to the increase of the time, secondary scene information checking is added for the accuracy of an arc discharge data scene label, so that the accuracy of the arc discharge data scene label is improved. Data is matched with scene information as much as possible; scene configuration information is obtained in real time before execution each time, and the scene configuration information is synchronously updated to a scene configuration file after data acquisition is completed; it is ensured that data cannot be collected repeatedly when execution is started next time if the data collection is abnormal midway or manually interrupted, errors possibly caused by manual intervention are reduced, and the use threshold of a control system is lowered.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

A method of handling a firmware update for a device is disclosed, comprising: determining a device to be in an updatable state; setting the device into an updating state after determining the updatable state; and after the device is in the updating state, writing a firmware update to memory for the device. After writing the firmware update, the device is switchable to a working state in which the device operates based on the firmware update.

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

Handling resets comprises communicating transport packets between a transport network and data processing circuitry, with at least a portion of the data processing circuitry operating in a given reset

The invention belongs to the technical field of processor chip design, and particularly discloses a microsystem module which is mainly based on a multi-core DSP (digital signal processor) and a high-performance FPGA (field programmable gate array) dual-processor architecture, and comprises a multi-core DSP, an FPGA processor, a program memory, a data memory, an electronic resume memory and a reset chip, the core 1 and the core 2 are respectively connected with a program memory, the core 1 is connected with a data memory, and the core 1 is connected with other cores in the multi-core DSP processor; the FPGA processor is connected with a program memory and an electronic resume memory; and the reset chip is used for providing reset delay time and realizing under-voltage protection and timed monitoring of the system. According to the invention, the circuit architecture is subjected to heterogeneous integration through the SIP technology, the product performance can be improved, the system power consumption can be reduced, the system function density can be improved, the development requirements of miniaturization and light weight of intelligent electronic equipment can be met, the design cost can be reduced, and the development period can be shortened.

According to an embodiment, an electronic device may include a first button, a second button, at least one processor, a pressure sensor configured to provide a first signal to the at least one processor, a piezo actuator configured to output vibration through the first button, and a memory storing instructions. The instructions, when executed individually or collectively by the at least one processor, may cause the electronic device to: detect a malfunction related to the first button on the basis of receiving a second signal from the piezo actuator while a first signal is not provided from the pressure sensor to the at least one processor; and execute a function assigned to a combination of a pressure on the first button and a pressure on the second button in response to the second signal and a third signal indicating the pressure on the second button being maintained for a reference time.

The invention discloses a multi-mode starting automatic control method and system based on a PC Farm array server, and relates to the technical field of server cluster management.The method comprises the steps that a central node creates a fine-grained strategy instruction and a corresponding mirror image instruction according to deployment requirements, and the fine-grained strategy instruction and the corresponding mirror image instruction are compressed into a mirror image compressed package through LZMA; the edge node extracts the verification label from the mirror image compressed package, analyzes the verification label through quantum error correction control, repairs a bit flipping error, and generates an anti-interference standardized instruction stream; based on the anti-interference standardized instruction stream, generating a quantum code stream data block through Hamming code coding, writing the quantum code stream data block into a configuration interface address, and correcting signal deviation to trigger a reset command; and executing the reset command, collecting a BIOS startup log, and comparing the BIOS startup log with pre-stored features to generate a startup state verification report. According to the method, accurate calibration and sequential control of hardware configuration are realized, the accuracy of starting parameters is ensured, and the high efficiency and stability of automatic deployment are improved.

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

The utility model discloses a circuit for a 4D millimeter wave radar to realize software control hardware restart, which comprises an input primary power supply DC-DC (Direct Current-Direct Current) for providing voltage for a system; the power supply PMIC is connected with the input primary power supply DC-DC and converts the voltage into a plurality of output voltages; the 4D millimeter wave radar main control unit is connected with the power supply PMIC and the input primary power supply DC-DC, and the power supply PMIC is connected with the input primary power supply DC-DC and is used for providing voltage input for the 4D millimeter wave radar main control unit; and the driving module is connected with the input primary power supply DC-DC and the 4D millimeter wave radar main control unit. Through the design of a hardware circuit, the hardware can be controlled to be restarted through software. The occurrence of unsuccessful restart events is effectively reduced, and the performance of the 4D millimeter wave radar is improved.

The application discloses a FPGA global reset synchronization circuit, a chip, a verification simulation system and a method. The FPGA global reset synchronization circuit comprises a clock signal channel and a reset signal channel. The clock signal channel comprises a filter and a frequency multiplier. The filter is used for filtering an input first clock signal, the frequency multiplier is used for frequency multiplication after the filtering, a second clock signal is generated, the frequency of the second clock signal is an integer multiple of the first clock signal, and the second clock signal is output to provide a clock signal for user logic in the FPGA chip. The reset signal channel comprises a cross-clock-domain transmission circuit. The cross-clock-domain transmission circuit is used for outputting an input reset signal after the cross-clock-domain transmission to provide a global reset signal for the user logic in the FPGA chip. The application does not depend on the distance of the FPGA and the length of the signal line, and is especially suitable for clock reset synchronization of a large number of FPGAs when the FPGAs are used for chip verification and simulation.

Particular embodiments described herein provide for an electronic device that includes a battery, a display, an embedded controller to determine a battery condition and set an indicator when then battery condition is at a low power state, and a basic input / output system (BIOS), where, before an operating system stage of a boot process, the BIOS sets a brightness of the display at a native brightness if the indicator is not set and sets the brightness of the display at a low power brightness to reduce the brightness of the display if the indicator is set. In an example, the embedded controller sets the indicator before the central processing unit is reset during the boot process.

The invention provides a layered reset control system of a switching module. The layered reset control system comprises a monitoring logic circuit and a microprocessor, the monitoring logic circuit is configured to receive reset request signals from at least two independent reset sources and perform logical operation on the reset request signals to generate a first reset control signal output to the switch chip layer and / or the bus interface layer; the microprocessor is configured to monitor the working state of the optical module layer and / or the network physical layer chip, and trigger and generate a second reset control signal for the optical module layer and / or the network physical layer chip based on the working state; wherein at least two of the switching chip layer, the bus interface layer, the optical module layer and the network physical layer form a controlled multi-level function level in the switching module, and the monitoring logic circuit and the microprocessor cooperate to realize discrete reset control of the multi-level function level. According to the system provided by the invention, rapid isolation and recovery of a fault unit are realized through layered precise reset, and global interruption of the system is avoided.

The application relates to a low-power-consumption clock delay method and system in the technical field of integrated circuits, which comprises the following steps: based on a counting clock signal, the counting clock signal is phase-aligned with a clock signal to be delayed to generate a first phase clock alignment signal and a second phase clock alignment signal; the rising edge information and the falling edge information of the first phase clock alignment signal are extracted to obtain a pulse signal; the clock rising edge information and the clock falling edge information are split to obtain a first pulse filtering signal and a second pulse filtering signal; the first pulse filtering signal and the second pulse filtering signal are sequentially subjected to coarse delay, and after the coarse delay, signal synthesis processing is carried out to obtain a coarse delay clock signal; and based on a digital time converter, the coarse delay clock signal is subjected to fine delay to obtain a fine delay clock signal, thereby solving the problem that the existing delay technology cannot simultaneously realize high delay precision and a large dynamic range under low power consumption.

Techniques are described herein that are capable of initiating recovery of an electronic device using a power reset pattern. In a first example implementation, a determination is made that an electronic device is in a non-operational state. A power supply control signal is generated. The electronic device is caused to initiate a recovery process using a power reset pattern by providing the power supply control signal to the power supply via a power line. The recovery process changes the electronic device from the non-operational state to an operational state. In a second example implementation, a power reset pattern is received via a power line from a power supply. A determination is made that the power reset pattern is an instruction to initiate a recovery process. An electronic device is changed from a non-operational state to an operational state by initiating the recovery process.

The present disclosure relates to a power domain management circuit and a system on chip. The power domain management circuit includes: an enable unit, configured to generate an enable signal with a first preset level in a case of receiving an isolation set signal, or to generate an enable signal with a second preset level in a case of receiving a reset indication signal; and a clamping unit, electrically connected to the enable unit, and configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal with a third preset level in a case of receiving the enable signal with the first preset level, or to skip clamping the initial signal to generate a target signal with a level that varies with a level of the initial signal in a case of receiving the enable signal with the second preset level.

The invention discloses a multi-level cabinet management system and method based on a high-density computing server, and relates to the technical field of high-density computing servers. In order to solve the state management problem that high-density computing servers of different architectures are integrated in the same cabinet, the adopted scheme comprises a computing node management module used for realizing health state monitoring, abnormal alarm reporting and remote startup and shutdown and reset functions of a single computing node through a BMC (Baseboard Management Controller); the case management module is used for establishing communication with the BMC of each computing node by means of the SMC, acquiring and controlling the state information of each computing node, summarizing the state data of all the computing nodes, and uniformly reporting the state data to the RMC in combination with the information of the case; and the cabinet management module is used for establishing communication with the SMC of each case by means of the RMC, acquiring and controlling the running state of each case and the data of the computing nodes in the case, integrating the state data of all the cases, superposing the information of the cabinet, and reporting the cabinet-level centralized management data to a cloud management system in a unified manner.