669results about "Data resetting" patented technology

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

During operation, an electronic device may receive, associated with a computer, a packet or a frame that includes a dynamic power reset pattern, where the dynamic power reset pattern specifies temporal pattern of power resets. Then, the electronic device may detect multiple power resets, where a given detected power reset in the detected power resets involves activation of a power reset button in the electronic device. Moreover, the electronic device may compute a detected power reset pattern, where the detected power reset pattern includes a detected temporal pattern of detected power resets. Next, the electronic device may compare the dynamic power reset pattern and the detected power reset pattern. Furthermore, based at least in part on a result of the comparison, the electronic device may at least selectively provide, to the computer, the result of the comparison.

The invention relates to the technical field of electronic systems of spacecrafts, and discloses a fault-tolerant method for non-redundant fault reconstruction of a spaceborne computer, which comprises the following steps of: 1, accessing a hardware state manager by a BIOS (Basic Input / Output System) after the system is started; obtaining health state data recording the health state of the local storage device, a current starting target ID used for indicating a current starting target, and a retry count value associated with the current starting target ID; a BIOS (Basic Input Output System) accesses a hardware state manager to obtain health state data and a retry count value of local storage equipment, so that normal equipment is autonomously selected for starting, and the fault-tolerant effect of dynamically avoiding a fault starting path is achieved; compared with the technical scheme in the prior art that the computer starting process highly depends on a solidified single physical storage device, the single-point fault risk of permanent paralysis of the computing system caused by damage of the single storage device is solved.

Disclosed is a reset semiconductor integrated circuit that outputs a reset signal in response to a power supply voltage of a monitoring target becoming lower than a predetermined level, the reset semiconductor integrated circuit including: a voltage detection circuit; an output stage including a CMOS circuit that generates and outputs a signal according to a detection result of the voltage detection circuit; a monitored voltage input terminal to which the power supply voltage of the monitoring target is input; a reference potential terminal to which a voltage as a reference potential of a circuit is applied; an external voltage terminal which is connected to a power supply voltage terminal of the output stage to allow a power supply voltage as an operation voltage of the output stage to be applied from outside; and an output terminal to output the signal generated by the output stage.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

The invention relates to a power supply control circuit, a detection device, a countering device and an electronic device. The power supply control circuit comprises a main control module which outputs a state feedback signal according to an operation state. The power management module is connected with the power equipment and the main control module, and the power management module is used for converting power voltage of the power equipment into power supply voltage and outputting the power supply voltage to the main control module. And the switching circuit is respectively connected with the power supply equipment, the power supply management module and the main control module, and is used for controlling the power supply management module to stop outputting the power supply voltage under the condition that the state feedback signal does not reach the preset standard, so that the main control module is powered off. And the switching circuit is also used for controlling the power management module to output the power supply voltage again according to the received power supply voltage after the power management module is controlled to stop working, so that the main control module is restarted. By implementing the embodiment of the invention, power-off reset can be realized without manual adjustment, and convenience and practicability are improved.

A communication device comprises: a communication interface; a display screen; a first processor configured to power up according to a first power-up time, the first processor for implementing radio functionality associated with the communication interface; and a second processor configured to power up according to a second power-up time longer than the first power-up time, the second processor for implementing extended functionality as compared to the first processor. The first processor, after the first power-up time: controls the display screen to provide a first GUI displaying communication interface-related information and a power-up status of the second processor; and after the second power-up time, hand off control of the display screen to the second processor. The second processor, after being provided with control of the display screen: controls the display screen to provide a second GUI displaying the communication interface-related information and information associated with the extended functionality.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The present disclosure discloses a fault recovery method. The method includes: in response to a server being powered on or reset, starting baseboard management controller firmware from one or more flash memories storing the baseboard management controller firmware; in response to a failure of the starting the baseboard management controller firmware from the flash memories, starting a boot loader from a flash memory in which the boot loader is burned; in response to the boot loader being successfully started, obtaining backup baseboard management controller firmware from an external storage device through the boot loader, and burning the backup baseboard management controller firmware to any one of the flash memories; and in response to the burning being completed, resetting the server, and enabling the flash memory to start the backup baseboard management controller firmware from the flash memory in which the backup baseboard management controller firmware is burned.

A request to update first configuration data associated with a first tenant of a multi-tenant system is received. The first configuration data can be included in a first shard residing at a first node of the system. The first shard can also include second configuration data associated with a second tenant. Upon initiation of an operation to update the first configuration data at the first node in accordance with the first request, an anomaly associated with the update at the first node is detected. A request to access the second configuration data is received. A second node that includes a second shard that includes the second configuration data is identified. An operation is performed to provide the second tenant with access to the second configuration data at the second node before the anomaly associated with the update to the first configuration data is resolved.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

The invention discloses a chip reset control method and device, equipment and a medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target chip comprising a plurality of functional modules, and constructing a reset matrix for the target chip according to reset requirements of the functional modules; loading and analyzing the reset matrix to determine a reset trigger condition of each functional module, and based on the reset trigger condition, generating a multi-stage reset control signal conforming to a reset control strategy through a preset general reset control circuit; distributing the multi-stage reset control signal to each functional module according to a preset reset time sequence so as to control each functional module to perform reset operation; and adjusting the dynamic control dimension parameters in the reset matrix in real time by presetting a dynamic configuration interface so as to perform reset adjustment and optimization on the target chip after tape-out. Through the technical scheme of the invention, the problems of low efficiency, time sequence conflict and insufficient flexibility in the traditional reset design can be solved.

The invention discloses a chip reset circuit, a server and a mobile terminal, relates to the technical field of chip reset, and provides the chip reset circuit aiming at the problem that the reset of a CPU (Central Processing Unit) chip excessively depends on a CPLD (Complex Programmable Logic Device) chip at present. And a power-on ready signal is output to a backward stage through the time delay module. The post-stage reset control circuit can control whether to reset the CPU chip according to whether the reset trigger signal is received. Otherwise, a reset control signal is output all the time to prohibit the CPU chip from being started, so that the reset control requirement and the power-on time sequence management requirement of the CPU chip are met at the same time. And the circuit is completely realized by a hardware circuit and does not need to depend on complex devices such as a CPLD (Complex Programmable Logic Device), so that the reliability and the stability of the reset control of the CPU chip are greatly improved.

A low battery voltage protection method for a microcontroller system and a microcontroller system using the same are provided. The low battery protection method and the microcontroller system are used to prevent continuous battery drain by setting time thresholds and a count threshold. In an embodiment, when a low-voltage power-on reset voltage is not exceeded within a first preset time, the microcontroller system is forced to enter a sleep mode to prevent power consumption by an analog block. In another embodiment, when the low-voltage power-on reset voltage is exceeded, but a reset count of the microcontroller system exceeds a preset value within a second preset time, the microcontroller system is also forced to enter the sleep mode to prevent a digital block from continuously loading data, which could lead to battery failure.

The invention discloses a reset circuit of an automobile MCU and an automobile controller. The reset circuit of the automobile MCU comprises a power management module and a hardware watchdog. When the voltage output by the voltage output end of the power supply management module is smaller than the minimum working voltage of the MCU, the MCU stops working, the communication connection between the communication end of the power supply management module and the MCU is disconnected, and a first reset signal end of the power supply management module outputs a first reset signal to the MCU; and when the watchdog input end of the hardware watchdog receives the dog feeding signal sent by the MCU overtime, a second reset signal end of the hardware watchdog outputs a second reset signal to the MCU. Compared with the prior art, the reset circuit of the automobile MCU integrates the power supply monitoring function of the power supply management module and the external hardware watchdog of the MCU to jointly ensure that the MCU can be stably started or recover normal work under an abnormal working condition, so that an automobile controller works more stably.

The application provides a system and a control method for implementing a DSP reset process based on FPGA, and relates to the technical field of DSP reset. A first IO pin of the FPGA is connected with a reset pin of the DSP through a DSP reset line to control the reset process of the DSP. A second IO pin of the FPGA is connected with a GPIO pin of the DSP through a DSP state flag line to represent the reset state of the DSP, so that initial reset control and midway crash reset control are completed. The reset signal of the DSP is controlled by the FPGA, and the application has the characteristics of flexibility, time controllability, state controllability, field maintainability and the like, and effectively solves the two technical problems of power-on non-starting and midway crash of the DSP.

The invention relates to the technical field of chips, and provides a power-on control method and system, a chip, equipment and a storage medium, and the method comprises the steps: controlling a first power domain to be powered on, maintaining a second power domain to be in a power-off state, and driving a signal processing circuit to process an external input signal and output a target signal, the first power domain supplies power to the signal processing circuit, and the second power domain supplies power to a post-stage logic circuit; after determining that the target signal is in a stable state, controlling the second power domain to be powered on so as to start the post-stage logic circuit; wherein the started post-stage logic circuit carries out sampling processing on the target signal in a stable state. According to the invention, power domain division is carried out on the signal processing circuit and the post-stage logic circuit and time-sharing power-on of the signal processing circuit and the post-stage logic circuit is controlled, so that stable and effective signals can be always sampled by the post-stage logic circuit when the post-stage logic circuit is started, and the power-on reliability of a chip and the stability of a system are improved.

The invention relates to a low-power-consumption clock delay method and system in the technical field of integrated circuits, and the method comprises the following steps: carrying out the phase alignment of a counting clock signal and a to-be-delayed clock signal based on the counting clock signal, and generating a first phase clock alignment signal and a second phase clock alignment signal; extracting rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal; splitting the clock rising edge information and the clock falling edge information to obtain a first pulse filtering signal and a second pulse filtering signal; performing coarse delay on the first pulse filtering signal and the second pulse filtering signal in sequence, and performing signal synthesis processing after coarse delay to obtain a coarse delay clock signal; and performing fine delay on the coarse delay clock signal based on the digital time converter to obtain a fine delay clock signal, thereby solving the problem that the existing delay technology cannot simultaneously realize high delay precision and large dynamic range under the condition of low power consumption.

The present disclosure relates to the field of memory technologies and provides a data sampling circuit, comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal, or to input the low-level signal to the first output terminal and input the high-level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module. In this data sampling circuit, the second sampling module is additionally provided, and the offset compensation module is connected in parallel to the second sampling module, such that kickback noise is reduced.

A method of updating software of an Electronic Control Unit (ECU) includes: downloading a boot loader to a boot area of a second memory bank in an inactive state, and downloading a firmware or data to a normal area, when a first memory bank is in an active state; setting the second memory bank, which is in the inactive state, as a memory bank to operate in the active state after a reset of the ECU; and resetting the ECU to cause the second memory bank to operate in the active state.

During system power-on, Ethernet controllers in a server are initialized and configured by a Power-On-Reset (POR) mechanism. A user-defined time period can be selected to delay configuration of an Ethernet link to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation. After configuration of an Ethernet PHY in the Ethernet controller is complete, an Ethernet link is established by exchanging messages with link partners according to the Ethernet protocol.

The invention provides a power-on reset circuit and a chip. The power-on reset circuit comprises a power-on module, and the power-on module is used for controlling connection or disconnection of a first end and a second end of the power-on module based on a control voltage and a power supply voltage of a first power supply end, and adjusting an output voltage of the power-on module based on the change of the power supply voltage when the power-on module is connected; the voltage dividing module is used for providing control voltage to the power-on module; the conversion module is used for converting the output voltage of the power-on module to output a reset control signal under the condition that the output voltage of the power-on module is changed to the overturning voltage of the conversion module; the first inverting module is used for converting the reset control signal to output a reset signal. Therefore, the power consumption generated in the circuit can be reduced while the circuit area is saved.

Provided in the present disclosure is a connector port multiplexing apparatus, comprising: a latch reset circuit, which is electrically connected to a first voltage source and a power terminal of a universal serial bus connector, and is configured to output a control signal on the basis of a first voltage that is output by the first voltage source and a second voltage from the universal serial bus connector; and an analog switch circuit, a control terminal of which is electrically connected to an output terminal of the latch reset circuit, a first terminal of which is electrically connected to a first signal transmission terminal of a universal serial bus controller, a second terminal of which is electrically connected to a second signal transmission terminal of the universal serial bus controller, and a third terminal of which is electrically connected to a multiplexing signal transmission terminal of the universal serial bus connector, wherein the analog switch circuit is configured to establish, on the basis of the control signal, a connection path between the first terminal and the third terminal of the analog switch circuit or a connection path between the second terminal and the third terminal of the analog switch circuit.

The invention discloses a method, a device, a system, equipment and a medium for clearing a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) on a PCH less platform. The method comprises the following steps of: initializing and operating the system; after the CPLD finishes initialization, performing power-on startup response on the system according to a normal power-on process; the BMC is initialized and runs to a normal working state according to the requirements of a system platform; initiating a CMOS (Complementary Metal Oxide Semiconductor) clearing instruction; after the CPLD receives the CMOS clearing instruction, the CPLD judges the current state: if the CPLD is not started up, orderly power-down control is carried out on related front power supply and power supply state signals of the CPU; after it is confirmed that power failure is completed, a high-level pulse is sent out, and a CMOS clearing instruction is completed; if the system is started up, all devices in the system enter a reset state, a rear power supply in the system and a front power supply of a CPU are powered down, and meanwhile all corresponding power supply state signals are set; after it is confirmed that all power failures are completed, a high-level pulse is sent out, and a CMOS clearing instruction is completed; through collaborative innovation of the BMC and the CPLD, a secure remote CMOS clearing function under a server without a PCH architecture is realized.

The invention discloses a system upgrading control method, a controller, a vehicle and a storage medium. According to the method and the device, when the target equipment loads the upgraded first mirror image file to carry out system boot, integrity verification on the first mirror image file is added. Based on the integrity verification result of the first mirror image file, starting control is conducted on the target device. Thus, in the process of system upgrading of the target device, the situation that the first mirror image file generates an updating error can be found in time, and starting control is performed on the target device based on the integrity verification result, so that the stability of system upgrading of the target device is improved.

According to the memory controller and the microcontroller chip provided by the invention, time division multiplexing can be carried out on a built-in mirror image buffer area with relatively small capacity in the microcontroller according to actual start setting requirements, so that different contents in a nonvolatile memory can be copied to the mirror image buffer area in sequence in a time division manner; the central processing unit can read and run corresponding contents from the mirror image buffer area, and in the process of running the previously copied contents by the central processing unit or after the central processing unit finishes running, the previously copied contents can be partially or completely covered by the later copied contents, so that compared with the mirror image buffer area of the microcontroller in the prior art, the mirror image buffer area of the microcontroller has the advantages that the reliability of the microcontroller is improved; the hardware cost is saved, and the cost of a microcontroller chip is remarkably reduced. In addition, the content needing to be copied to the mirror image buffer area in the MCU chip power-on reset or system reset stage is reduced compared with the prior art, and therefore the system starting time can be remarkably shortened.

The present application relates to the technical field of computers. Provided are a data recording method and apparatus, and an electronic device and a nonvolatile readable storage medium. The method comprises: separately configuring a basic input output system and a baseboard management controller as a shared memory under a shared central processing unit, wherein the shared memory is a preset region of a memory mounted on the central processing unit; agreeing on a shared-memory usage rule for the basic input output system and the baseboard management controller; and when a server is started, performing shared-channel inspection on the shared memory to determine whether the shared memory has been successfully initialized; and when the shared memory has been successfully initialized, on the basis of the shared-memory usage rule, transmitting, to the baseboard management controller by means of the shared memory, data collected by the basic input output system and related to an RAS function. The solution of the present application enables the recording of data related to an RAS function no longer to be affected by a server chip architecture and constrained by the architecture, and has the characteristics of high universality and high applicability.

The present application relates to the technical field of computer communications. Disclosed are a method and apparatus for link reestablishment after a PCIe link equalization failure. The method comprises: determining a current state of a state machine and a state previous to the current state; when the current state is a speed recovery state and the previous state is an equalization recovery state, generating an initial reset request signal; after the initial reset request signal is generated, assigning a preset non-zero count value to a predefined counter, and starting decrement counting; and when the count value is not zero, generating a target reset pulse signal, wherein the target reset pulse signal is used for enabling the state machine to jump to a reset state. The present application uses direct hardware control, without the need for scheduling by a central processing unit; therefore, central processing unit and memory resources are not consumed, the impact on the overall system performance is relatively small, and a higher link reestablishment speed and a higher efficiency are achieved.

A wake-up method and an electronic device. When the electronic device enters a deep suspend state, the electronic device can automatically reboot, so that the electronic device restores to normal, and can be normally used by a user, thereby improving user experience. In the method, the electronic device starts timing. A suspend duration is obtained if a working state of the electronic device is a suspend state when a timing duration reaches a preset refresh period, where the suspend duration is a difference between a moment at which the electronic device enters the suspend state and a timing refresh moment. The electronic device triggers, if the suspend duration is greater than or equal to a first preset threshold, an operation of rebooting a system.