1293results about "Data resetting" patented technology

The invention discloses a queue management method of a storage device, an electronic device and a storage medium, and relates to the technical field of data processing. When the storage device is configured, a host only needs to send an instruction containing a batch operation type and a queue parameter storage address; triggering the storage device to obtain queue parameter information of a plurality of input and output queues in batches from a specified address, and completing creation or deletion operation of all the input and output queues at one time; according to the method and the device, a plurality of commands which need to be issued one by one originally are simplified into single interaction, so that the communication times and data transmission redundancy between the host and the storage equipment are greatly reduced, the occupation of link bandwidth is reduced, the time of an initialization or reset process is remarkably shortened, and the data transmission efficiency is greatly improved especially in a scene with a relatively large number of queues. The problems of heavy interaction burden, low link efficiency, long processing delay and reset overtime risk in the prior art are effectively solved, and the technical effects of simplifying the interaction frequency and improving the configuration efficiency are achieved.

A decoding operation is performed by receiving a command to read a correction matrix comprising multiple bit-values from memory of a decoder. The decoding operation also includes, responsive to receipt of the command, generating, using circuitry of a decoder, a predetermined correction matrix comprising a same bit-value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.

The satellite-borne heterogeneous computing system comprises a CPU (central processing unit) module, an FPGA (field programmable gate array) module and an NPU (network processing unit) module, the CPU module is used for receiving instructions and telemetering polling of a satellite service computer, reading load scientific data received by the FPGA module, providing installation and operation environments for various types of universal application programs, and scheduling and controlling the NPU module; the FPGA module is used for providing external interface expansion, receiving load scientific data and sending the load scientific data to the CPU module, and is also used for providing a logic control function comprising SPI FLASH triple modular redundancy logic and barking reset; and the NPU module is used for performing high-performance calculation and providing a high-computing-power environment for the system. The system has high flexibility, reliability and universality, and can operate various computing software and neural network algorithms; the power consumption is low, and strict requirements of a satellite platform on power consumption can be met. And a plurality of systems are interconnected to form a distributed computing system, so that the performance is extremely high.

The invention discloses a power gating system, a power gating method and a system on chip. Relates to the technical field of power management, and comprises a central processing unit used for writing software power-down configuration information into a register module; the register module is used for triggering a software power-down request according to the software power-down configuration information and sending the software power-down request to the power gating controller; the system power consumption controller is used for determining a system power consumption mode according to the state of the central processing unit, triggering a hardware power-down request and sending the hardware power-down request to the power gating controller under the condition that the system power consumption mode is a low-power-consumption mode; and the power gate controller is used for detecting the state of a bus of the power domain based on the software power-down request or the hardware power-down request, and executing power-down time sequence control on the power domain under the condition that the state of the bus is detected to be an idle state. The technical problems that the power gating speed is low and the software overhead is large when the bus state is inquired through software with high complexity in the prior art are solved.

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

The invention provides a reset processing method and system based on multiple reset sources, electronic equipment and a storage medium. The method comprises the following steps: a reset state machine generates a reset application for each reset source according to a reset signal and a reset type corresponding to each reset source; the round-robin scheduling module performs round-robin scheduling on each reset application to generate a reset scheduling response signal; the reset state machine generates a reset release application of each reset source according to the reset scheduling response signal and the reset type; the rotation scheduling performs rotation scheduling on each reset release application, generates a reset release scheduling response signal of each reset release application, and sends each reset release scheduling response signal to the reset state machine; the reset state machine clears the reset application and the unlocking reset signal of each reset source according to each reset release scheduling response signal, and the reset state machine generates the reset application corresponding to each reset source according to the reset type with higher priority and the reset signal of each reset source corresponding to the type.

The invention discloses an IC generation method of a virtual controller, a product, a medium and equipment, and relates to the technical field of nuclear power simulators, and the method comprises the steps: obtaining a modified project file; compiling the modified project file, and adding a point table generation operation in the compiling process to obtain a point table file; downloading the point table file into a virtual controller of a lower computer; in a virtual controller of the lower computer, performing IC reset operation on the old IC file based on the point table file to obtain a modified IC file; the old IC file is an IC file corresponding to a project file before modification; and storing the modified IC file. According to the IC generation method of the virtual controller, the product, the medium and the equipment, the flexibility and the efficiency of IC file upgrading can be effectively improved.

During operation, an electronic device may receive, associated with a computer, a packet or a frame that includes a dynamic power reset pattern, where the dynamic power reset pattern specifies temporal pattern of power resets. Then, the electronic device may detect multiple power resets, where a given detected power reset in the detected power resets involves activation of a power reset button in the electronic device. Moreover, the electronic device may compute a detected power reset pattern, where the detected power reset pattern includes a detected temporal pattern of detected power resets. Next, the electronic device may compare the dynamic power reset pattern and the detected power reset pattern. Furthermore, based at least in part on a result of the comparison, the electronic device may at least selectively provide, to the computer, the result of the comparison.

The invention provides a system and a method for automatically recording CPU abnormal restart reasons and storing logs and data, the system comprises a reset trigger module, a reset reason recording module, a data and log recording module and a reset execution module, each module circuit uses a discrete device, an FPGA or CPLD chip does not need to be used, the cost is saved, and the system reliability is improved. According to the method, restart reasons which can be automatically recorded comprise the condition of active restart or passive restart caused by program exception, the condition of manual operation of a reset key and the condition of sudden temporary failure of a power supply, and meanwhile, important data, state information and log information can be quickly stored through a memory by a CPU (Central Processing Unit) through a design mechanism before restart; and after restarting, the data is transferred to the nonvolatile storage device, so that data loss is prevented, and deep reasons of abnormal restarting can be further analyzed.

The invention relates to the technical field of electronic systems of spacecrafts, and discloses a fault-tolerant method for non-redundant fault reconstruction of a spaceborne computer, which comprises the following steps of: 1, accessing a hardware state manager by a BIOS (Basic Input / Output System) after the system is started; obtaining health state data recording the health state of the local storage device, a current starting target ID used for indicating a current starting target, and a retry count value associated with the current starting target ID; a BIOS (Basic Input Output System) accesses a hardware state manager to obtain health state data and a retry count value of local storage equipment, so that normal equipment is autonomously selected for starting, and the fault-tolerant effect of dynamically avoiding a fault starting path is achieved; compared with the technical scheme in the prior art that the computer starting process highly depends on a solidified single physical storage device, the single-point fault risk of permanent paralysis of the computing system caused by damage of the single storage device is solved.

The invention relates to a data transmission processing system, method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps of: transmitting received storage data from a host to a rear end through a storage data forwarding module in an FPGA (Field Programmable Gate Array) chip; the method comprises the following steps: controlling a stored data forwarding module to be initialized through an SOC chip under the condition that transmission of stored data is detected to be abnormal; controlling the register module to obtain queue pointer information of the host; the obtained queue pointer information is stored in the initialized storage data forwarding module; sending a retransmission instruction to the initialized storage data forwarding module; and further executing a data retransmission operation of the stored data according to the received retransmission instruction through the initialized stored data forwarding module so as to transmit the stored data to a rear end in a lossless manner. By adopting the method, lossless data transmission can be realized, and the stability and robustness of the system are improved.

Aspects of the present disclosure are directed to techniques and apparatuses for implementing a power-on (PON) sequence in a computer system. A power management integrated circuit (PMIC) receives a boot circuit indicator (BCI) signal from a computer system. The BCI signal identifies a circuit of the computer system to be enabled in a power-on (PON) sequence. The PMIC provides power to the boot core or cluster of the SoC based on the BCI signal.

Disclosed is a reset semiconductor integrated circuit that outputs a reset signal in response to a power supply voltage of a monitoring target becoming lower than a predetermined level, the reset semiconductor integrated circuit including: a voltage detection circuit; an output stage including a CMOS circuit that generates and outputs a signal according to a detection result of the voltage detection circuit; a monitored voltage input terminal to which the power supply voltage of the monitoring target is input; a reference potential terminal to which a voltage as a reference potential of a circuit is applied; an external voltage terminal which is connected to a power supply voltage terminal of the output stage to allow a power supply voltage as an operation voltage of the output stage to be applied from outside; and an output terminal to output the signal generated by the output stage.

A semiconductor integrated circuit includes a first detection circuit and a second detection circuit. The first detection circuit is configured to assert a first signal until a first input voltage decreases from a first detection voltage to a first operating voltage limit, and to cause the first signal to enter an indeterminate state, upon occurrence of a condition in which the first input voltage decreases to be less than the first operating voltage limit. The second detection circuit is configured to assert a second signal until a second input voltage decreases from a second detection voltage to a second operating voltage limit, and to cause the second signal to enter an indeterminate state, upon occurrence of a condition in which the second input voltage decreases to be less than the second operating voltage limit.

The invention discloses a multi-core heterogeneous SOC local reset method, electronic equipment and a chip, the SOC is applied to a data acquisition terminal and comprises a security domain, an application domain and a resource management domain which are used for inter-core communication, and the data acquisition terminal is connected with an upper computer through PCIe. The method comprises the following steps: mapping a reset parameter register of a data acquisition terminal and a register of an interface controller to an upper computer; when the upper computer monitors that data transmission of the application domain is interrupted, a reset preparation signal is sent to the security domain; the security domain feeds back a reset confirmation signal to the upper computer and sends a reset instruction to the resource management domain and the application domain; in the process of resetting the application domain, the resource management domain closes resources of the application domain and clears data of the interface controller; after the application domain is reset, the application domain sends a clock resource initialization request to the security domain; and the security domain sends a reset completion signal to the upper computer. According to the method, the problems of important data loss, long reset time and the like caused by global reset can be solved.

Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

Examples described herein relate to a circuit board that includes a device, firmware memory, and a power controller. In some examples, the firmware memory is to store a firmware update and in response to a software-initiated command, the power controller is to reduce power to the device to cause a firmware update of the device and restore power to the device to cause execution of the firmware update. In some examples, the power controller is to reduce power solely to the device independent from power supply to at least one other device. In some examples, device configuration is saved prior to reduction of power to the device and restored to the device after power is restored to the device.

The invention relates to a power supply control circuit, a detection device, a countering device and an electronic device. The power supply control circuit comprises a main control module which outputs a state feedback signal according to an operation state. The power management module is connected with the power equipment and the main control module, and the power management module is used for converting power voltage of the power equipment into power supply voltage and outputting the power supply voltage to the main control module. And the switching circuit is respectively connected with the power supply equipment, the power supply management module and the main control module, and is used for controlling the power supply management module to stop outputting the power supply voltage under the condition that the state feedback signal does not reach the preset standard, so that the main control module is powered off. And the switching circuit is also used for controlling the power management module to output the power supply voltage again according to the received power supply voltage after the power management module is controlled to stop working, so that the main control module is restarted. By implementing the embodiment of the invention, power-off reset can be realized without manual adjustment, and convenience and practicability are improved.

The present disclosure discloses a fault recovery method. The method includes: in response to a server being powered on or reset, starting baseboard management controller firmware from one or more flash memories storing the baseboard management controller firmware; in response to a failure of the starting the baseboard management controller firmware from the flash memories, starting a boot loader from a flash memory in which the boot loader is burned; in response to the boot loader being successfully started, obtaining backup baseboard management controller firmware from an external storage device through the boot loader, and burning the backup baseboard management controller firmware to any one of the flash memories; and in response to the burning being completed, resetting the server, and enabling the flash memory to start the backup baseboard management controller firmware from the flash memory in which the backup baseboard management controller firmware is burned.

The invention provides a power-on and power-off control circuit and a multi-power-supply system, and relates to the field of power supply control, the circuit comprises a first control sub-circuit, the input end of the first control sub-circuit is connected with a first power supply, the output end of the first control sub-circuit is connected with a power utilization module, and the power supply end of the first control sub-circuit is connected with a second power supply; the first control sub-circuit is switched on to work under the condition that the second power supply is powered on, and the first control sub-circuit is used for controlling the power utilization module to work based on the output voltage of the first power supply. The reset signal is generated according to the size of the first power supply, whether the reset signal can be transmitted to the power utilization module or not is determined according to whether the second power supply is powered on or not, the power-on and power-off states of the first power supply can be known when the power utilization module receives the reset signal, and control over the power utilization module is achieved when the first power supply is powered on later and powered off first.

A communication device comprises: a communication interface; a display screen; a first processor configured to power up according to a first power-up time, the first processor for implementing radio functionality associated with the communication interface; and a second processor configured to power up according to a second power-up time longer than the first power-up time, the second processor for implementing extended functionality as compared to the first processor. The first processor, after the first power-up time: controls the display screen to provide a first GUI displaying communication interface-related information and a power-up status of the second processor; and after the second power-up time, hand off control of the display screen to the second processor. The second processor, after being provided with control of the display screen: controls the display screen to provide a second GUI displaying the communication interface-related information and information associated with the extended functionality.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The invention discloses a reset circuit, a reset method and a multi-core heterogeneous system. The reset circuit is applied to the multi-core heterogeneous system comprising at least two hardware domains. Each mutually isolated hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected with each processor core; each hardware domain and the operating system corresponding to each hardware domain form each domain system; each domain system accesses system resources through a system bus; the reset circuit comprises a monitoring module which is used for monitoring each monitored object and obtaining a monitoring signal for each monitored object; the first processing module is used for acquiring a target reset mode from at least two reset modes according to the monitoring signal; processing the monitoring signal based on the target reset mode to obtain a first reset signal; and the reset control module is used for controlling the output of a first reset signal, and the output first reset signal is used for resetting the monitored object matched with the target reset mode.

The present disclosure discloses a fault recovery method. The method includes: in response to a server being powered on or reset, starting baseboard management controller firmware from one or more flash memories storing the baseboard management controller firmware; in response to a failure of the starting the baseboard management controller firmware from the flash memories, starting a boot loader from a flash memory in which the boot loader is burned; in response to the boot loader being successfully started, obtaining backup baseboard management controller firmware from an external storage device through the boot loader, and burning the backup baseboard management controller firmware to any one of the flash memories; and in response to the burning being completed, resetting the server, and enabling the flash memory to start the backup baseboard management controller firmware from the flash memory in which the backup baseboard management controller firmware is burned.

A request to update first configuration data associated with a first tenant of a multi-tenant system is received. The first configuration data can be included in a first shard residing at a first node of the system. The first shard can also include second configuration data associated with a second tenant. Upon initiation of an operation to update the first configuration data at the first node in accordance with the first request, an anomaly associated with the update at the first node is detected. A request to access the second configuration data is received. A second node that includes a second shard that includes the second configuration data is identified. An operation is performed to provide the second tenant with access to the second configuration data at the second node before the anomaly associated with the update to the first configuration data is resolved.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

The invention discloses a chip reset control method and device, equipment and a medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target chip comprising a plurality of functional modules, and constructing a reset matrix for the target chip according to reset requirements of the functional modules; loading and analyzing the reset matrix to determine a reset trigger condition of each functional module, and based on the reset trigger condition, generating a multi-stage reset control signal conforming to a reset control strategy through a preset general reset control circuit; distributing the multi-stage reset control signal to each functional module according to a preset reset time sequence so as to control each functional module to perform reset operation; and adjusting the dynamic control dimension parameters in the reset matrix in real time by presetting a dynamic configuration interface so as to perform reset adjustment and optimization on the target chip after tape-out. Through the technical scheme of the invention, the problems of low efficiency, time sequence conflict and insufficient flexibility in the traditional reset design can be solved.

The invention discloses a chip reset circuit, a server and a mobile terminal, relates to the technical field of chip reset, and provides the chip reset circuit aiming at the problem that the reset of a CPU (Central Processing Unit) chip excessively depends on a CPLD (Complex Programmable Logic Device) chip at present. And a power-on ready signal is output to a backward stage through the time delay module. The post-stage reset control circuit can control whether to reset the CPU chip according to whether the reset trigger signal is received. Otherwise, a reset control signal is output all the time to prohibit the CPU chip from being started, so that the reset control requirement and the power-on time sequence management requirement of the CPU chip are met at the same time. And the circuit is completely realized by a hardware circuit and does not need to depend on complex devices such as a CPLD (Complex Programmable Logic Device), so that the reliability and the stability of the reset control of the CPU chip are greatly improved.