472results about "Data resetting" patented technology

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

The invention relates to the technical field of electronic systems of spacecrafts, and discloses a fault-tolerant method for non-redundant fault reconstruction of a spaceborne computer, which comprises the following steps of: 1, accessing a hardware state manager by a BIOS (Basic Input / Output System) after the system is started; obtaining health state data recording the health state of the local storage device, a current starting target ID used for indicating a current starting target, and a retry count value associated with the current starting target ID; a BIOS (Basic Input Output System) accesses a hardware state manager to obtain health state data and a retry count value of local storage equipment, so that normal equipment is autonomously selected for starting, and the fault-tolerant effect of dynamically avoiding a fault starting path is achieved; compared with the technical scheme in the prior art that the computer starting process highly depends on a solidified single physical storage device, the single-point fault risk of permanent paralysis of the computing system caused by damage of the single storage device is solved.

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

The invention discloses a chip reset control method and device, equipment and a medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target chip comprising a plurality of functional modules, and constructing a reset matrix for the target chip according to reset requirements of the functional modules; loading and analyzing the reset matrix to determine a reset trigger condition of each functional module, and based on the reset trigger condition, generating a multi-stage reset control signal conforming to a reset control strategy through a preset general reset control circuit; distributing the multi-stage reset control signal to each functional module according to a preset reset time sequence so as to control each functional module to perform reset operation; and adjusting the dynamic control dimension parameters in the reset matrix in real time by presetting a dynamic configuration interface so as to perform reset adjustment and optimization on the target chip after tape-out. Through the technical scheme of the invention, the problems of low efficiency, time sequence conflict and insufficient flexibility in the traditional reset design can be solved.

A low battery voltage protection method for a microcontroller system and a microcontroller system using the same are provided. The low battery protection method and the microcontroller system are used to prevent continuous battery drain by setting time thresholds and a count threshold. In an embodiment, when a low-voltage power-on reset voltage is not exceeded within a first preset time, the microcontroller system is forced to enter a sleep mode to prevent power consumption by an analog block. In another embodiment, when the low-voltage power-on reset voltage is exceeded, but a reset count of the microcontroller system exceeds a preset value within a second preset time, the microcontroller system is also forced to enter the sleep mode to prevent a digital block from continuously loading data, which could lead to battery failure.

The application provides a system and a control method for implementing a DSP reset process based on FPGA, and relates to the technical field of DSP reset. A first IO pin of the FPGA is connected with a reset pin of the DSP through a DSP reset line to control the reset process of the DSP. A second IO pin of the FPGA is connected with a GPIO pin of the DSP through a DSP state flag line to represent the reset state of the DSP, so that initial reset control and midway crash reset control are completed. The reset signal of the DSP is controlled by the FPGA, and the application has the characteristics of flexibility, time controllability, state controllability, field maintainability and the like, and effectively solves the two technical problems of power-on non-starting and midway crash of the DSP.

The invention relates to the technical field of chips, and provides a power-on control method and system, a chip, equipment and a storage medium, and the method comprises the steps: controlling a first power domain to be powered on, maintaining a second power domain to be in a power-off state, and driving a signal processing circuit to process an external input signal and output a target signal, the first power domain supplies power to the signal processing circuit, and the second power domain supplies power to a post-stage logic circuit; after determining that the target signal is in a stable state, controlling the second power domain to be powered on so as to start the post-stage logic circuit; wherein the started post-stage logic circuit carries out sampling processing on the target signal in a stable state. According to the invention, power domain division is carried out on the signal processing circuit and the post-stage logic circuit and time-sharing power-on of the signal processing circuit and the post-stage logic circuit is controlled, so that stable and effective signals can be always sampled by the post-stage logic circuit when the post-stage logic circuit is started, and the power-on reliability of a chip and the stability of a system are improved.

A method of updating software of an Electronic Control Unit (ECU) includes: downloading a boot loader to a boot area of a second memory bank in an inactive state, and downloading a firmware or data to a normal area, when a first memory bank is in an active state; setting the second memory bank, which is in the inactive state, as a memory bank to operate in the active state after a reset of the ECU; and resetting the ECU to cause the second memory bank to operate in the active state.

According to the memory controller and the microcontroller chip provided by the invention, time division multiplexing can be carried out on a built-in mirror image buffer area with relatively small capacity in the microcontroller according to actual start setting requirements, so that different contents in a nonvolatile memory can be copied to the mirror image buffer area in sequence in a time division manner; the central processing unit can read and run corresponding contents from the mirror image buffer area, and in the process of running the previously copied contents by the central processing unit or after the central processing unit finishes running, the previously copied contents can be partially or completely covered by the later copied contents, so that compared with the mirror image buffer area of the microcontroller in the prior art, the mirror image buffer area of the microcontroller has the advantages that the reliability of the microcontroller is improved; the hardware cost is saved, and the cost of a microcontroller chip is remarkably reduced. In addition, the content needing to be copied to the mirror image buffer area in the MCU chip power-on reset or system reset stage is reduced compared with the prior art, and therefore the system starting time can be remarkably shortened.

The present application relates to the technical field of computer communications. Disclosed are a method and apparatus for link reestablishment after a PCIe link equalization failure. The method comprises: determining a current state of a state machine and a state previous to the current state; when the current state is a speed recovery state and the previous state is an equalization recovery state, generating an initial reset request signal; after the initial reset request signal is generated, assigning a preset non-zero count value to a predefined counter, and starting decrement counting; and when the count value is not zero, generating a target reset pulse signal, wherein the target reset pulse signal is used for enabling the state machine to jump to a reset state. The present application uses direct hardware control, without the need for scheduling by a central processing unit; therefore, central processing unit and memory resources are not consumed, the impact on the overall system performance is relatively small, and a higher link reestablishment speed and a higher efficiency are achieved.

A wake-up method and an electronic device. When the electronic device enters a deep suspend state, the electronic device can automatically reboot, so that the electronic device restores to normal, and can be normally used by a user, thereby improving user experience. In the method, the electronic device starts timing. A suspend duration is obtained if a working state of the electronic device is a suspend state when a timing duration reaches a preset refresh period, where the suspend duration is a difference between a moment at which the electronic device enters the suspend state and a timing refresh moment. The electronic device triggers, if the suspend duration is greater than or equal to a first preset threshold, an operation of rebooting a system.

A method for recording data and an apparatus, an electronic device and a non-transitory computer readable storage medium is provided, and relates to the field of computer technologies. The method includes: configuring a BIOS and a BMC to share a shared memory of a CPU respectively, wherein the shared memory is a preset area of a memory mounted by the CPU; establishing a rule for using the shared memory for the BIOS and the BMC; when a server is started, checking a shared channel for the shared memory to determine whether the shared memory is successfully initialized; and transferring data related to RAS collected by the BIOS to the BMC via the shared memory based on the rule for using the shared memory, in a case where the shared memory is successfully initialized.

To provide a system that implements a state suspension for optimizing a start-up process of an autonomous vehicle.SOLUTION: Diagnostics and boot up for AV hardware and software of a computer system of an autonomous vehicle may be performed based at least on receiving a shutdown or power off indication, then a computing state of the computer system may be suspended with the computer system entering a low-power mode. The suspended computing state can be rapidly restored without requiring a reboot and diagnostics for key-on. To ensure integrity of the saved computing state, the computer system may exit the low-power mode, rerun the diagnostics, reload the programs, and then reenter the low-power mode. Restoring the suspended computing state may be triggered by a user inserting an ignition key, pressing a button to turn on the vehicle, opening a door to the vehicle, remotely unlocking the vehicle, remotely starting the vehicle, etc.SELECTED DRAWING: Figure 1

The application discloses a reset circuit and a vehicle-mounted Ethernet PHY chip reset system. The reset circuit comprises an Ethernet SWITCH unit, an MCU unit, a PHY chip unit and a reset chip unit. The Ethernet SWITCH unit is connected with a plurality of the PHY chip units. The plurality of the PHY chip units are connected with the reset chip unit. The Ethernet SWITCH unit is connected with the MCU unit. The MCU unit is connected with the reset chip unit. The reset circuit provided by the application can be reset in multiple ways. The reset circuit provided by the application has improved reliability, functionality and flexibility in a vehicle-mounted environment.

Embodiments of this application disclose an electronic device and a related reset restoring method. The electronic device includes a first processor core, a second processor core, and a power management unit. A first output pin of the first processor core is connected to a first input pin of the second processor core, a first reset pin of the first processor core is connected to a first control pin of the second processor core, and a second reset pin of the second processor core is separately connected to a second control pin of the first processor core and a third control pin of the power management unit. The second processor core is configured to: enter, by the second processor core, a reset state after the second reset pin of the second processor core receives a reset signal; and determine whether the first input pin is in a first state, and if the first input pin is in the first state, send a reset signal to the first reset pin by using the first control pin, for the first processor core to enter a reset state. According to embodiments of this application, a reset operation can be implemented when the electronic device is not completely powered off.

The application provides a PCIe data link recovery method and a PCIe system, and relates to the technical field of PCIe communication technology.When it is determined that the current board card is an EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is a low level; wherein the MODprel signal is used to indicate whether an optical module is in place; if the MODprel signal is a low level, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is a low level; wherein the first RXLOS signal is used to indicate whether an optical signal is in place; if yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so that the data link is recovered; wherein the RSSI signal is used to represent the size of optical power. The application has the effect that the PCIe system can automatically re-establish a chain after the optical module or the optical fiber line is plugged in or unplugged.

The present application belongs to the chip verification technical field, and particularly relates to a controllable clock reset signal generation module and method based on SV and UVM. The function module is used for providing the required clock reset signal as an excitation signal in a test platform. The module architecture comprises an rcc interface, an rcc configuration class, an rcc environment top layer, a sequence library, and an rcc transaction class. The rcc interface contains N virtual clock group interfaces. The rcc configuration class defines a clock reset group agent number variable and N clock group configurations. The rcc environment top layer declares an rcc virtual interface handle, an rcc configuration handle, and N clock reset group agents. The sequence library contains four function sequences for controlling the clock signal and the reset release signal in the excitation signal. The rcc transaction class creates N clk transaction classes and encapsulates the attribute configuration of the corresponding clock reset. The present application overcomes the problems of the traditional verification platform, such as the clock reset signal being unable to be flexibly edited, low verification efficiency, high error rate and the like.

An electronic circuit is disclosed. The circuit includes power voltage monitoring circuits (610, 700) to monitor a main power voltage (MPS) provided to a first circuit configured to operate in a main power domain (MPD), generate a main power domain monitor signal (MUL, MLL) based on the main power voltage (MPS), monitor a second power voltage (SPS) provided to a second circuit to operate in a second power domain (SPD), and generate a second power domain monitor signal (2UL, 2LL) based on the second power voltage (SPS); a non-volatile memory (650) to store data indicating an expected power domain value for the second power domain (SPD); a mask register (630, 640) to receive and store data from the non-volatile memory (650) indicating the expected power domain value for the second power domain (SPD); and a controller (620) to generate a power status signal (OUT) for the second power domain (SPD) based on data (PD2 MASK) of the mask register (630), the main power domain monitor signal (MUL, MLL), and the second power domain monitor signal (2UL, 2LL).

An apparatus, system, and method are provided that improve communication between a memory device and a controller. A data communication apparatus includes a transceiver coupled to a data path and configured to send or receive data over the data path, and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether any device is allowed to occupy the data path. The interrupt circuit generates an interrupt signal to prevent another device from accessing the data path in response to an activation signal to send or receive data by the transceiver.

The invention discloses a power station arc discharge data acquisition control method, which comprises the following steps of: after equipment is electrified, carrying out equipment self-inspection to ensure that each piece of equipment in a system can operate normally and the equipment is accurately positioned when the equipment is abnormal, and ensuring that the abnormal equipment is quickly positioned and repaired; by automatically matching an actual data acquisition scene according to the current environment, the data acquisition efficiency and accuracy are improved, meanwhile, in order to protect equipment, a time interval is increased when an impedance network is set, and due to the increase of the time, secondary scene information checking is added for the accuracy of an arc discharge data scene label, so that the accuracy of the arc discharge data scene label is improved. Data is matched with scene information as much as possible; scene configuration information is obtained in real time before execution each time, and the scene configuration information is synchronously updated to a scene configuration file after data acquisition is completed; it is ensured that data cannot be collected repeatedly when execution is started next time if the data collection is abnormal midway or manually interrupted, errors possibly caused by manual intervention are reduced, and the use threshold of a control system is lowered.

The utility model relates to the technical field of servers, and discloses a CMOS data clearing device and a liquid cooling system.The device comprises a microcontroller and a switch unit, the microcontroller comprises a first pin, the switch unit comprises a second pin, a third pin and a fourth pin, the first pin is electrically connected with the second pin, and the third pin is electrically connected with the fourth pin. The third pin and the fourth pin are respectively used for being electrically connected with an RTC pin and a GND pin of a CMOS jumper wire of the server; the microcontroller is used for sending a first signal to the second pin through the first pin when receiving a control signal, so that the third pin and the fourth pin are conducted. By means of the mode, the efficiency of clearing the CMOS data in the server is improved.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

A method of handling a firmware update for a device is disclosed, comprising: determining a device to be in an updatable state; setting the device into an updating state after determining the updatable state; and after the device is in the updating state, writing a firmware update to memory for the device. After writing the firmware update, the device is switchable to a working state in which the device operates based on the firmware update.

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

Handling resets comprises communicating transport packets between a transport network and data processing circuitry, with at least a portion of the data processing circuitry operating in a given reset

The disclosed technology is directed to a computing device for handling system management interruptions if an emergency response is desired. In some examples, a computing device includes a memory controller and a processor. The memory controller, in response to determining that the memory access matches the attack pattern, sets the register to a value and triggers a system management interrupt. When a system management interrupt is detected, the processor causes the first thread to enter a system management mode. The first thread then accesses the register. A power reset on the computing device is triggered in response to determining that the register is set to the value without waiting for remaining threads to enter a system management mode.

An information handling system battery interfaces with a motherboard through a connector and receptacle that contribute to a standardized coupling arrangement while accommodating a wide variety of footprints and component configurations. The connector terminates to pin terminals that mount to a circuit board and gap terminals that accept a wire to accommodate different coupling arrangements. The connector conductive elements slide horizontally into receptacle conductive members or alternatively press down for a vertical coupling. Insertion of the battery connector into the battery receptacle completes a circuit detected by an embedded controller that can selectively reset the system in the event of a hangup.