93 results about "Logic element" patented technology

The invention relates to the field of document processing, and particularly provides a document format processing method, system, terminal and medium based on a large language model.The method comprises the steps that a generation instruction containing a target document type and a source material are received, and original text content is generated through the large language model integrating domain knowledge; obtaining a matched structured format template, and analyzing the style rule into a format instruction set; identifying logic elements and hierarchical relationships thereof in the original text based on a natural language processing technology; performing association mapping on the format instruction and the logic element, and performing automatic style rendering by calling a document object model interface to generate an intermediate document with a standard format; and finally, outputting after quality verification. According to the method, an automatic process of content generation and intelligent formatting is constructed, and the document writing efficiency and normalization are improved.

The invention provides a query statement generation method and device, electronic equipment and a storage medium, and relates to the field of artificial intelligence, in particular to the field of computers, the field of databases and the field of deep learning. The query statement generation method comprises the steps of performing intention recognition on a demand text based on business data to obtain a demand intention; in response to the demand intention meeting a preset demand condition, processing the demand intention by using a language model to obtain an execution logic structure, the execution logic structure comprising a plurality of execution logic elements based on structured representation, and a structured relationship among the plurality of execution logic elements representing an execution process of executing the query statement; determining target mode information matched with the text semantics represented by the execution logic element from preset database mode information; performing semantic understanding on the plurality of execution logic elements and the target mode information by utilizing a language model, and outputting a plurality of pieces of intermediate structured data for describing the query statement; and generating a query statement according to the intermediate structured data.

Methods of arbitrating between requestors and a shared resource wherein for each processing cycle a plurality of select signals are generated and then used by decision nodes in a binary decision tree to select a requestor. The select signals are generated using valid bits and priority bits. Each valid bit corresponds to one of the requestors and indicates whether, in the processing cycle, the requestor is requesting access to the shared resource. Each priority bit corresponds one of the requestors and indicates whether, in the processing cycle, the requestor has priority. Corresponding valid bit and priority bits are combined in an AND logic element to generate a valid_and_priority bit for each requestor. Pair-wise OR-reduction is then performed on both the valid bits and the valid_and_priority bits to generate additional valid bits and valid_and_priority bits for sets of requestors and these are then used to generate the select signal.

A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.

Ultrasound image devices, systems, and methods are provided. An intraluminal ultrasound imaging system, comprising a patient interface module (PIM) in communication with an intraluminal imaging device comprising an ultrasound imaging component, the PIM comprising a first reconfigurable logic block including a first plurality of logic elements interconnected by first reconfigurable interconnection elements; a configuration memory coupled to the first reconfigurable logic block; and a processing component coupled to the configuration memory, the processing component configured to detect a device attribute of the intraluminal imaging device in communication with the PIM; and load at least one of a first configuration or a second configuration to the configuration memory based on the detected device attribute to configure one or more of the first reconfigurable interconnection elements such that the first plurality of logic elements are interconnected for communication with the ultrasound imaging component.

A computer system includes two or more devices connected to each other. Each of the devices includes a switch core, port logic elements connected to the switch core that each include a transmit replay buffer and receive logic, and physical layers connected to the port logic elements. In response to a link failure between a first port logic element of a first device and a second device, the first port logic element enters a loopback mode. In the loopback mode, an in-flight data packet including acknowledged data segments and unacknowledged data segments is looped back from the transmit replay buffer and the port receive logic of the first port logic element to the switch core, and from the switch core to a second port logic element to avoid loss of in-flight data.

A new inverting logic gate or a FET gate driver is disclosed. The logic gate mitigates the trade-off between power dissipation (or quiescent power) and slew rate of the typical RTL and DLL buffers by using an innovative circuit topology involving a pull-up bootstrapping transistor. The bootstrapping transistor may be an enhancement mode GaN field effect transistor (FET). This bootstrapping transistor may be driven by the complement of the input signal. Alternatively, the bootstrapping transistor may monitor the drain terminal of the pull-down transistor and conduct current accordingly. Other Boolean functions may also be achieved using this approach.

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

In some embodiments, a storage device includes a printed circuit board, a memory device coupled to the printed circuit board, a storage controller which controls the memory device and is coupled to the printed circuit board, an active interposer including a logic element coupled to the printed circuit board, a sensor disposed inside the active interposer and configured to sense an impact and provide a sensor signal of the impact to the storage controller, and a strain gauge disposed inside the active interposer and configured to measure a physical strain and provide a signal about the physical strain to the storage controller.

The invention relates to a network planning method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: receiving business demand information input by a user, and performing intention analysis on the business demand information to obtain a structured intention object; converting the intention object into a logic element, and adding the logic element into a preset meta-model to trigger a logic element updating event; the meta-model is used for providing semantic standards of logic elements and data elements; responding to the logic element updating event through a co-processing framework, and calling an intelligent mapping engine to convert the logic element into a corresponding data parameter; and filling the data parameters in a data filling interface, and generating a network planning scheme containing the logic elements and the data parameters. By adopting the method, collaboration of a logic arrangement layer and a data filling layer can be realized, and the problem that logic design and data filling are disjointed is solved.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes: parsing sequential FHE logic gate code; transforming the FHE logic gate code into a set of code modules, each code module in the set of code modules having an input and an output that is a function of the input and not passing control to other functions; creating node wrappers around each code module; configuring at least one of the main processing cores to implement an equivalent logic element of each element in a streaming mode of operation, wherein a data stream flowing out of a corresponding arithmetic logic unit flows into main memory and into other arithmetic logic units among a plurality of arithmetic logic units.

A ternary logic element including a transistor and a switching element. The transistor includes a channel layer including silicon, an input electrode, an output electrode, and a control electrode. The switching element includes an emitter, a base extending from the emitter, and a collector extending from the base. When a first control voltage is applied to the control electrode, the ternary logic element outputs a first voltage, and when a second control voltage different from the first control voltage is applied to the control electrode, the ternary logic element outputs a second voltage different from the first voltage, and when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, the ternary logic element outputs a third voltage different from the first voltage and the second voltage.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a logic block and a p-bit block. The logic block includes a plurality of plurality of logic elements. The p-bit block includes a transistor, a first bit cell with a magnetic structure and at least one second bit cell with a resistance structure. The first bit cell with the magnetic structure is connected to one end of the transistor. The at least one second bit cell with the resistance structure is connected to another end of the transistor.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.

Scientific instrument support systems and related methods, computing devices, and computer readable media are disclosed herein. For example, in some embodiments, a scientific instrument support apparatus includes a first logic element to generate a first command frame including a flag having a first value; and a second logic element to transmit the first command frame to a first device. The first value indicates that the first device should ignore an operation indicated by the first command frame. The scientific instrument supporting device comprises a third logic element which is used for determining whether a confirmation signal indicating successful operation is received or not; and a fourth logic element for generating a second command frame including a flag having a second value upon receipt of the acknowledgement signal. The second value indicates that the first device should perform an operation indicated by the second command frame.

The invention relates to software quality verification, in particular to a software quality verification system and method for logic alignment of an execution path and a design blueprint, a design logic atlas construction module is used for converting extracted blueprint logic elements into a design logic atlas in a digraph form and providing a standardized design reference for logic alignment; the execution path atlas construction module is used for converting the collected key program execution track data into an execution path atlas consistent with the design logic atlas in structure; the logic alignment algorithm module is used for calculating map similarity based on a map editing distance, quantitatively evaluating logic consistency between a design logic map and an execution path map, and outputting a logic alignment score; the difference analysis engine is used for carrying out deep analysis on parts which are not successfully logically aligned, identifying logic difference types and carrying out risk level evaluation; according to the technical scheme provided by the invention, the defect that logic consistency verification is difficult to carry out on the program execution logic and the original design intention in the prior art can be effectively overcome.

A method for planning the design of partitions, each partition being for a programmable gate array and a plurality of program routines, the programmable gate array comprising different categories of logic elements at predetermined locations, the plurality of program routines comprising a first program routine and further program routines, comprising the following steps: providing for allocating a first partition of the programmable gate array to the first program routine and allocating further partitions to the further program routines; determining a demand for logic elements by the first program routine; matching this demand with resources of logic elements present in the first partition; and if the demand for logic elements by the first program routine exceeds the corresponding resources of the first partition, selecting logic elements of the corresponding category from the further partitions and transferring them to the first partition by changing the direction of a partition boundary between these partitions, the partition boundary extending in a curved manner in at least one section before and / or after its direction is changed.

To provide a programmable logic device (PLD) having a less number of switches and high reliability.SOLUTION: A PLD includes: first to third columns each having a plurality of logic elements (LE); a plurality of first to third wiring lines to which a signal output from LE of the first to third columns are respectively given; a plurality of fourth wiring lines to which a signal inputted to LE on the second column are respectively given; a plurality of groups each of which has at least a first switch and a second switch for selecting a conduction state or a non-conduction state according to a potential of a node to which a signal is given through the first switch; a fifth wiring line to which a predetermined potential is given; and a third switch for controlling electrical connection between the plurality of fourth wiring lines and the fifth wiring line. The plurality of first to third wiring lines are respectively provided between the first column and the second column or between the second column and the third column, and in one group of the plurality of groups selected according to the signal, and when the second switch becomes a conduction state, one of the plurality of first to third wiring lines is connected to one of the plurality of fourth wiring lines.SELECTED DRAWING: Figure 1

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

This bidirectional logic element is provided with: a function / inverse function control unit; a forward input unit; a forward information transmission unit; a reverse input unit; a reverse information transmission unit; a bidirectional function operation unit that performs a forward logical operation and also performs a reverse operation; a forward function transfer unit; and an inverse function transfer unit. The arithmetic device and the arithmetic method use the bidirectional logic element.

Stimuli-responsive sensor system (e.g. chemo-responsive, thermo-responsive, radiation-responsive), a digital logic element comprising a stimuli-responsive sensor system, a robotic system comprising a stimuli-responsive sensor system or a digital logic element and a method of detecting an external stimulus. The stimuli-responsive sensor system comprises a dielectric elastomer switch (1), preferably a pizeo-resistive elastomer) and a stimuli-responsive elastomer (2) that are configured to contact each other at a contact surface (3). The stimuli-responsive elastomer component (2) is configured to exert a pressure (by shrinking or swelling) on this contact surface (3) if an external stimulus interacts with the stimuli-responsive elastomer (2) and the dielectric elastomer switch (1) is configured to detect the pressure exerted on the contact surface (3) by the stimuli-responsive elastomer (2) and to generate an electric output signal in dependence of the detected pressure.

This bidirectional logic element is provided with a function / inverse function control unit, a forward input unit, a forward information transmission unit, a reverse input unit, a reverse information transmission unit, a bidirectional function operation unit for performing a forward logical operation and also performing a reverse operation, a forward function transmission unit, and a reverse function transmission unit. This operation device and operation method use the aforementioned bidirectional logic element.

Logic elements and methods of fabricating logic elements are provided. The semiconductor logic element includes an n-channel gate wrap around (n-GAA) field effect transistor on a substrate integrated with a p-channel gate wrap around (p-GAA) field effect transistor on the substrate, the p-channel gate wrap around (p-GAA) field effect transistor being adjacent to the n-channel gate wrap around (p-GAA) field effect transistor. The n-channel gate-around (n-GAA) field effect transistor has a structure comprising a plurality of layers comprising silicon and a respective plurality of layers comprising at least 25% germanium, which extend between a source region and a drain region and are alternately arranged in a stack pair, and the p-channel gate-all-around (p-GAA) field effect transistor has a plurality of layers comprising germanium in the range of from 5% to 15% and a respective plurality of layers comprising germanium of at least 25%, which are alternately arranged in a stack pair.

According to examples, a hardware component for acceleration of QUIC data packets includes a data store on which is stored a first table and a second table, in which the first table and the second table respectively store information corresponding to a direction in which the QUIC data packets are to flow through a network. The hardware component includes a plurality of logic elements that are to receive information for a QUIC connection, determine a direction of initiation of the QUIC connection, and cause the received information to be stored in one of the first table and the second table depending upon the determined direction of the QUIC connection initiation.

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.

The application discloses a hardware design security vulnerability qualitative analysis method and system, according to a mixed attribute label propagation logic element library and a mixed attribute model construction method based on discrete mapping, so that a corresponding mixed attribute model can be constructed for any HDL design in linear time; the label designed by the mixed attribute model integrates two types of attributes, so that the safety behavior related to the safety attribute and the clock attribute can be modeled simultaneously; the method provided by the application can realize effective discrimination of hardware Trojan horses and hardware time measurement channels by verifying the clock attribute and the safety attribute; the application is deployed in the design and verification stage of the EDA process, so that the HDL design security vulnerability can be detected early, and the design basis is provided for high-reliability hardware design.

An image sensor includes a stack structure including an active pixel region and a light-blocking region outside of the active pixel region. The stack structure includes a first substrate having a first surface and a second surface opposite to the first surface, and including unit pixels, a PD isolation pattern extending in a vertical direction to the first substrate in the active pixel region and the light-blocking region, and defining the unit pixels, an anti-reflective laminate including a lower insulating film and a conductive film sequentially stacked on the second surface, a light blocking layer on the anti-reflective laminate in the light-blocking region, and a second substrate including logic elements configured to drive the unit pixels. The lower insulating film includes an open region opening the second surface in the light-blocking region. The conductive film is coupled with the second surface through the open region of the lower insulating film.

A device includes a first register, a second register, a third register and a first logic element. The first register is configured to store first input data. The second register is configured to store first weight data. The third register is configured to output first output data according to each of the first input data and the first weight data. The first logic element is configured to control the first register according to each of first bit data and second bit data. The first bit data and the second bit data correspond to the first input data and the first weight data, respectively.