32 results about "Logic element" patented technology

The invention relates to the field of document processing, and particularly provides a document format processing method, system, terminal and medium based on a large language model.The method comprises the steps that a generation instruction containing a target document type and a source material are received, and original text content is generated through the large language model integrating domain knowledge; obtaining a matched structured format template, and analyzing the style rule into a format instruction set; identifying logic elements and hierarchical relationships thereof in the original text based on a natural language processing technology; performing association mapping on the format instruction and the logic element, and performing automatic style rendering by calling a document object model interface to generate an intermediate document with a standard format; and finally, outputting after quality verification. According to the method, an automatic process of content generation and intelligent formatting is constructed, and the document writing efficiency and normalization are improved.

A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

The invention relates to a network planning method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: receiving business demand information input by a user, and performing intention analysis on the business demand information to obtain a structured intention object; converting the intention object into a logic element, and adding the logic element into a preset meta-model to trigger a logic element updating event; the meta-model is used for providing semantic standards of logic elements and data elements; responding to the logic element updating event through a co-processing framework, and calling an intelligent mapping engine to convert the logic element into a corresponding data parameter; and filling the data parameters in a data filling interface, and generating a network planning scheme containing the logic elements and the data parameters. By adopting the method, collaboration of a logic arrangement layer and a data filling layer can be realized, and the problem that logic design and data filling are disjointed is solved.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a logic block and a p-bit block. The logic block includes a plurality of plurality of logic elements. The p-bit block includes a transistor, a first bit cell with a magnetic structure and at least one second bit cell with a resistance structure. The first bit cell with the magnetic structure is connected to one end of the transistor. The at least one second bit cell with the resistance structure is connected to another end of the transistor.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.

This bidirectional logic element is provided with: a function / inverse function control unit; a forward input unit; a forward information transmission unit; a reverse input unit; a reverse information transmission unit; a bidirectional function operation unit that performs a forward logical operation and also performs a reverse operation; a forward function transfer unit; and an inverse function transfer unit. The arithmetic device and the arithmetic method use the bidirectional logic element.

The application discloses a hardware design security vulnerability qualitative analysis method and system, according to a mixed attribute label propagation logic element library and a mixed attribute model construction method based on discrete mapping, so that a corresponding mixed attribute model can be constructed for any HDL design in linear time; the label designed by the mixed attribute model integrates two types of attributes, so that the safety behavior related to the safety attribute and the clock attribute can be modeled simultaneously; the method provided by the application can realize effective discrimination of hardware Trojan horses and hardware time measurement channels by verifying the clock attribute and the safety attribute; the application is deployed in the design and verification stage of the EDA process, so that the HDL design security vulnerability can be detected early, and the design basis is provided for high-reliability hardware design.

An image sensor includes a stack structure including an active pixel region and a light-blocking region outside of the active pixel region. The stack structure includes a first substrate having a first surface and a second surface opposite to the first surface, and including unit pixels, a PD isolation pattern extending in a vertical direction to the first substrate in the active pixel region and the light-blocking region, and defining the unit pixels, an anti-reflective laminate including a lower insulating film and a conductive film sequentially stacked on the second surface, a light blocking layer on the anti-reflective laminate in the light-blocking region, and a second substrate including logic elements configured to drive the unit pixels. The lower insulating film includes an open region opening the second surface in the light-blocking region. The conductive film is coupled with the second surface through the open region of the lower insulating film.

Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

To provide an image sensor with improved reliability.SOLUTION: The multilayer structure includes: a first substrate having an active pixel region in which a plurality of pixels are defined; and a pad region disposed on at least one side of the active pixel region, wherein the first substrate has a first surface and a second surface located opposite to the first surface, and wherein each of the plurality of pixels includes a photoelectric conversion region; a plurality of dielectric layers disposed on the first surface of the first substrate; and a nanoprism pattern arranged in at least one of the dielectric layers in the active pixel region, wherein the plurality of dielectric layers include: a meta-optical structure having a pad opening that exposes a bonding pad in the pad region; a passivation layer covering a portion of the plurality of dielectric layers provided on a side wall of the pad opening; and a second substrate disposed on the second surface of the first substrate, on which a logic element for driving the plurality of pixels is formed.SELECTED DRAWING: Figure 3

This application provides a timing path screening method and apparatus, relating to the field of integrated circuit technology. The method includes: acquiring each clock port corresponding to each clock cycle in the chip under test, and determining the timing paths associated with the timing logic elements corresponding to each clock port; calculating the clock offset corresponding to each timing path; using a ST (Scheduling and Timing) tool to determine the actual hold time margin of each timing path; and determining whether each timing path has a timing violation risk based on the clock offset and the actual hold time margin. This application can accurately screen out timing paths with timing violation risks due to clock offsets, thereby improving chip yield.

A system and method for debugging logic elements in a configurable logic block using only one pin. A synchronization pulse is generated, and each logic element is connected, in turn, using a digital selector switch. The synchronization pulse and a logic state of each logic element are received, in turn, by an output buffer. First, second, and third digital outputs levels are enabled on a single output line using a voltage divider configuration of resistors connected to the output line of the output buffer. The output levels include the synchronization pulse, a low logic state, and a high logic state. The synchronization pulse and the logic state of each logic element are outputted as the different output levels, in turn, via a single debug pin connected to an oscilloscope or other display device for visualization. The debug pin may be shared with other functions when not being used for debugging.

The invention discloses a method for amplifying AND logic gate output efficient positive feedback signals based on coding double RCA, which comprises the following steps of: on the basis of realizing AND initial logic operation by a double catalytic activity center 8-17 DNAzyme AND logic element and a double rA site modified substrate probe, dividing a functional sequence of E6 DNAzyme into two parts, and respectively coding the two parts into a ring template of the RCA; a new 3'end generated after the probe is cut is used as a primer of RCA, double rolling circle amplification is triggered through the primer, and the product is hybridized and assembled to enable E6 DNAzyme to recover activity, so that the catalytic action is exerted to cut the substrate probe, and positive feedback signal amplification under AND logic is realized.

To efficiently verify a control logic including a large number of logic elements without requiring an environment in which a dedicated application is installed.SOLUTION: The present disclosure relates to a control logic analysis device for analyzing a control logic for performing automatic control of plant equipment. The control logic analysis apparatus obtains binary data corresponding to the control logic, and converts the binary data into natural language data by performing decoding processing on the binary data. Based on the converted natural language data, a data frame in which logic element information on logic elements included in the control logic is listed is created.SELECTED DRAWING: Figure 3

The present disclosure relates to an integrated memory device comprising: - an array of memory cells with decoding and sensing circuitry; - a memory controller; - read and write circuitry associated with the sensing circuitry; - a logic circuit portion in the read and write circuitry comprising at least one logic element receiving a data stream on a data input and a clock signal on a clock input; - at least one programmable or trimmable delay element or circuit upstream of the data input or the clock input for self-trimming an internal timing of the at least one logic element by aligning the clock signal and / or the data stream in time. The present disclosure further relates to a method for setting an operating parameter of an integrated circuit, in particular for self-trimming an internal timing of the integrated circuit.

The invention discloses a dual microRNAs AND initial logic sensing system based on engineering 8-17 DNAzyme. The dual microRNAs AND initial logic sensing system comprises an 8-17 DNAzyme AND logic element with dual catalytic activity centers, two closed chains and a substrate probe, when miRNA-21 and miRNA-205 exist in a sample at the same time, the two closed chains are combined with two recognition arms of the AND logic element so as to close catalytic activity sites of the AND logic element, and when miRNA-21 and miRNA-205 exist in the sample at the same time, the two closed chains are removed through a strand displacement reaction, so that the catalytic activity of the AND logic element is activated, and a substrate probe is cut to generate a fluorescence signal; the method realizes AND logic gate operation recognition of double miRNAs, has the characteristics of high specificity, high sensitivity, visual output and the like, can be used for constructing a logic detection platform of tumor-related microRNAs, and has application potential in the aspect of early diagnosis of diseases.

The utility model relates to nuclear power technology field, concretely relates to a priority selection drive machine cabinet for nuclear power plant safety level instrument control system, including the cabinet body, the cabinet body is equipped with machine cabinet power supply device, signal transmission device, equipment drive device and priority drive machine case from top to bottom in proper order in it, signal transmission device links with upstream control system, signal transmission device links with priority drive machine case, and priority drive machine case links with equipment drive device, priority drive machine case includes terminal unit, IO card spare and priority control module, and priority drive machine case sets up a plurality of priority control modules according to the controlled equipment quantity, and priority control module is configured as receiving drive command and according to the priority height selection output drive command, the utility model replaces the complex circuit of relay and other logic elements, can save a large number of spaces under the condition of realizing same selection drive logic, reduces the system complexity, improves the reliability, reaches shorter response time.

The invention provides a packaging structure comprising at least two memory elements, an assembly structure and a preparation method thereof. The package structure includes a molded structure, a logic element, a non-volatile memory element and a volatile memory element. The molded structure includes a memory controller element, an interconnect element, and an encapsulant encapsulating the memory controller element and the interconnect element. The logic element is electrically connected with the interconnection element. The nonvolatile memory element and the volatile memory element are electrically connected with the logic element through the memory controller element. The volatile memory element is electrically connected with the nonvolatile memory element through the memory controller element.

A low thermal resistance device package and heatsink assembly may include a device package containing one or more logic elements with the logic elements thermally connected to one or more diamond dies in a manner that provides a thermally conductive connection between the logic elements through the one or more diamond dies and one or more heatsinks. Each heatsink contains one or more chambers configured for a fluid heat transfer medium. A reconstituted wafer product may include a plurality of diamond dies attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond. The first wafer may be a 300 millimeters sized wafer and the diamond dies may include four sector dies arranged in four sectors of the 300 millimeters sized wafer.

The invention comprises a method for authorizing an operating action sent from a first field device (FG1) to a second field device (FG2), the first field device (FG1) comprising at least one first sub-component (SK1), the first sub-component (SK1) being configured to enable the first field device (FG1) to perform at least one additional function, the second sub-component (SK1) being configured to enable the second field device (FG2) to perform at least one additional function. The first sub-component (SK1) has a first security element (SE1) in which the first logic element (LE1) and the first identification information (ID1) are stored, and wherein the second field device (FG2) is communicatively connected to the first field device (FG1) via a communication network (KN) and comprises at least one second sub-component (SK2) in which the first logic element (LE1) and the first identification information (ID1) are stored in the first security element (SE1). The second sub-component (SK2) is configured to enable the second field device (FG2) to perform at least one additional function, the second sub-component (SK2) having a second secure element (SE2), the second logic element (LE2) and the second identification information (ID2) being stored in the second secure element (SE2), comprising:-an operator initiating an operating action on the first field device (FG1), the second logic element (LE2) and the second identification information (ID2) being stored in the second secure element (SE2); the operating action relates to a second subassembly (SK2) on the second field device (FG2); checking the operating action by means of the second logic element (LE2); and-authorizing the operating action if the check is successful by the second logic element (LE2).

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

A neuromorphic circuit suitable for implementing a neural network includes word lines, pairs of complementary bit-lines, source lines, a set of elementary cells, and an electronic circuit implementing a neurone having an output. The electronic circuit includes a set of logic components, a counting unit, and a comparison unit having a comparator and a comparison voltage generator, the comparator being configured to compare the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit.

The invention provides a literature retrieval method and device, electronic equipment and a storage medium, and belongs to the technical field of natural language process.The method comprises the steps that a knowledge graph is constructed, and the knowledge graph comprises a knowledge network of multiple papers, the knowledge network of each thesis comprises logic nodes corresponding to text blocks obtained by segmenting the thesis, a connection relationship between the logic nodes, entity nodes and a connection relationship between the entity nodes and the logic nodes, the logic nodes represent a specific logic element, the logic element is a semantic unit forming a demonstration structure of the thesis, and the semantic unit is a semantic unit. The entity nodes are named entities in the papers; after a user query is received, determining an entity node and a logic node corresponding to the user query in the knowledge graph; and generating a retrieval result based on the entity node and the logic node. According to the method, the inherent defects in the aspects of semantic understanding shallow layer, logic structure deficiency and cross-domain query intention understanding in the prior art are overcome.

This application discloses a method, apparatus, device, and medium for upgrading integrated circuit firmware, belonging to the field of server technology. The method includes: receiving an instruction to upgrade the firmware of any signal enhancement integrated circuit; determining the signal enhancement integrated circuit to be upgraded based on the model information of the signal enhancement integrated circuit; loading a first firmware file from the storage medium corresponding to the signal enhancement integrated circuit to be upgraded via a logic element; obtaining a second firmware file; and writing the second firmware file into the storage medium corresponding to the signal enhancement integrated circuit to be upgraded via a first substrate management controller and the logic element to replace the first firmware file. This application shortens the time required for power-on firmware loading of the signal enhancement integrated circuit, provides a new firmware upgrade method for signal enhancement integrated circuits, and improves the efficiency of integrated circuit firmware upgrades.

A ballistic, asynchronous logic circuit includes a controlled barrier which has a reversible memory cell and a polarity filter. The polarity filter is inductively coupled to the reversible memory cell. The circuit includes first and second polarity separators connected to the controlled barrier. The circuit includes a circulator connected to the controlled barrier.

Communication buses with power-saving techniques applied are disclosed. In particular, in certain MIPI Alliance standards, such as, for example, the CPHY or the DPHY standards, are defined low-power modes. Aspects of the present disclosure contemplate turning off logic elements in a control circuit during such low-power modes to reduce power consumption that otherwise might occur. Further aspects of the present disclosure contemplate a variety of ways to select an appropriate amount of time for which the logic elements may be turned off in such low-power modes.

A system and method for debugging logic elements in a configurable logic block using only one pin. A synchronization pulse is generated, and each logic element is connected, in turn, using a digital selector switch. The synchronization pulse and a logic state of each logic element are received, in turn, by an output buffer. First, second, and third digital outputs levels are enabled on a single output line using a voltage divider configuration of resistors connected to the output line of the output buffer. The output levels include the synchronization pulse, a low logic state, and a high logic state. The synchronization pulse and the logic state of each logic element are outputted as the different output levels, in turn, via a single debug pin connected to an oscilloscope or other display device for visualization. The debug pin may be shared with other functions when not being used for debugging.

The invention relates to the technical field of vehicle evacuation, in particular to a vehicle evacuation tripping device and a tripping method.The vehicle evacuation tripping device comprises a first connecting piece, a second connecting piece and a third connecting piece, one end of the second connecting piece is arranged on the rotary lock catch, and the other end of the second connecting piece is rotationally connected with the first connecting piece; the fixing piece is detachably arranged between the first connecting piece and the second connecting piece and used for limiting relative rotation of the first connecting piece and the second connecting piece. By means of ingenious arrangement of the first connecting end and the second connecting end of the traction rope, the two-stage step-by-step action of firstly relieving rotation limitation and then driving the lock catch to be separated is achieved only by means of the stroke difference of the traction rope in the stress state. The purely mechanical linkage design avoids the possible signal delay or failure problem of the electronic logic element in extreme environments such as high temperature, dense smoke and the like, and ensures the absolute reliability of the tripping action.