226results about "Power reduction in field effect transistors" patented technology

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

The present invention discloses a level conversion circuit and chip for converting an input signal in a first voltage domain into an output signal in a second voltage domain. The level conversion circuit includes: a switch unit including a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage; an input unit operating in the first voltage domain and connected to the second end of the first MOS transistor and the second end of the second MOS transistor; a conversion unit operating in the second voltage domain and connected to the first end of the first MOS transistor and the first end of the second MOS transistor; an output unit operating in the second voltage domain; and a clamping unit connected between the switch unit and a first low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage. The present invention reduces chip area and avoids power consumption caused by the DC current brought by the pull-down element.

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

The invention relates to a high-performance low-power-consumption anti-radiation latch capable of tolerating three-node upset, which preserves an original high-performance low-power-consumption anti-radiation latch structure capable of tolerating double-node upset and inherits the capability of tolerating single-node upset and double-node upset of an original circuit. Two extra redundant nodes are introduced and form an interlocking monitoring network with the original nodes through a three-input C unit; a TNU detection and recovery module composed of two three-input C units is additionally arranged outside an original DNU feedback loop, the module continuously monitors the state consistency of a key node group, when errors of three or more nodes are detected, redundant nodes are started for state reconstruction, and a correct value is output through a voting mechanism. According to the invention, the fault-tolerant capability of the latch is comprehensively improved from DNU to TNU under extremely low extra overhead, and meanwhile, the excellent characteristics of low power consumption and high performance of the latch are maintained, so that the ultimate requirements of modern aerospace and other severe radiation environments on the reliability of an integrated circuit are met.

A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.

The invention discloses a low-delay low-power-consumption level shift circuit, relates to the technical field of integrated circuits, and is used for solving the problem that in the prior art, a high-voltage level shift circuit usually has large delay and power consumption. Comprising a low-power-consumption level shift circuit, a rapid falling edge capture circuit, a rapid rising edge capture circuit and an RS trigger. The low-power-consumption level shift circuit is connected with the input end of the fast falling edge capture circuit and the input end of the fast rising edge capture circuit, and the output end of the fast falling edge capture circuit and the output end of the fast rising edge capture circuit are both connected with the RS trigger. According to the invention, nanosecond-level delay and nanoampere-level static power consumption are realized while low-voltage domain signals in a specific range are converted into high-voltage domain signals in a preset range.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

The invention belongs to the technical field of integrated circuits, and discloses a CML-to-CMOS logic circuit, a chip and electronic equipment. The CML-to-CMOS logic circuit comprises a CML signal-to-CMOS signal module which is used for converting an input CML differential clock into a CMOS differential clock and outputting the CMOS differential clock; and the duty ratio correction module is connected with a common mode node of the CML signal to CMOS signal module and is used for adjusting the common mode voltage of the CML signal to CMOS signal module so as to correct the duty ratio deviation of the CMOS differential clock. The common-mode voltage of the CML signal-to-CMOS signal module is directly adjusted, so that the duty ratio adjustment process is not affected by a CMOS transmission path, and the problem that the duty ratio adjustment power consumption is increased along with the lengthening of the CMOS transmission path is avoided. Therefore, correction of the CMOS differential clock duty ratio deviation is realized with low power consumption.

The semiconductor device comprises a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line and having gates connected to drains,a first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor.,

To provide a comparator circuit and a drive circuit with low power consumption.SOLUTION: A comparator circuit 30 comprises: a comparator element 31 that outputs an accordance signal indicating whether or not a value of a first input signal and a value of a second input signal are agreed with each other; an FF circuit 33 that holds data of a data input terminal D on the basis of a comparator clock signal CMP_CLOCK and outputs an enable signal EN for stopping an operation of the comparator element 31; and an internal signal generation circuit that outputs an internal signal Z1 to the data input terminal D on the basis of the accordance signal Z and an output signal from the FF circuit 33.SELECTED DRAWING: Figure 1

The invention relates to a low-offset low-leakage sampling holding circuit and a control method, the low-offset low-leakage sampling holding circuit comprises a common-mode voltage generation circuit, a pre-sampling holding control circuit and an output-stage sampling holding circuit, the common-mode voltage generation circuit generates common-mode voltage VCM with driving capability for the pre-sampling holding control circuit; then the pre-sampling holding control circuit is combined with the common-mode voltage VCM, input voltage information and offset voltage information are sampled according to the input voltage VIN, the offset voltage information is counteracted in the pre-holding stage, the precision of the sampling information is improved, voltage information VOUT is output, and finally the output-stage sampling holding circuit processes the voltage information VOUT, so that the output-stage sampling holding control circuit outputs the output voltage VIN. The target voltage information VSAMPLE meeting the long-time storage requirement of the signal is output; according to the invention, the pre-sampling holding control circuit is designed, switches are reasonably switched to reduce imbalance, and the voltage difference between each stage of a switching tube in the output stage sampling holding circuit is reduced, so that electric leakage is reduced, and the storage time of input voltage information is prolonged.

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.

The application relates to a high-performance low-power anti-radiation latch tolerating three-node upset, which retains the original high-performance low-power anti-radiation latch structure tolerating double-node upset and inherits the capability of tolerating single-node and double-node upset of the original circuit. Two additional redundant nodes are introduced, and interlocking monitoring networks are formed by three-input C cells and original nodes; in addition to the original DNU feedback loop, a TNU detection and recovery module formed by two three-input C cells is newly added, the module continuously monitors the state consistency of the key node group, when three or more node errors are detected, the redundant node is enabled to perform state reconstruction, and the correct value is output through a voting mechanism. The fault-tolerant capability of the latch is comprehensively improved from DNU to TNU with a small additional cost, while the excellent characteristics of low power consumption and high performance are maintained, so that the ultimate requirement of integrated circuit reliability in modern aerospace and other harsh radiation environments is met.

Methods and devices for reducing the power consumption of level shifters in the absence of an input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the stable HIGH or LOW state. The described methods further include a delay element that serves to keep power consumption low in the case of slow input power supply ramps.

The invention provides an in-phase driving level conversion circuit with zero starting power consumption, which comprises a silicon carbide field effect transistor, a two-stage level inversion circuit used for controlling level inversion and connected to the silicon carbide field effect transistor, and a driving current amplification circuit used for driving the silicon carbide field effect transistor and connected to the two-stage level inversion circuit, the positive electrode of the circuit is connected to the driving current amplifying circuit; the two-stage level inversion circuit comprises a first field effect transistor and a second field effect transistor, the drain electrode of the first field effect transistor is connected with the grid electrode of the second field effect transistor, and the source electrode of the first field effect transistor and the source electrode of the second field effect transistor are jointly connected to the negative electrode of the circuit. The drain electrode of the second field effect transistor is connected to the grid electrode of the silicon carbide field effect transistor, and the source electrode of the second field effect transistor is connected with the source electrode of the silicon carbide field effect transistor; according to the invention, the level conversion function is ensured, and the standby energy consumption with zero power consumption is realized.

The present application discloses a low-power-consumption self-biased slew-rate-enhanced circuit and an integrator. The enhanced circuit comprises: a self-biased control circuit used for outputting a bias voltage on the basis of an output voltage of an input voltage measurement circuit; the input voltage measurement circuit connected to the self-biased control circuit and used for measuring the magnitude of a differential input voltage; and a slew rate control circuit used for providing, when the voltage of a differential input voltage end exceeds a starting voltage, a sourcing current or a sinking current for an output end of an operational amplifier, and when the voltage of the differential input voltage end does not exceed the starting voltage, not generating an additional current or not generating a slew rate enhancement effect. In the present invention, an additional bias voltage or bias current does not need to be input, a static current is not consumed when the function of the slew-rate-enhanced circuit is not enabled, and a static bias current of an operational amplifier does not need to be increased when the slew-rate-enhanced circuit is started, so that fast charging and discharging of a large capacitance load can be achieved without affecting a small signal frequency domain characteristic of the operational amplifier, and a bidirectional slew rate of the operational amplifier is enhanced, thereby meeting low-power consumption and high-speed design requirements of an integrated circuit.

The application claims a kind of fast level shift circuit for power management chip, including level shift core circuit and low delay path detection circuit.The application uses resistance R1 to make PMOS tube M5-M6 drain voltage can quickly from V DDH Drop to V SSH , improve circuit transient characteristics, shorten voltage conversion delay and reduce switching loss;Adopt PMOS tube M13-M14 to constitute pull-up MOS tube, make PMOS tube M5-M6 drain voltage quickly rise, reduce switching loss;Adopt gate, source and substrate short NMOS tube M7-M8 to realize diode, make PMOS tube M5-M6 drain low voltage not less than V SSH -0.7, improve circuit reliability, adopt inverter to realize delay chain technology, make corresponding NAND gate output a lower pulse signal, and then circuit output a high voltage signal consistent with input signal change, so as to realize high-performance fast level shift circuit.

The semiconductor device of the embodiment includes a circuit block and a clock circuit that provides a clock signal to the circuit block at a specific time. The clock circuit includes: an output circuit that outputs a clock signal to the circuit block; and a control circuit that controls the timing of the clock signal output by the output circuit. The threshold voltage of the transistor in the output circuit that at least uses the clock signal as an input / output signal is a first threshold voltage, and the threshold voltage of the transistor constituting the control circuit is a second threshold voltage that is higher than the first threshold voltage.

The invention relates to a smart switch with over-current protection during an idle mode state. A circuit is described that includes a power transistor connected between a power supply terminal and an output terminal, a control circuit coupled to a control electrode of the power transistor and configured to apply a control current to the control electrode to turn on or off the power transistor, and an overcurrent protection circuit connected to the power transistor. The circuit may be in a first mode (some functions of the circuit are inactive to reduce power consumption) and a second mode (all functions of the circuit are active). The overcurrent protection circuit is configured to cause the circuit to change from a first mode to a second mode when the circuit is in the first mode and a sense signal indicative of a current through the power transistor has reached a first threshold, which requires a specific transition time from the sense signal reaching the first threshold, and to cause the circuit to change from the first mode to the second mode when the sense signal reaches the second threshold. A discharge signal that reduces the control current applied to the control electrode is output during the transition time.

To provide a semiconductor device including a logic circuit with single polarity, and the like.SOLUTION: In a logic circuit formed of transistors with the same conductivity type, the decrease in output voltage is prevented using at least three transistors and a capacitor element. By using an oxide semiconductor in a semiconductor layer of a transistor, the logic circuit with high output voltage and high withstanding voltage can be obtained. In addition, by using the logic circuit, a semiconductor device with high output voltage and high withstanding voltage can be obtained.SELECTED DRAWING: Figure 12

The invention relates to a semiconductor device and a semiconductor system. The semiconductor device includes first and second power supply voltage lines to which a power supply voltage is supplied, a first impedance element provided between the first and second power supply voltage lines, first and second reference voltage lines to which a reference voltage is supplied, and a second impedance element provided between the first and second power supply voltage lines. A second impedance element provided between the first reference voltage line and the second reference voltage line, electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined process on an input signal, and first transistor as a P-channel MOS transistor provided in series between the second power supply voltage line and the second reference voltage line and having a gate connected to a drain, and method thereof and the second transistor is an N-channel MOS transistor.

A semiconductor device includes a first gate electrode, an insulating part, a source electrode, a drain electrode, and a contact part. The insulating part is on one surface of the first gate electrode. The source electrode is connected to the insulating part. The drain electrode is connected to the insulating part. The contact part is between the source electrode and the drain electrode and on the insulating part. The contact part contains an atomic layered material. The contact part has a second part contactable with a sample. The second surface is opposite to a first surface facing the insulating part. A surface of the insulating part, the surface facing the contact part, has an uneven structure with respect to the first gate electrode.

The invention discloses a zero-power-consumption power-on reset circuit which is characterized in that a power supply voltage division unit performs voltage division on input power supply voltage and then outputs a first signal to a voltage detection unit; the voltage detection unit outputs a high-level or low-level second signal to the inverting unit according to a comparison result of the first signal and a preset threshold value. The inverting unit performs shaping and inverting processing on the second signal, generates a third signal and transmits the third signal to the output shaping unit. And the output shaping unit is used for buffering and shaping the third signal and outputting a reset signal. The AND gate unit inputs a reset signal and a sixth signal output by the D trigger unit to generate a fourth signal. And the delay unit receives the fourth signal, delays the fourth signal, generates a fifth signal and inputs the fifth signal to the D trigger unit. And the D trigger unit respectively receives the reset signal and the fifth signal, generates a sixth signal, inputs the sixth signal to the power supply voltage dividing unit, and turns off the power supply voltage dividing unit, so that the whole reset circuit keeps a zero power consumption state.

The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.