390results about "Power reduction in field effect transistors" patented technology

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

The invention discloses an automatic direction induction level conversion circuit, which comprises a first voltage domain circuit and a second voltage domain circuit which have the same structure, and can automatically input an input signal A of the first voltage domain circuit to a second level conversion module through a first voltage domain circuit driving input module. A driving signal is output to a second voltage domain circuit to drive an output module to control weak driving and control a monostable circuit to generate corresponding strong driving at the same time, and a second signal B in the same phase is output; or similarly, the input signal B of the second voltage domain circuit is automatically converted into a first signal A with the same phase. According to the level conversion circuit, the transmission direction of the switching signal can be automatically sensed without an additional signal, bidirectional level conversion is realized, and the system structure is simplified; meanwhile, strong driving output is started in a short time through the monostable circuit, the output driving capacity and transmission speed are improved, strong driving output on the other side is closed through a feedback signal, and mistaken starting of the bidirectional level conversion circuit is avoided.

The invention relates to a high-voltage level shift circuit and a layout structure thereof, and the high-voltage level shift circuit comprises a pulse generation module which is used for receiving an input signal and generating a double-path low-voltage domain narrow pulse signal; the level shift module is used for receiving the low-voltage domain narrow pulse signal and converting the low-voltage domain narrow pulse signal into a corresponding double-path high-voltage domain narrow pulse signal; the voltage transient noise detection module is used for detecting voltage transient noise and generating a transient noise intensity signal; the voltage transient noise filtering module is used for filtering voltage transient noise based on the received transient noise intensity signal to generate a double-path high-voltage domain filtering signal; and the RS trigger is used for converting the received high-voltage domain filtering signal into a high-side power device driving signal. The common-mode noise filtering capability and the VS negative bias resisting capability of the voltage transient noise filtering module can be enhanced, the transmission delay of a chip is effectively reduced, and the width of a narrow pulse signal is free of loss in the transmission process, so that the dynamic power consumption is reduced.

The invention discloses a level shift circuit with a mixed structure, relates to the technical field of integrated circuits, and aims to solve the problems of long time delay and high power consumption of a level shift circuit in the prior art when the level shift circuit is converted between a low voltage domain and a high voltage domain. The circuit at least comprises a first current mirror level shift sub-circuit and a second current mirror level shift sub-circuit which are connected with a cross-coupling level shift sub-circuit; an output signal of the first current mirror level shift sub-circuit is used for reducing the pull-up strength of a first pull-up network in the cross-coupling level shift sub-circuit; the output signal of the second current mirror level shift sub-circuit is used for reducing the pull-up strength of a second pull-up network in the cross coupling level shift sub-circuit; the cross coupling level shift sub-circuit is used for cutting off quiescent current paths in the first current mirror level shift sub-circuit and the second current mirror level shift sub-circuit and realizing conversion between a low voltage domain and a high voltage domain of the circuit; therefore, level conversion between a low-voltage domain and a high-voltage domain is realized by picosecond-level delay and nanoampere-level static power consumption.

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

The present invention discloses a level conversion circuit and chip for converting an input signal in a first voltage domain into an output signal in a second voltage domain. The level conversion circuit includes: a switch unit including a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage; an input unit operating in the first voltage domain and connected to the second end of the first MOS transistor and the second end of the second MOS transistor; a conversion unit operating in the second voltage domain and connected to the first end of the first MOS transistor and the first end of the second MOS transistor; an output unit operating in the second voltage domain; and a clamping unit connected between the switch unit and a first low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage. The present invention reduces chip area and avoids power consumption caused by the DC current brought by the pull-down element.

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

The invention relates to an analog switch capable of transmitting positive and negative voltages beyond a power rail, and belongs to the technical field of circuit structures. According to the analog switch capable of transmitting the positive and negative voltages beyond the power supply rail, the control logic module is used for controlling one of the on function module and the off function module of the complementary charge pump to work so as to control the on-off of the switch module, so that the problem that a power supply is lower than a signal range can be solved without constructing a negative-voltage charge pump; positive and negative voltages can be transmitted beyond a power rail, signals are not distorted, and the power consumption and the cost of an analog switch chip are greatly reduced. And the switch module adopts two NMOS (N-channel metal oxide semiconductor) tubes which are connected back to back, so that the switch does not generate electric leakage under negative voltage, the VISO can be always kept higher than the potential of the substrate by processing positive and negative voltages of the isolating ring, and the isolating ring always keeps reverse bias on a parasitic diode of the P-type substrate.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

A complementary metal oxide semiconductor (CMOS)-to-current mode logic (CML) converter for converting a CMOS input signal into a CML output signal, including: a low-pass filter comprising a fixed resistor and a first fixed capacitor, and a swing width control circuit configured to adjust a swing width of a voltage swing of the CML output signal based on a common mode level, wherein the swing width control circuit includes: a second fixed capacitor; and a variable capacitor comprising a capacitor array.

The invention relates to a high-performance low-power-consumption anti-radiation latch capable of tolerating three-node upset, which preserves an original high-performance low-power-consumption anti-radiation latch structure capable of tolerating double-node upset and inherits the capability of tolerating single-node upset and double-node upset of an original circuit. Two extra redundant nodes are introduced and form an interlocking monitoring network with the original nodes through a three-input C unit; a TNU detection and recovery module composed of two three-input C units is additionally arranged outside an original DNU feedback loop, the module continuously monitors the state consistency of a key node group, when errors of three or more nodes are detected, redundant nodes are started for state reconstruction, and a correct value is output through a voting mechanism. According to the invention, the fault-tolerant capability of the latch is comprehensively improved from DNU to TNU under extremely low extra overhead, and meanwhile, the excellent characteristics of low power consumption and high performance of the latch are maintained, so that the ultimate requirements of modern aerospace and other severe radiation environments on the reliability of an integrated circuit are met.

A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.

The invention discloses a wide-input-range low-power-consumption level shift circuit, which relates to the technical field of electronic equipment and comprises a current mirror branch and a logic error diagnosis circuit. The current mirror branch is connected with the logic error diagnosis circuit; the current mirror branch at least comprises a first phase inverter and a second phase inverter; the first phase inverter and the second phase inverter are used for ensuring that the static power consumption is about zero and reducing the transient power consumption of the circuit; the logic error diagnosis circuit is used for ensuring that the input level is consistent with the output level. The level shift circuit is constructed by adopting the current mirror, so that the competitive relationship between an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) is avoided, and a wide input voltage range can be A phase inverter is inserted into a current mirror branch to reduce power consumption. The logic error diagnosis circuit avoids a logic error caused by inconsistent input and output levels of the shifter; level conversion in a wide input voltage range is achieved, low static power consumption and dynamic power consumption are achieved, and rail-to-rail output swing can be achieved.

The invention discloses a low-delay low-power-consumption level shift circuit, relates to the technical field of integrated circuits, and is used for solving the problem that in the prior art, a high-voltage level shift circuit usually has large delay and power consumption. Comprising a low-power-consumption level shift circuit, a rapid falling edge capture circuit, a rapid rising edge capture circuit and an RS trigger. The low-power-consumption level shift circuit is connected with the input end of the fast falling edge capture circuit and the input end of the fast rising edge capture circuit, and the output end of the fast falling edge capture circuit and the output end of the fast rising edge capture circuit are both connected with the RS trigger. According to the invention, nanosecond-level delay and nanoampere-level static power consumption are realized while low-voltage domain signals in a specific range are converted into high-voltage domain signals in a preset range.

A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

A power control apparatus for a non-volatile memory includes a reference voltage generator, an adjusting circuit and a switching circuit. The adjusting circuit receives a deep standby signal and an operation signal. The adjusting circuit generates a mode indicating signal and a control signal. The switching circuit is connected with a first node. A voltage at the first node is an operation voltage. In a deep standby mode, the ground voltage is connected with the first node through the switching circuit. In a normal operation mode, a supply voltage is connected with the first node through the switching circuit. In a standby mode, an adjustable resistance path is connected between the supply voltage and the first node. The resistance value of the adjustable resistance path is adjusted according to the control signal until the operation voltage is equal to the reference voltage.

The present application provides a level shift circuit, including: a first P-channel field effect transistor, whose source is connected to a first voltage, whose drain is connected to point A, and whose gate is connected to point B; a second P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to point B, and whose gate is connected to point A; a first N-channel field effect transistor, whose drain is connected to point A, and whose gate is connected to a first control signal; a second N-channel field effect transistor, whose drain is connected to point B, and whose gate is connected to a second control signal; a voltage output unit, whose input end is connected to point B, and whose output end is used to output a shifted target signal according to the voltage at point B; a first switch tube, whose input end is connected to a first voltage, whose output end is connected to point B, and whose gate is connected to a third control signal; and the first switch tube is used to turn on after the second N-channel field effect transistor is turned off. The present application can improve efficiency by setting the first switch tube to directly pull up the potential at point B.

The invention belongs to the technical field of integrated circuits, and discloses a CML-to-CMOS logic circuit, a chip and electronic equipment. The CML-to-CMOS logic circuit comprises a CML signal-to-CMOS signal module which is used for converting an input CML differential clock into a CMOS differential clock and outputting the CMOS differential clock; and the duty ratio correction module is connected with a common mode node of the CML signal to CMOS signal module and is used for adjusting the common mode voltage of the CML signal to CMOS signal module so as to correct the duty ratio deviation of the CMOS differential clock. The common-mode voltage of the CML signal-to-CMOS signal module is directly adjusted, so that the duty ratio adjustment process is not affected by a CMOS transmission path, and the problem that the duty ratio adjustment power consumption is increased along with the lengthening of the CMOS transmission path is avoided. Therefore, correction of the CMOS differential clock duty ratio deviation is realized with low power consumption.

The semiconductor device comprises a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line and having gates connected to drains,a first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor.,

To suppress the decrease in power supply capability even when a free area is necessary in a power supply switch circuit.SOLUTION: A semiconductor device includes a first power supply line, a second power supply line, an end cap, and a first power supply switch circuit including a first transistor and a second transistor. The first transistor is connected to the first power supply line and the second power supply line. The second transistor is connected to the first power supply line and the second power supply line. The first transistor includes a first number of first fins extending in a first direction in a plan view and arranged in a second direction, which is different from the first direction, in the plan view. The second transistor includes a second number of second fins extending in the first direction in the plan view and arranged in the second direction in the plan view. The first number is greater than the second number. The second transistor is disposed between the first transistor and the end cap in the plan view.SELECTED DRAWING: Figure 3

The embodiment of the invention provides a logic circuit and a driving method thereof, a digital chip and electronic equipment, relates to the technical field of transistors, and is used for reducing the power consumption of the logic circuit. The logic circuit comprises a first P-type transistor and a first N-type transistor, the control end of the first P-type transistor and the control end of the first N-type transistor are both connected with the input signal end, the first end of the first P-type transistor is connected with the power signal end, the second end of the first P-type transistor and the first end of the first N-type transistor are both connected with the output signal end, and the first end of the first N-type transistor is connected with the output signal end. The second end of the first N-type transistor is connected with the grounding end; the first P-type transistor and the first N-type transistor are super steep transistors; the voltage of an input signal transmitted by the input signal end and the voltage of an output signal transmitted by the output signal end are both smaller than the voltage of a power signal transmitted by the power signal end. The logic circuit can stably operate under the condition of non-full swing and is low in power consumption.

To provide a comparator circuit and a drive circuit with low power consumption.SOLUTION: A comparator circuit 30 comprises: a comparator element 31 that outputs an accordance signal indicating whether or not a value of a first input signal and a value of a second input signal are agreed with each other; an FF circuit 33 that holds data of a data input terminal D on the basis of a comparator clock signal CMP_CLOCK and outputs an enable signal EN for stopping an operation of the comparator element 31; and an internal signal generation circuit that outputs an internal signal Z1 to the data input terminal D on the basis of the accordance signal Z and an output signal from the FF circuit 33.SELECTED DRAWING: Figure 1

The invention relates to a low-offset low-leakage sampling holding circuit and a control method, the low-offset low-leakage sampling holding circuit comprises a common-mode voltage generation circuit, a pre-sampling holding control circuit and an output-stage sampling holding circuit, the common-mode voltage generation circuit generates common-mode voltage VCM with driving capability for the pre-sampling holding control circuit; then the pre-sampling holding control circuit is combined with the common-mode voltage VCM, input voltage information and offset voltage information are sampled according to the input voltage VIN, the offset voltage information is counteracted in the pre-holding stage, the precision of the sampling information is improved, voltage information VOUT is output, and finally the output-stage sampling holding circuit processes the voltage information VOUT, so that the output-stage sampling holding control circuit outputs the output voltage VIN. The target voltage information VSAMPLE meeting the long-time storage requirement of the signal is output; according to the invention, the pre-sampling holding control circuit is designed, switches are reasonably switched to reduce imbalance, and the voltage difference between each stage of a switching tube in the output stage sampling holding circuit is reduced, so that electric leakage is reduced, and the storage time of input voltage information is prolonged.

The invention discloses a level conversion circuit, which comprises a first latch module used for obtaining a first logic signal and a second logic signal with a level range from a second power supply voltage to a first reference ground according to an input signal with a level range from the first power supply voltage to the first reference ground, and the first logic signal and the second logic signal are complementary signals; the second latch module is used for obtaining a third logic signal of which the level range is from the second power supply voltage to the second reference ground according to the first logic signal and the second logic signal; the output shaping module is used for obtaining an output signal according to the third logic signal, and the level range of the output signal is from the second power supply voltage to the second reference ground; and the enabling control module is used for pulling down one of the first logic signal and the second logic signal to the first reference ground under the condition that the first power supply voltage is smaller than the set reference voltage, so that the level conversion circuit is prevented from outputting an unstable signal, and the reliability of the circuit is improved.

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

The present invention discloses an ultra-wide voltage range relative voltage difference level comparison circuit, comprising: a relative voltage difference level generation module, a transmission gate and a rail-to-rail comparator; the relative voltage difference level generation module generates a set of relative voltage difference levels based on a reference level, and the transmission gate is used to control one of the relative voltage difference levels to enter the rail-to-rail comparator for comparison with a comparison voltage to form a hysteresis window. The ultra-wide voltage range relative voltage difference level comparison circuit of the present invention changes the ordinary PMOS differential pair comparator or NMOS differential pair comparator in the prior art into a rail-to-rail comparator, and realizes an ultra-wide voltage range by changing the structure of the comparator; secondly, the present invention designs a relative voltage difference level generation module, which can not only realize an ultra-wide input voltage range, but also generate a relative voltage difference level signal of a wide voltage range, thereby realizing an ultra-wide voltage range relative voltage difference comparison function.