14results about "Power reduction in field effect transistors" patented technology

An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

A pulse signal output circuit capable of stable operation and a shift resistor including the same. One of the objectives is to provide [a service / product]. [Solution] A pulse signal output circuit according to one aspect of the disclosed invention includes a node connected to the output terminal. The channel length of the transistors that make up the system is the channel length of the transistor that functions as the output terminal. Make it larger than the length of the loop. This will suppress current leakage from the node and prevent leakage over a long period of time. This makes it possible to maintain a stable potential over a long period, preventing malfunctions in the pulse signal output circuit. It can be stopped.

Methods and devices to decrease the power consumption of level shifters in the absence of input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the HIGH or LOW steady state. The disclosed methods further include a delay element used to keep the power consumption low in the case of slow input power supply ramps.

To reduce power consumption in a driving circuit by reducing a driving voltage of the driving circuit.SOLUTION: An amplitude voltage of a signal IN1 can be increased and output by a level shifter circuit. Specifically, the amplitude voltage of the signal IN1 can be made high and output. Thus, an amplitude voltage of a circuit (shift register circuit, decoder circuit, etc.) outputting the signal IN can be reduced. Therefore, power consumption of the circuit can be reduced. In addition, a voltage applied to a transistor included in the circuit can be reduced, which can thus inhibit the transistor from deteriorating or be broken.SELECTED DRAWING: Figure 1

This application relates to the field of electronic technology and discloses a reference voltage output circuit, comprising: a digital to analog converter comprising a resistor string divider, a first multiplexer and a second multiplexer, generating multiple bits of divided voltages that are grouped and output to respective first multiplexers; a level shift circuit that boosts the divided voltage output by the digital to analog converter in a low power mode; a selection module comprising a third multiplexer, receiving the boosted divided voltage output by the level shift circuit or the divided voltage output by the digital to analog converter, and based on the mode selection signal, selecting the boosted divided voltage for differential output in the low power mode or selects the divided voltage output by the digital to analog converter for differential output in a non-low power mode; an output buffer comprising a bias circuit, an operational amplifier, and an output stage circuit, the operational amplifier receives the differential voltages output by the selection module and amplifies the differential voltages, the output stage circuit converts the amplified differential voltages into a single ended voltage and outputs it as a reference voltage. The present invention can provide a reference voltage that is simultaneously universally applicable to different standards.

The challenge is to reduce the drive voltage of the drive circuit and thereby reduce the power consumption of the drive circuit. ru. [Solution] A level shifter circuit increases the amplitude voltage of signal IN1 and outputs it. This is possible. Specifically, the amplitude voltage of signal IN1 can be increased and output. This causes the vibration of the circuit that outputs the signal IN (shift register circuit, decoder circuit, etc.) The voltage range can be reduced. Therefore, the power consumption of the circuit can be reduced. Alternatively, the voltage applied to the transistors constituting the circuit can be reduced. Therefore, degradation or destruction of the transistor can be suppressed.

A semiconductor device includes a first transistor, a second transistor and a multiplexer. The first transistor is controlled by a first control signal. The second transistor is coupled in series with the first transistor, and is controlled by a first voltage signal. The multiplexer is configured to generate the first voltage signal according to the first control signal.

A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

According to one embodiment, a semiconductor device includes a first terminal which is coupled to a first node and to which a control signal is externally input, a first circuit coupled to the first node, configured to switch based on a logic level of the first node between a first state where a first voltage is not output to a second node and a second state where the first voltage is output to the second node, and configured to control a slew rate of an output voltage at a time of switching from the first state to the second state, and a second circuit including a switch circuit which includes one end coupled to the first node and another end applied with a second voltage, and configured to control the switch circuit based on a voltage at the second node.

Some embodiments include apparatuses and methods of making the apparatuses. One of the apparatuses includes: a first supply node (V2); a second supply node (140); and a driver (110). The driver includes a first input path (221), a second input path (222), an output node (205), a first N-type transistor (M1), a second N-type transistor (M2), and a resistor (M3). The first N-type transistor (M1) includes a gate coupled to the first input path, a first terminal coupled to the first supply node, and a second terminal coupled to the output node. The second N-type transistor includes a gate coupled to the second input path, a first terminal coupled to the output node, and a second terminal. The resistor is coupled between the second terminal of the second N-type transistor and the second supply node.

An object of the invention is to reduce reflux of an operating current of an electronic circuit provided with a plurality of transistor circuits. The electronic circuit includes a first power supply line, a second power supply line, a third power supply line, a first transistor circuit, and a second transistor circuit. A positive power supply voltage is applied to the first power supply line. A negative power supply voltage is applied to the second power supply line. An intermediate voltage between the positive power supply voltage and the negative power supply voltage is applied to the third power supply line. The first transistor circuit is connected between the first power supply line and the third power supply line. The second transistor circuit is connected between the second power supply line and the third power supply line.