One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable
system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in
system memory and stores the command information in a
queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a
queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status. The disk drive can
signal that it is ready to execute the programmed command, or it can
signal that it is not ready to perform the programmed command but is ready to receive additional command
programming information corresponding to another
queue entry, or it may
signal that it is ready to execute a previously programmed command. The disk drive host controller then performs the required operations using the information stored in the queue without involving the processor. Because the processor is only involved in setting up a command block in
system memory and in signaling the disk drive host controller that the command block is ready for reading, the processor is freed up to perform other tasks and overall system performance is improved.