356 results about "Cascode" patented technology

Disclosed herein is a single photon avalanche diode (SPAD) pixel circuit, including a SPAD having an anode coupled to a negative voltage and a cathode and a cascode transistor having a drain coupled to the cathode of the SPAD, a gate controlled by a cascode control signal, and a source. A readout circuit is coupled to the source of the cascode transistor and configured to detect a voltage change at the source of the cascode transistor and generate a pulse indicating an occurrence of an avalanche event. An active quenching circuit is coupled to the cathode of the SPAD and configured to detect an onset of the avalanche event and pull the cathode of the SPAD to a negative voltage to quench the avalanche event.

The embodiment of the utility model discloses a cascode cascade device which is applied to the technical field of semiconductor manufacturing. In a cascode cascade device, a source electrode and a grid electrode of a low-voltage enhanced field effect transistor are respectively used as a source electrode end and a grid electrode end of the cascade device, and a drain electrode of a high-voltage enhanced field effect transistor is used as a drain electrode end of the cascade device, so that a balancing circuit and an adjusting circuit can be integrated on the low-voltage enhanced field effect transistor; and the balancing circuit and the adjusting circuit only relate to the resistor and the diode, and when the resistor and the diode are integrated on the low-voltage enhanced field effect transistor, only one mask needs to be added, so that the process cost is relatively low. And redundant devices do not need to be integrated on the high-voltage field-effect tube in the cascade device, so that the area of the high-voltage field-effect tube is saved, and the overall cost of the cascade device is relatively low.

The invention provides a low-noise amplifier and a radio frequency front-end module, and the low-noise amplifier comprises an input matching circuit, a first-stage power amplification circuit, an inter-stage matching circuit, a second-stage power amplification circuit and an output matching circuit. The inter-stage matching circuit comprises a first inductor, a second inductor and a first capacitor; the second-stage power amplification circuit is of a cascode structure; and the output matching circuit comprises a third inductor and a fourth inductor which are coupled with each other. According to the low-noise amplifier, the high-frequency gain, the in-band gain flatness, the isolation degree, the stability and the output matching bandwidth of the low-noise amplifier can be improved.

An electronic device may include wireless circuitry having a transformer with a primary coil and a secondary coil, a first series inductor coupled to the primary coil, a second series inductor coupled to the primary coil, and a filter inductor inductively coupled to the first and second series inductors and operable to produce a first filter response when the wireless circuitry is operable in a first mode and a second filter response when the wireless circuitry is operable in a second mode. The transformer can be coupled to another filter inductor. The transformer can be coupled to an active circuit. The active circuit can include input transistors and cascode transistors. The cascode transistors can be coupled to resistors and / or capacitors that are selectively activated using associated filter switches.

The invention provides a millimeter wave digital power amplifier based on a serial transmission line balun synthesis network, and belongs to the technical field of millimeter wave digital power amplifiers. According to the millimeter wave digital power amplifier, firstly, a driving power distribution network based on a bridge and a transformer is adopted, and radio frequency power is subjected to differential conversion and then input into a digital power amplifier unit array; secondly, the digital power amplifier unit adopts a differential Cascode structure with a neutralizing capacitor, so that the gain and the output impedance of the digital power amplifier unit can be effectively improved; finally, a synthesis network based on a series transmission line balun is adopted, the synthesis network can realize active load modulation optimization of the digital power amplifier, the impedance matching condition of the digital power amplifier under the maximum and partial rollback output power levels is improved and balanced, and the overall efficiency is improved.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

The invention discloses a low-voltage cascode NMOS (N-channel Metal Oxide Semiconductor) current mirror circuit which comprises a basic current mirror circuit, a biasing circuit and an operational amplifier feedback network, the basic current mirror circuit is used for forming a current mirror by adopting an NMOS (N-channel metal oxide semiconductor) transistor pair, and generating a corresponding output current IOUT after mirroring the received reference current IIN; the bias circuit is used for providing bias voltage for the basic current mirror circuit; the operational amplifier feedback network is used for forming a closed-loop feedback network of the basic current mirror circuit through the operational amplifier, so that the voltage of the input end of the basic current mirror circuit is equal to the voltage of the output end of the basic current mirror circuit. According to the invention, the operational amplifier is introduced to form a closed loop feedback network, so that the potentials of the input / output branches of the basic current mirror circuit are strictly matched, and the problem that the mirror image precision of a traditional structure is reduced due to drain electrode voltage mismatch is solved.

The invention discloses a monolithic integrated vertical GaN Cascode device structure and a preparation method thereof. The monolithic integrated vertical GaN Cascode device structure comprises a GaN MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a depletion type vertical GaN HEMT (High Electron Mobility Transistor) which are integrated on a Si-based substrate, wherein the drain electrode of the GaN MOSFET is connected with the source electrode of the GaN HEMT, the grid electrode of the GaN MOSFET serves as the grid electrode of the vertical GaN Cascode device structure, the source electrode of the GaN MOSFET is connected with the grid electrode of the GaN HEMT and then serves as the source electrode of the vertical GaN Cascode device structure, and the drain electrode of the GaN HEMT serves as the drain electrode of the vertical GaN Cascode device structure. The invention can solve the problems that the traditional cascade Cascode device is large in size, complex in packaging, large in parasitic parameter, low in mobility and limited by the material performance of the Si tube.

The invention provides an operational amplifier. The operational amplifier comprises a bias module, a chopping module, an enhanced recovery folded cascode module and an output stage module, the enhanced recovery folded cascode module comprises a first input tube group, a second input tube group and a regulation resistor, grid electrodes of the first input tube group and the second input tube group are connected with the output end of the chopping module, a source electrode of the first input tube group is connected to one end of the regulation resistor, a source electrode of the second input tube group is connected to the other end of the regulation resistor, and a source electrode of the second input tube group is connected to the other end of the regulation resistor. The first input tube group and the second input tube group generate different gate-source voltages; the three-path current recovery structure comprises at least two folded node transistors, two circulating current mirror transistors and two shunt transistors, the ratio of the width-to-length ratios of the folded node transistors, the circulating current mirror transistors and the shunt transistors is (1 + x): z (1-x): y (1-x), the value of x is larger than 0 and smaller than 1, and y + z = 1; and the grid electrodes of the matching transistors are connected to the bias voltage provided by the bias module.

A cascode solid-state switch device includes a normally-off transistor and a normally-on transistor having a source electrically connected to a drain of the normally-off transistor. A gate charge of the cascode solid-state switch device is independent of both a voltage class of the cascode solid-state switch device and a drain-to-source on-state resistance of the cascode solid-state switch device. A circuit component of the cascode solid-state switch device and a power electronics circuit that includes the cascode solid-state switch device are also described.

A double-channel semiconductor device is presented herein. The double-channel semiconductor device is a cascode solution integrating two semiconductor channels: a HEMT channel (104) and a thin film transistor (TFT) channel (216). The HEMT channel can be an AIGaN / GaN HEMT channel and the TFT channel can be a polycrystalline silicon (polysilicon) TFT channel. The polysilicon TFT may advantageously operate in enhancement mode to realize an enhancement-mode cascode device.

A GaN / SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.

The application discloses a common-source common-gate type HEMT power device and a preparation method and a chip thereof. The buffer layer, the drift layer and the barrier layer are formed in a laminated mode on a semiconductor substrate, the barrier layer and the drift layer are isolated into multiple functional areas by a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer, the first source metal layer, the first drain metal layer, the first gate metal layer and the gate dielectric layer are formed in one of the functional areas, the second drain metal layer, the second source metal layer, the second Schottky metal layer and the cap layer are formed in another of the functional areas, and the cathode metal layer and the first Schottky metal layer are formed in a third of the functional areas. The integrated common-source common-gate type HEMT power device is formed by selectively connecting the metal layers, the parasitic capacitance and the parasitic inductance can be effectively reduced, the switching frequency of the device is improved, and the application scenarios of the HEMT power device are greatly expanded.

The invention discloses a continuous time current comparator capable of outputting maximum current and minimum current. The continuous time current comparator comprises eight groups of cascode current mirrors consisting of NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N20 and PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N5 and the drain electrode of the NMOS tube N7 at the same time, the drain electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N11 and the drain electrode of the NMOS tube N13 at the same time, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N17; a to-be-compared current Ia is input from the drain electrode of the NMOS transistor N1, and a to-be-compared current Ib is input and then is divided into two paths which respectively flow to the drain electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N9; the drain electrode of the NMOS tube N19 outputs the maximum current Imax, and the drain electrode of the NMOS tube N15 outputs the minimum current Imin. After currents Ia and Ib to be compared are input, the maximum current Imax and the minimum current Imin corresponding to the currents Ia and Ib are output through current copying, summation and difference operation of the cascode current mirror, and the maximum current Imax and the minimum current Imin are both continuous analog current signals.

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

A current-integrating summing circuit is provided, and may include a first capacitor and a second capacitor to integrate an input current over time, a first pair of transistors to receive a differential pair of input signals, a second pair of transistors to receive a common-mode voltage, a third pair of transistors and a fourth pair of transistors respectively configured in a cascode formation relative to the first pair of transistors and the second pair of transistors, and a pair of complementary clocks to activate the third pair of transistors to enable charging of the first and second capacitors according to the differential pair of input signals during an integration phase, wherein the pair of complementary clocks are to activate the fourth pair of transistors to enable discharging of the first and second capacitors during a reset phase.

This invention provides a common-source common-gate field-effect transistor (CFET) and a semiconductor chip with a shielded gate, comprising multiple parallel-connected transistor structure groups, each including a first transistor structure and a second transistor structure. A first stacked structure is connected to the upper end of a first drain, and both a first oxide layer and a second stacked structure are connected to the upper end of the first stacked structure. A first shielded gate is connected inside the first oxide layer and is connected to the first source. A first gate is connected to the upper end of the first oxide layer, and the first source is connected to the first oxide layer and the second stacked structure. A third stacked structure is connected to the upper end of a second drain, and the second oxide layer and a fourth stacked structure are connected to the upper end of the third stacked structure. A second shielded gate is connected to the interior of the second oxide layer and is connected to the second gate. The second gate is connected to the upper end of the second oxide layer, and the second source is connected to the second oxide layer and the fourth stacked structure.

The application provides a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a dynamic working closed-loop cascode FIA as a residual amplifier to reduce power consumption by eliminating the static current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through the nested second-order CIFF and second-order EF noise shaping loops to achieve high precision in noise shaping at the same oversampling rate, and integrates the sampling noise cancellation (SNC) method to reduce the capacitance of the sampling capacitor to save chip area; the architecture adopts a closed-loop cascode FIA as a residual amplifier and CIFF and EF as noise shaping loops to solve the problem that the traditional noise shaping SAR ADC is difficult to simultaneously achieve high precision and low power consumption. In addition, the sampling KT / C noise cancellation (SNC) technology is integrated to reduce the capacitance of the sampling capacitor and save chip area.

The application provides a common-source common-gate amplifier, comprising a signal input module, which is used for generating an input signal according to a power supply voltage; a cross-coupling module, which is electrically connected with the signal input module and is used for forming internal positive feedback according to an output signal; a first biasing module, which is electrically connected with the cross-coupling module; a first branch module, which is electrically connected with the first biasing module; a second biasing module, which is electrically connected with the cross-coupling module; a second branch module, which is electrically connected with the second biasing module; wherein the first biasing module and the second biasing module are used for providing biasing after an input common-mode feedback voltage, the first branch module and the second branch module are used for providing large-swing output biasing, and the first branch module and the second branch module are respectively electrically connected with the signal input module, and the signal input module is further used for outputting branch signals to the first branch module and the second branch module. The application improves the voltage swing, the gain and the bandwidth of the circuit under the single-stage amplifier structure.

Disclosed in the present invention is a floating inverter amplifier based on capacitor stacking, which boosts a power supply of the floating inverter amplifier to 2 times VDD by means of the capacitor stacking; under such condition, a transistor in the inverter may be better turned on, and a cascode structure can be applied to an inverting amplifier operating at a low power supply voltage. Furthermore, an ADC system employing the floating inverter amplifier of the present invention can process an input signal with a common-mode voltage of VDD and an amplitude up to 2 times VDD, which effectively addresses a problem of a reduced input signal amplitude under an ultra-low voltage, thereby increasing a signal-to-noise ratio of the system.

The invention discloses a monolithic integrated PGaN gate-controlled Cascode structure GaN IGBT, and relates to the technical field of semiconductor devices, a third P-GaN layer on the surface is used as a gate region of an E-mode device, and a trench formed by etching a second P-GaN layer, a barrier layer, a channel layer and a part of a drift layer is used as a gate region of a D-mode device. And etching a trench which is in contact with the second P-GaN layer and the two-dimensional electron gas at the same time to serve as an emitter region of the IGBT, and etching a deep trench at the bottom of the substrate to the first P-GaN layer to serve as a collector region of the IGBT. By moving the grid electrode to the surface, the grid electrode and the collector electrode are prevented from being oppositely placed, and reverse transfer capacitance is greatly reduced.

The invention belongs to the technical field of semiconductors, and particularly discloses a depletion type GaN device and an HEMT cascade type device.The depletion type GaN device comprises a source electrode, a drain electrode, a gate electrode, a substrate, a laminated structure and a dielectric layer, the substrate, the laminated structure and the dielectric layer are sequentially arranged from bottom to top, and the top of the gate electrode is provided with a first functional area and a second functional area which are arranged in a staggered mode in the circumferential direction of the gate electrode; the absolute value of the threshold voltage of each first functional area is larger than that of the threshold voltage of each second functional area, the threshold voltage of each first functional area is smaller than 0, and the orthographic projection of the whole of all the first functional areas and the second functional areas located at the top of the gate electrode on the gate electrode coincides with the gate electrode. According to the depletion type GaN device, transconductance can be optimized, the matching problem of the switching speed between the depletion type GaN device and the low-voltage MOS device in a cascade type device can be improved, the problems of oscillation, electromagnetic interference and tube explosion are not prone to occurring, and the efficiency and the reliability of the device are effectively improved.

The application belongs to the technical field of radio frequency amplifiers, and specifically discloses a CMOS common-source common-gate radio frequency amplifier with temperature and process deviation compensation, which comprises a bias circuit and an amplification stage circuit; the bias circuit adopts a temperature and process deviation compensation bias circuit; when the ambient temperature changes, the bias circuit can collect the real-time temperature of an amplifying tube and generate a new bias voltage, so that the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the temperature change is reduced; similarly, when the process parameter distribution deviation occurs in different regions of a wafer during the chip manufacturing process, the same chip bias circuit and the amplifying tube region of the amplification stage circuit are the same, the same process deviation is generated, the bias circuit can generate a new bias voltage according to the process deviation, the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the process deviation is reduced. The application is suitable for a low-noise amplifier in a WiFi radio frequency front-end module.

The invention discloses a self-adaptive gain and bandwidth operational amplifier circuit, which comprises a biasing circuit, a folded cascode operational amplifier and a source follower, and is characterized in that the folded cascode operational amplifier comprises PMOS (P-channel Metal Oxide Semiconductor) tubes forming a cascode structure and NMOS (N-channel Metal Oxide Semiconductor) tubes forming a cascode structure; the input end of the bias circuit is used for accessing a control signal, and the output end of the bias circuit is used for outputting a first bias voltage and a second bias voltage; the first bias voltage and the second bias voltage are grid voltages provided for a PMOS tube and an NMOS tube which form a cascode structure respectively, the control signal is used for controlling the first bias voltage and the second bias voltage, and the gain and the bandwidth of the operational amplifier circuit change along with the change of the first bias voltage and the second bias voltage. According to the invention, the gain and bandwidth of the operational amplifier circuit can be adaptively adjusted according to the use scene, and the circuit design is simplified, so that the complexity and cost of the circuit are reduced, and the flexibility of the circuit is improved.

A transmitter employs simple inverters to predrive cascode-connected pull-up and pull-down output stages. Each output stage includes a drive transistor with a thin gate dielectric for fast switching. The drive transistor is cascode connected to a set of parallel-connected transistors. Calibration circuitry selectively enables the parallel-connected transistors to calibrate output resistance. The parallel transistors converge at a single resistor.

The invention discloses a system and equipment for inhibiting voltage and current mismatching of series-parallel field-effect transistors, and belongs to the technical field of power electronics, the system comprises a gate driving module and a gate driving module, the gate driving module is electrically connected with a parallel field-effect transistor module, and the gate driving module is electrically connected with a series field-effect transistor module; wherein the gate driving module is used for acquiring a gate control signal, forming a charging and discharging path based on the gate control signal, and acquiring a driving delay signal based on the charging and discharging path so as to realize current balance matching of the parallel field effect transistor module based on the driving delay signal; and the gate driving module is used for executing an equalization voltage adjusting action. According to the system and the device for suppressing voltage and current mismatching of the series-parallel field-effect tubes, the problem of unbalanced voltage and current distribution of the series-parallel field-effect tubes in the prior art can be solved, and parallel current-sharing control and series active voltage-sharing control are realized.

The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

This application is directed to techniques for performing sensing operations. In some examples, a memory device can include a pair of transistors to pre-charge a digit line. A first transistor of the pair of transistors can be coupled with a first node, and a second transistor of the pair of transistors can be coupled with a second node. In some cases, the first node and the second node can be selectively coupled via a transistor. The first transistor and the second transistor can be activated to pre-charge the first node and the second node. In some examples, a pulse can be applied to a capacitor coupled with the second node to transfer charge to the digit line. In some cases, a common-source common-gate transistor can maintain or control a voltage of the digit line to be at or below an upper operating voltage of the memory cell.

The present disclosure relates to a cascode power switch that can be used in DC-DC converter applications. A cascode power switch includes a high side (HS) switch coupled between an output node configured to provide an output voltage and a first voltage supply terminal configured to provide a first voltage supply; and a low side (LS) switch coupled between the output node and a second voltage supply terminal configured to provide a second voltage supply. The LS switch includes a first transistor coupled between the intermediate node and a second voltage supply terminal, and a second transistor coupled between the intermediate node and the output node. The LS driver has a voltage monitoring circuit configured to receive a first control signal that opens the HS switch when negated. The voltage monitoring circuit includes a logic circuit having a first input configured to receive a first control signal and a second input coupled to the intermediate node, and an output coupled to the control electrode of the first transistor.

The invention belongs to the technical field of integrated circuits, and particularly relates to a millimeter wave broadband low-noise amplifier. The millimeter wave broadband low-noise amplifier comprises a broadband input matching network, a first-stage cascode amplification stage, a first-stage inter-stage matching network based on three-coil coupling, a second-stage differential cascode amplification stage, a second-stage inter-stage matching network based on an asymmetric resonant cavity, a third-stage differential cascode amplification stage and a broadband output matching network. The broadband input matching network comprises a source electrode degeneration inductor and a series-parallel capacitor inductor network, and good conjugate matching and noise matching can be achieved at the same time within the broadband range. According to the invention, a three-coil coupling architecture and an asymmetric resonant cavity architecture are respectively adopted in the design of an inter-stage matching network, and higher gain and lower gain ripple and noise coefficient are realized in a broadband range.