510 results about "Cascode" patented technology

The invention discloses a C / X wave band ultra-wideband GaAs MMIC low-noise amplifier, and mainly relates to the technical field of radio frequency front ends. Comprising an input matching network used for receiving a radio frequency signal and performing impedance matching so as to effectively transmit the signal to a subsequent active amplification part; and the active amplification part adopts an improved cascode-cascode cascade amplification structure and is used for amplifying the radio frequency signal transmitted by the input matching network. The amplifier has the advantages that an improved cascode-cascode cascade amplification structure is adopted, the gain is improved through an improved Cascode structure, the noise coefficient of the circuit is reduced, and the performance indexes of ultra wide band, low noise and high gain are achieved. The design of the structure not only improves the overall performance of the amplifier, but also enables the amplifier to keep stable gain output in a broadband range, and effectively solves the problems of low gain and high noise of a traditional low-noise amplifier in broadband application.

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

Disclosed herein is a single photon avalanche diode (SPAD) pixel circuit, including a SPAD having an anode coupled to a negative voltage and a cathode and a cascode transistor having a drain coupled to the cathode of the SPAD, a gate controlled by a cascode control signal, and a source. A readout circuit is coupled to the source of the cascode transistor and configured to detect a voltage change at the source of the cascode transistor and generate a pulse indicating an occurrence of an avalanche event. An active quenching circuit is coupled to the cathode of the SPAD and configured to detect an onset of the avalanche event and pull the cathode of the SPAD to a negative voltage to quench the avalanche event.

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

A bandgap reference circuit includes a first, a second and a third current source, a first and a second amplifier. The first, the second and the third current source each includes two cascode PMOS transistors for reducing the voltage stress applied to PMOS transistors when receives a high power supply voltage. The first amplifier controls the PMOS transistors in the first and the second current source to ensure that the PMOS transistors have enough headroom when receives a low power supply voltage. The second amplifier provides a gain-boosting loop to prevent the system mismatch of the PMOS transistors in the first, the second and the third current source. A temperature coefficient adjustment unit introduces positive temperature coefficients and negative temperature coefficients in the currents generated by the first and second current source, and a resistor generates the reference voltage according to a current duplicated by the third current source.

A cascode switch device includes a normally-on switch device, a normally-off switch device, and a gate driver. The normally-on switch device has a first terminal, a second terminal and a control terminal. The normally-off switch device has a first terminal, a second terminal and a control terminal. The first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device. The gate driver is configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device. The normally-on switch device is turned on or turned off in response to the gate driver signal.

The embodiment of the utility model discloses a cascode cascade device which is applied to the technical field of semiconductor manufacturing. In a cascode cascade device, a source electrode and a grid electrode of a low-voltage enhanced field effect transistor are respectively used as a source electrode end and a grid electrode end of the cascade device, and a drain electrode of a high-voltage enhanced field effect transistor is used as a drain electrode end of the cascade device, so that a balancing circuit and an adjusting circuit can be integrated on the low-voltage enhanced field effect transistor; and the balancing circuit and the adjusting circuit only relate to the resistor and the diode, and when the resistor and the diode are integrated on the low-voltage enhanced field effect transistor, only one mask needs to be added, so that the process cost is relatively low. And redundant devices do not need to be integrated on the high-voltage field-effect tube in the cascade device, so that the area of the high-voltage field-effect tube is saved, and the overall cost of the cascade device is relatively low.

The invention discloses a gain boosting type floating anti-phase dynamic amplifier circuit, and relates to the technical field of integrated circuits, the gain boosting type floating anti-phase dynamic amplifier circuit comprises a power supply, a main amplifier, a first auxiliary amplifier and a second auxiliary amplifier, and the main amplifier and the auxiliary amplifiers both adopt a cascode floating anti-phase dynamic amplifier structure; the main amplifier comprises a first power supply capacitor, a second power supply capacitor, a plurality of first common-source transistors and a plurality of first common-gate transistors; a plurality of drain electrodes of the plurality of first common-source transistors are respectively connected with the input ends of the first auxiliary amplifier and the second auxiliary amplifier, and a plurality of grid electrodes of the first common-gate transistors are respectively connected with the output ends of the first auxiliary amplifier and the second auxiliary amplifier; the first auxiliary amplifier and the second auxiliary amplifier each comprise a plurality of second common-gate transistors, and a plurality of gates of the second common-gate transistors are directly connected to the common-mode level. According to the amplifier circuit, the gain of the amplifier is improved on the premise that the speed and the stability are guaranteed.

The invention provides a low-noise amplifier and a radio frequency front-end module, and the low-noise amplifier comprises an input matching circuit, a first-stage power amplification circuit, an inter-stage matching circuit, a second-stage power amplification circuit and an output matching circuit. The inter-stage matching circuit comprises a first inductor, a second inductor and a first capacitor; the second-stage power amplification circuit is of a cascode structure; and the output matching circuit comprises a third inductor and a fourth inductor which are coupled with each other. According to the low-noise amplifier, the high-frequency gain, the in-band gain flatness, the isolation degree, the stability and the output matching bandwidth of the low-noise amplifier can be improved.

According to another disclosed embodiment, an energy efficient implantable neurostimulator for delivering one or more electrical pulses to a target region within a patient's body is provided. The neurostimulator includes a converter for generating the stimulation current, wherein the converter includes a voltage increasing circuit and a voltage reducing circuit. The stimulator may also include a current source that includes a pair of cascode arranged transistors that are controlled to maintain an amplitude of the stimulation current substantially constant. The neurostimulator may also include a bias voltage power supply that powers a selecting circuit for selecting one of the voltage increasing or voltage decreasing circuits.

A voltage regulator includes an input power supply node, an output regulated power supply node, a flipped voltage follower circuit, and a compensation capacitor. The flipped voltage follower circuit includes an output transistor configured as a common-source amplifier circuit. A source terminal of the output transistor is coupled to the input power supply node and a drain terminal of the output transistor is coupled to the output regulated power supply node. The flipped voltage follower circuit includes a folded cascode feedback circuit. The folded cascode feedback circuit includes a folding node. The folded cascode feedback circuit is configured to receive an output regulated voltage on the output regulated power supply node and to provide a feedback signal to a gate terminal of the output transistor. The compensation capacitor is coupled to the output regulated power supply node and the folding node.

Composite cascode power amplifiers for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a composite cascode power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The composite cascode power amplifier includes an enhancement mode (E-MODE) field-effect transistor (FET) for amplifying the RF signal and a depletion mode (D-MODE) FET in cascode with the E-MODE FET.

An electronic device may include wireless circuitry having a transformer with a primary coil and a secondary coil, a first series inductor coupled to the primary coil, a second series inductor coupled to the primary coil, and a filter inductor inductively coupled to the first and second series inductors and operable to produce a first filter response when the wireless circuitry is operable in a first mode and a second filter response when the wireless circuitry is operable in a second mode. The transformer can be coupled to another filter inductor. The transformer can be coupled to an active circuit. The active circuit can include input transistors and cascode transistors. The cascode transistors can be coupled to resistors and / or capacitors that are selectively activated using associated filter switches.

The invention provides a millimeter wave digital power amplifier based on a serial transmission line balun synthesis network, and belongs to the technical field of millimeter wave digital power amplifiers. According to the millimeter wave digital power amplifier, firstly, a driving power distribution network based on a bridge and a transformer is adopted, and radio frequency power is subjected to differential conversion and then input into a digital power amplifier unit array; secondly, the digital power amplifier unit adopts a differential Cascode structure with a neutralizing capacitor, so that the gain and the output impedance of the digital power amplifier unit can be effectively improved; finally, a synthesis network based on a series transmission line balun is adopted, the synthesis network can realize active load modulation optimization of the digital power amplifier, the impedance matching condition of the digital power amplifier under the maximum and partial rollback output power levels is improved and balanced, and the overall efficiency is improved.

The invention discloses a high-linearity medium-power amplifier based on cascode RC negative feedback and a composite matching network. The high-linearity medium-power amplifier comprises a common-source transistor M1, a common-gate transistor M2, a single power supply VDD with an active bias circuit, an input matching network, an output matching network and a negative feedback loop, the input matching network comprises an inductor Lb and an inductor Lg, the output skin matching network comprises an inductor Ld1 and an inductor Ld2, and the negative feedback loop comprises a resistor Rf and a capacitor Cf; the source electrode of the common source transistor M1 is connected with the drain electrode of the common gate transistor M2, one side of the active bias circuit is connected to the grid electrode of the common source transistor M1 through the inductor Lb and the inductor Lg in sequence, the common end of the inductor Lb and the inductor Lg is connected with the input end, and the resistor Rf and the capacitor Cf are connected in series and connected between the grid electrode of the common source transistor M1 and the output end. One side of the inductor Ld2 is connected with the source electrode of the common-gate transistor M2, the other side of the inductor Ld2 is connected with one side of the inductor Ld1, the other side of the inductor Ld1 is connected with the single power supply VDD, and the common end of the inductor Ld1 and the inductor Ld2 is connected with the capacitor Cf and the output end; the method is suitable for radar and communication systems in industrial application, and has important significance for developing high-performance, low-cost and high-integration-level multifunctional chips.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

The invention discloses a low-voltage cascode NMOS (N-channel Metal Oxide Semiconductor) current mirror circuit which comprises a basic current mirror circuit, a biasing circuit and an operational amplifier feedback network, the basic current mirror circuit is used for forming a current mirror by adopting an NMOS (N-channel metal oxide semiconductor) transistor pair, and generating a corresponding output current IOUT after mirroring the received reference current IIN; the bias circuit is used for providing bias voltage for the basic current mirror circuit; the operational amplifier feedback network is used for forming a closed-loop feedback network of the basic current mirror circuit through the operational amplifier, so that the voltage of the input end of the basic current mirror circuit is equal to the voltage of the output end of the basic current mirror circuit. According to the invention, the operational amplifier is introduced to form a closed loop feedback network, so that the potentials of the input / output branches of the basic current mirror circuit are strictly matched, and the problem that the mirror image precision of a traditional structure is reduced due to drain electrode voltage mismatch is solved.

The invention discloses a monolithic integrated vertical GaN Cascode device structure and a preparation method thereof. The monolithic integrated vertical GaN Cascode device structure comprises a GaN MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a depletion type vertical GaN HEMT (High Electron Mobility Transistor) which are integrated on a Si-based substrate, wherein the drain electrode of the GaN MOSFET is connected with the source electrode of the GaN HEMT, the grid electrode of the GaN MOSFET serves as the grid electrode of the vertical GaN Cascode device structure, the source electrode of the GaN MOSFET is connected with the grid electrode of the GaN HEMT and then serves as the source electrode of the vertical GaN Cascode device structure, and the drain electrode of the GaN HEMT serves as the drain electrode of the vertical GaN Cascode device structure. The invention can solve the problems that the traditional cascade Cascode device is large in size, complex in packaging, large in parasitic parameter, low in mobility and limited by the material performance of the Si tube.

The invention provides a high-gain wide-output ring amplifier and a pipelined SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-gain wide-output ring amplifier comprises a ring amplification module, a level shifting capacitor, a transmission gate switch module and a cascode module, the annular amplification module is used for acquiring a residual signal output by the adjacent SAR ADC module and performing amplification processing on the residual signal to obtain a residual amplification signal; the level shift capacitor is used for performing wide-swing processing on the residual amplification signal under the control of the transmission gate switch module to form a wide-output residual amplification signal; the cascode module adopts a cascode amplification circuit to improve the voltage gain of the annular amplification module; and a high-gain wide-output ring amplifier is arranged between every two SAR ADC modules in the assembly line SAR ADC. Therefore, the gain and the response speed of the assembly line SAR ADC are improved, and the power consumption and the signal delay accumulation are reduced at the same time.

The invention provides an operational amplifier. The operational amplifier comprises a bias module, a chopping module, an enhanced recovery folded cascode module and an output stage module, the enhanced recovery folded cascode module comprises a first input tube group, a second input tube group and a regulation resistor, grid electrodes of the first input tube group and the second input tube group are connected with the output end of the chopping module, a source electrode of the first input tube group is connected to one end of the regulation resistor, a source electrode of the second input tube group is connected to the other end of the regulation resistor, and a source electrode of the second input tube group is connected to the other end of the regulation resistor. The first input tube group and the second input tube group generate different gate-source voltages; the three-path current recovery structure comprises at least two folded node transistors, two circulating current mirror transistors and two shunt transistors, the ratio of the width-to-length ratios of the folded node transistors, the circulating current mirror transistors and the shunt transistors is (1 + x): z (1-x): y (1-x), the value of x is larger than 0 and smaller than 1, and y + z = 1; and the grid electrodes of the matching transistors are connected to the bias voltage provided by the bias module.

Described herein is an operational transconductance amplifier (OTA) with a constant current source that provides a constant current to a node. The OTA includes two input pairs of transistors: the first sources variable currents based on feedback and input voltages, while the second sinks variable currents also based on feedback and input voltages. A folded cascode arrangement includes two branches, with one branch including a Monticelli cell. A class-AB output stage is present, with its inputs connected across the Monticelli cell. Additionally, a bias stage mirrors and scales the constant current to generate control voltages. Within the folded cascode branches, compensation transistors are controlled by these control voltages, ensuring that various sourced and sunk variable currents are of equal magnitude, making the OTA input voltage independent.

A cascode solid-state switch device includes a normally-off transistor and a normally-on transistor having a source electrically connected to a drain of the normally-off transistor. A gate charge of the cascode solid-state switch device is independent of both a voltage class of the cascode solid-state switch device and a drain-to-source on-state resistance of the cascode solid-state switch device. A circuit component of the cascode solid-state switch device and a power electronics circuit that includes the cascode solid-state switch device are also described.

A double-channel semiconductor device is presented herein. The double-channel semiconductor device is a cascode solution integrating two semiconductor channels: a HEMT channel (104) and a thin film transistor (TFT) channel (216). The HEMT channel can be an AIGaN / GaN HEMT channel and the TFT channel can be a polycrystalline silicon (polysilicon) TFT channel. The polysilicon TFT may advantageously operate in enhancement mode to realize an enhancement-mode cascode device.

The invention relates to a method for enhancing controllability of switching speed of an electronic cascode power device, the electronic cascode power device comprising a high-voltage normally-on transistor and a low-voltage normally-off transistor, the high-voltage normally-on transistor is provided with a drain electrode connected to a high-side terminal of the cascode power device and a grid electrode connected to a low-side terminal of the cascode power device; a low-voltage normally-off transistor having a drain connected to a source of the high-voltage normally-on transistor, a source connected to the low-side terminal of the cascode power device, and a gate connected to a control terminal of the cascode power device; the method includes introducing a coupling capacitor into the electronic cascode power device by: connecting a first terminal of the coupling capacitor to the source of the high voltage normally on type transistor; and connecting a second terminal of the coupling capacitor to the gate of the low voltage normally off type transistor.

A GaN / SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.

The application discloses a common-source common-gate type HEMT power device and a preparation method and a chip thereof. The buffer layer, the drift layer and the barrier layer are formed in a laminated mode on a semiconductor substrate, the barrier layer and the drift layer are isolated into multiple functional areas by a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer, the first source metal layer, the first drain metal layer, the first gate metal layer and the gate dielectric layer are formed in one of the functional areas, the second drain metal layer, the second source metal layer, the second Schottky metal layer and the cap layer are formed in another of the functional areas, and the cathode metal layer and the first Schottky metal layer are formed in a third of the functional areas. The integrated common-source common-gate type HEMT power device is formed by selectively connecting the metal layers, the parasitic capacitance and the parasitic inductance can be effectively reduced, the switching frequency of the device is improved, and the application scenarios of the HEMT power device are greatly expanded.

To provide a composite cascode power amplifier for an envelope tracking application.SOLUTION: In an envelope tracking system, a composite cascode power amplifier 250 that amplifies a radio frequency (RF) signal includes a composite cascode power amplifier that receives power from a power amplifier supply voltage VPA and an envelope tracker that generates a power amplifier supply voltage based on an envelope of a RF signal RFIN. The composite cascode power amplifier includes an enhancement-mode (E-mode) field-effect transistor (FET) 241 for amplifying the RF signal, and a depletion-mode (D-mode) FET242 to be cascoded to the E-mode FET.SELECTED DRAWING: Figure 3

The invention discloses a continuous time current comparator capable of outputting maximum current and minimum current. The continuous time current comparator comprises eight groups of cascode current mirrors consisting of NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N20 and PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N5 and the drain electrode of the NMOS tube N7 at the same time, the drain electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N11 and the drain electrode of the NMOS tube N13 at the same time, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N17; a to-be-compared current Ia is input from the drain electrode of the NMOS transistor N1, and a to-be-compared current Ib is input and then is divided into two paths which respectively flow to the drain electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N9; the drain electrode of the NMOS tube N19 outputs the maximum current Imax, and the drain electrode of the NMOS tube N15 outputs the minimum current Imin. After currents Ia and Ib to be compared are input, the maximum current Imax and the minimum current Imin corresponding to the currents Ia and Ib are output through current copying, summation and difference operation of the cascode current mirror, and the maximum current Imax and the minimum current Imin are both continuous analog current signals.

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.