194 results about "Cascode" patented technology

The invention provides a low-noise amplifier and a radio frequency front-end module, and the low-noise amplifier comprises an input matching circuit, a first-stage power amplification circuit, an inter-stage matching circuit, a second-stage power amplification circuit and an output matching circuit. The inter-stage matching circuit comprises a first inductor, a second inductor and a first capacitor; the second-stage power amplification circuit is of a cascode structure; and the output matching circuit comprises a third inductor and a fourth inductor which are coupled with each other. According to the low-noise amplifier, the high-frequency gain, the in-band gain flatness, the isolation degree, the stability and the output matching bandwidth of the low-noise amplifier can be improved.

A GaN / SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.

The invention discloses a continuous time current comparator capable of outputting maximum current and minimum current. The continuous time current comparator comprises eight groups of cascode current mirrors consisting of NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N20 and PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N5 and the drain electrode of the NMOS tube N7 at the same time, the drain electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N11 and the drain electrode of the NMOS tube N13 at the same time, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N17; a to-be-compared current Ia is input from the drain electrode of the NMOS transistor N1, and a to-be-compared current Ib is input and then is divided into two paths which respectively flow to the drain electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N9; the drain electrode of the NMOS tube N19 outputs the maximum current Imax, and the drain electrode of the NMOS tube N15 outputs the minimum current Imin. After currents Ia and Ib to be compared are input, the maximum current Imax and the minimum current Imin corresponding to the currents Ia and Ib are output through current copying, summation and difference operation of the cascode current mirror, and the maximum current Imax and the minimum current Imin are both continuous analog current signals.

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

This invention provides a common-source common-gate field-effect transistor (CFET) and a semiconductor chip with a shielded gate, comprising multiple parallel-connected transistor structure groups, each including a first transistor structure and a second transistor structure. A first stacked structure is connected to the upper end of a first drain, and both a first oxide layer and a second stacked structure are connected to the upper end of the first stacked structure. A first shielded gate is connected inside the first oxide layer and is connected to the first source. A first gate is connected to the upper end of the first oxide layer, and the first source is connected to the first oxide layer and the second stacked structure. A third stacked structure is connected to the upper end of a second drain, and the second oxide layer and a fourth stacked structure are connected to the upper end of the third stacked structure. A second shielded gate is connected to the interior of the second oxide layer and is connected to the second gate. The second gate is connected to the upper end of the second oxide layer, and the second source is connected to the second oxide layer and the fourth stacked structure.

The application provides a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a dynamic working closed-loop cascode FIA as a residual amplifier to reduce power consumption by eliminating the static current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through the nested second-order CIFF and second-order EF noise shaping loops to achieve high precision in noise shaping at the same oversampling rate, and integrates the sampling noise cancellation (SNC) method to reduce the capacitance of the sampling capacitor to save chip area; the architecture adopts a closed-loop cascode FIA as a residual amplifier and CIFF and EF as noise shaping loops to solve the problem that the traditional noise shaping SAR ADC is difficult to simultaneously achieve high precision and low power consumption. In addition, the sampling KT / C noise cancellation (SNC) technology is integrated to reduce the capacitance of the sampling capacitor and save chip area.

The application provides a common-source common-gate amplifier, comprising a signal input module, which is used for generating an input signal according to a power supply voltage; a cross-coupling module, which is electrically connected with the signal input module and is used for forming internal positive feedback according to an output signal; a first biasing module, which is electrically connected with the cross-coupling module; a first branch module, which is electrically connected with the first biasing module; a second biasing module, which is electrically connected with the cross-coupling module; a second branch module, which is electrically connected with the second biasing module; wherein the first biasing module and the second biasing module are used for providing biasing after an input common-mode feedback voltage, the first branch module and the second branch module are used for providing large-swing output biasing, and the first branch module and the second branch module are respectively electrically connected with the signal input module, and the signal input module is further used for outputting branch signals to the first branch module and the second branch module. The application improves the voltage swing, the gain and the bandwidth of the circuit under the single-stage amplifier structure.

Disclosed in the present invention is a floating inverter amplifier based on capacitor stacking, which boosts a power supply of the floating inverter amplifier to 2 times VDD by means of the capacitor stacking; under such condition, a transistor in the inverter may be better turned on, and a cascode structure can be applied to an inverting amplifier operating at a low power supply voltage. Furthermore, an ADC system employing the floating inverter amplifier of the present invention can process an input signal with a common-mode voltage of VDD and an amplitude up to 2 times VDD, which effectively addresses a problem of a reduced input signal amplitude under an ultra-low voltage, thereby increasing a signal-to-noise ratio of the system.

The application belongs to the technical field of radio frequency amplifiers, and specifically discloses a CMOS common-source common-gate radio frequency amplifier with temperature and process deviation compensation, which comprises a bias circuit and an amplification stage circuit; the bias circuit adopts a temperature and process deviation compensation bias circuit; when the ambient temperature changes, the bias circuit can collect the real-time temperature of an amplifying tube and generate a new bias voltage, so that the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the temperature change is reduced; similarly, when the process parameter distribution deviation occurs in different regions of a wafer during the chip manufacturing process, the same chip bias circuit and the amplifying tube region of the amplification stage circuit are the same, the same process deviation is generated, the bias circuit can generate a new bias voltage according to the process deviation, the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the process deviation is reduced. The application is suitable for a low-noise amplifier in a WiFi radio frequency front-end module.

The invention discloses a system and equipment for inhibiting voltage and current mismatching of series-parallel field-effect transistors, and belongs to the technical field of power electronics, the system comprises a gate driving module and a gate driving module, the gate driving module is electrically connected with a parallel field-effect transistor module, and the gate driving module is electrically connected with a series field-effect transistor module; wherein the gate driving module is used for acquiring a gate control signal, forming a charging and discharging path based on the gate control signal, and acquiring a driving delay signal based on the charging and discharging path so as to realize current balance matching of the parallel field effect transistor module based on the driving delay signal; and the gate driving module is used for executing an equalization voltage adjusting action. According to the system and the device for suppressing voltage and current mismatching of the series-parallel field-effect tubes, the problem of unbalanced voltage and current distribution of the series-parallel field-effect tubes in the prior art can be solved, and parallel current-sharing control and series active voltage-sharing control are realized.

The example cascode voltage regulator circuit (300) has an input voltage terminal (V IN A first transistor (302) is coupled to the source terminal and configured as a source follower to provide an output voltage at the source terminal, and the source terminal and output terminal (V) of the first transistor (302) are connected. OUT The system includes a second transistor (310) coupled in series with the first transistor (302) and configured as a current limiter, and current mirrors (322 and 324) coupled between the first and second control terminals of the first and second transistors (302 and 310), respectively, which receive a first current indicating a source follower current flowing through the first transistor (302), and are configured to turn off the second transistor (310) by coupling the first and second control terminals together in response to the source follower current exceeding a certain threshold.

This invention discloses a vector modulation active phase shifter, comprising a coupling network (100) for generating quadrature signals, a first active amplitude control module (200) and a second active amplitude control module (300) composed of a common-source cascode transistor array for adjusting the gain of in-phase and quadrature signals, and a power combining and output matching network (400). The vector modulation active phase shifter includes a phase compensation network (500) located between the coupling network for generating quadrature signals and the active amplitude control module, used to optimize the phase bandwidth of the quadrature signals and improve phase shift accuracy. This invention realizes a wideband, high-precision, directly digitally controlled vector combining active phase shifter with a 360° phase shift range.

This application relates to the field of radio frequency communication technology, providing a low-noise amplifier and a radio frequency front-end module. The low-noise amplifier includes: a signal input terminal and a signal output terminal; a common-source cascode (CRBC) amplifier module connected to the signal input terminal for signal amplification; a switching module connected to both the CRBC amplifier module and the signal output terminal; and a gain module connected to the switching module for increasing the signal amplification gain. The switching module controls the on / off switching between the gain module and the CRBC amplifier module. By controlling the on / off switching between the gain module and the CRBC amplifier module through the switching module, the low-noise amplifier can flexibly switch between a high-gain operating mode and a high-linearity operating mode. This allows for selection of high-gain or high-linearity signal amplification processing according to the application scenario, enabling the low-noise amplifier to meet the requirements of both high-gain and high-linearity scenarios.

Including storage device: a memory arrangement (200) containing several memory cells (210) arranged in rows and columns; a control loop bias generator (400) configured to output a voltage signal to a column decoder (450) configured to output a column selection signal to the memory arrangement (200); a current limiter (300) configured to receive an output signal (VG) from the control loop bias generator (400), wherein the current limiter (300) is coupled to several columns of the memory arrangement (200), wherein the current limiter (300) comprises a cascode of a first NMOS transistor (M4) and a second coupled NMOS transistor (M2), wherein the bias generator (400) comprises a third cascode-connected NMOS transistor (M3) and a fourth cascode-connected NMOS transistor (M1) and an operational amplifier (402) configured to receive a feedback signal, where a source of the third NMOS transistor (M3) is connected to a gate of the second NMOS transistor (M2).

This invention discloses a method for predicting gate switch oscillation in GaN-HEMT devices, belonging to the field of semiconductors and power devices. The invention trains a BPNN network model to obtain a preliminary mapping relationship between parasitic capacitance and gate-source voltage based on the BPNN algorithm model. Then, a Cascode-based two-port network function for GaN HEMT is established. The parasitic capacitance value of the GaN HEMT device under all S-parameters is obtained experimentally. This extracted parasitic capacitance value is then input into the BPNN network model as a dataset to obtain Vo. GS_m V under all S parameters DS C GS C GD The relationship between the surface and the curve is shown. Simulation results show that the standard error of the prediction method of the present invention is smaller than that of ANN and PSO, proving that the detection method for GaN-HEMT gate switch oscillation based on the BPNN algorithm model of the present invention has high prediction accuracy.

Disclosed in the present invention is an input stage circuit. The input stage circuit is used for providing a differential current to a post-stage circuit on the basis of a differential input signal. The input stage circuit comprises: a first input transistor pair, and a first cascode structure and a first tail current source which are adaptively connected to the first input transistor pair; and a second input transistor pair, and a second cascode structure and a second tail current source adaptively connected to the second input transistor pair, wherein a first bias voltage is provided to the second cascode structure by means of a common node of the first input transistor pair and the first tail current source, and a second bias voltage is provided to the second cascode structure by means of a common node of the second input transistor pair and the second tail current source. Therefore, self-biasing can be achieved, thereby reducing power consumption and improving the response speed.

The application belongs to the technical field of amplifiers, and relates to a cyclic structure amplifier, in particular to a high-gain transconductance-enhanced cyclic structure amplifier. The cyclic structure amplifier comprises PMOS tubes P1a, P1b, P2a, P2b, P5, P6, P7, P8 and P9, and NMOS tubes N1, N2, N3, N4, N5a, N5b, N6a, N6b, N7a, N7b, N8a and N8b. The drain of the PMOS tube P1b is connected to the gate of the NMOS tube N5b. The drain of the PMOS tube P2b is connected to the gate of the NMOS tube N6b. The NMOS tube N5b and the PMOS tube P1b and the NMOS tube N6b and the PMOS tube P2b form a cross positive feedback path, which can enhance the transconductance of the PMOS tubes P1b and P2b. The high-gain transconductance-enhanced cyclic structure amplifier provided by the application has a transconductance five times that of a conventional folded cascode operational amplifier and a nine-time higher slew rate than that of the folded cascode operational amplifier.

A CMOS sensor pixel (10) comprises a photosensitive element (100), a reset transistor (105) and a source follower (110). A terminal of the photosensitive element (100), a gate terminal (111) of the source follower (110) and a terminal of the reset transistor (105) are electrically coupled to a node (102). The CMOS sensor pixel (10) further comprises a cascode transistor (114) arranged between the photosensitive element (100) and the node (102), and a biasing circuit (118) configured to change a gate voltage to be applied to a gate terminal (115) of the cascode transistor (114) during an activation time of the CMOS sensor pixel (10).

The invention discloses a Ka-band broadband low-noise amplifier based on a mixed feedback mode and a design method and device thereof. The Ka-band broadband low-noise amplifier comprises an input matching network, a single-section microstrip line coupling feedback network, an inter-stage matching network, a resistance negative feedback network, a three-section microstrip line coupling feedback network and an output matching network. And an active bias network is assisted to ensure the working stability. The circuit is composed of two stages of circuits, the preceding stage circuit adopts a cascode transistor amplifier to minimize noise, and the backward stage circuit adopts a cascode structure to improve linearity and bandwidth. Simulation results show that in the frequency band of 25-40 GHz, the amplifier achieves the excellent performance that the gain is higher than 20 dB, the flatness is 0.6 dB, the noise coefficient is 1.43-1.75 dB, the output 1dB compression point is larger than 5.5 dBm, and the direct-current power consumption is only 40.6 mW. According to the low-noise amplifier, the problems of gain roll-off, high noise, limited bandwidth and the like of a traditional low-noise amplifier in broadband application are solved by innovatively combining a resistance negative feedback technology and a microstrip line coupling feedback technology.

The application discloses a high linearity low noise amplifier based on a post-distortion technology, which comprises a common source and common gate structure circuit, an input matching circuit, an output matching circuit, an auxiliary amplification circuit and a neutralizing inductor; the common source and common gate structure circuit comprises a first common source tube and a second common gate tube; the auxiliary amplification circuit comprises a first common gate tube; the gate and the source of the first common source tube are connected with the input matching circuit; the drain of the first common source tube is connected with the output end of the neutralizing inductor and the source of the first common gate tube; the source of the second common gate tube is connected with the input end of the neutralizing inductor; the drain and the gate of the second common gate tube are connected with the output matching circuit; the source and the gate of the first common gate tube are connected with the auxiliary amplification circuit. The application can realize the balance of multiple indexes such as linearity, power consumption, gain and matching. The application can be widely applied in the field of radio frequency integrated circuit technology.

This invention provides a cascode-type amplifier circuit with suppressed overvoltage input. [Solution] The amplification circuit 1 comprises an input terminal 101 and an output terminal 102, an FET 11 having a gate terminal g1, a drain terminal d1 and a source terminal s1, an FET 12 having a gate terminal g2, a drain terminal d2 and a source terminal s2, a diode 511 having a first anode terminal and a first cathode terminal, and a diode 512 having a second anode terminal and a second cathode terminal. The gate terminal g1 is connected to the input terminal 101, the drain terminal d1 is connected to the source terminal s2, the drain terminal d2 is connected to the output terminal 102, the first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal 101 and the gate terminal g1, and the second anode terminal and the first cathode terminal are connected to the drain terminal d1.

The invention provides a double-coupling inductor Cascode ultra-wideband low-noise amplifier. The double-coupling inductor Cascode ultra-wideband low-noise amplifier comprises an input matching network, a first amplifier, an inter-stage matching network, a second amplifier and an output matching network which are connected in sequence, the first amplifier comprises a first RC negative feedback loop, a first source negative feedback inductor and a first double-coupling inductor loop; and the second amplifier comprises a second RC negative feedback loop, a second source negative feedback inductor and a second double-coupling inductor loop. According to the amplifier provided by the invention, the high-frequency gain of the low-noise amplifier is improved by introducing unstable factors to intermediate frequency and high frequency, so that the working frequency band is widened, and relatively high gain is kept.

Amplifiers with differential transformers for high peaking frequency are described herein. An example amplifier includes a differential transistor pair, an auxiliary transistor pair coupled to the differential transistor pair, a differential transformer coupled between base terminals of the auxiliary transistor pair, and a bias circuit coupled between base terminals of the auxiliary transistor pair. The differential transformer can be embodied as a coupled-line transformer. The bias circuit can include a first bias circuit coupled between a first coupled line of the differential transformer and a base terminal of a first transistor among the auxiliary transistor pair, and a second bias circuit coupled between a second coupled line of the differential transformer and a base terminal of a second transistor among the auxiliary transistor pair.

Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

This invention belongs to the field of integrated circuit technology, specifically relating to an LDO circuit that achieves precise zero-point control through Cascode compensation. The circuit includes a first-stage error amplifier, a second-stage buffer, a third-stage output power transistor, a feedback circuit, and a compensation module for precise zero-point control. By employing a unique controlled resistor combined with Cascode compensation technology, this invention achieves precise zero-point tracking of the output power transistor's load current changes during compensation. This solves the core problem of difficulty in controlling the Q-value of the conjugate pole under heavy loads in Cascode compensation, which leads to low bandwidth and slow output transient response.

This disclosure relates to an adaptive cascode gate bias generation circuit. The circuit includes a first resistor, a second resistor, a current source, and a transistor. The first resistor is located between a voltage rail and a drive interconnect. The drive interconnect and the voltage rail are electrically connected to the first resistor. The second resistor is located between the drive interconnect and ground. Ground and the drive interconnect are electrically connected to the second resistor. The current source is located between the voltage rail and the drive interconnect. The drive interconnect and the voltage rail are electrically connected to the current source. The transistor is located between the drive interconnect and a snubber interconnect. The drive interconnect and the snubber interconnect are electrically connected to the transistor.

A radio frequency (RF) switch employing differential signal cancellation is disclosed. The differential RF switch enables high isolation and extremely small size by employing cascode current steering within a differential switching amplifier. Unlike series RF switches, isolation with the differential RF switch is limited by device mismatch, not switch parasitic capacitance, enabling high frequency operation. Since the differential RF switch can be placed within the already present cascode devices, there is no additional insertion loss from the switch.

The invention discloses a multi-stage feedback broadband low-noise amplifier which comprises a first-stage amplifier, a second-stage amplifier and an output-stage buffer amplifier. The first-stage amplifier is composed of a cascode structure and a current multiplexing structure; the second-stage amplification electric appliance is composed of a complementary common-source structure and a current multiplexing structure. The output stage buffer amplification circuit is composed of a common source buffer structure and a current multiplexing structure. According to the invention, the cascade structure and the complementary common-source structure are connected in parallel, and inter-stage capacitance offset, source inductance and current multiplexing are adopted. By means of the mode, the use efficiency of current in the circuit is improved, the circuit gain and noise performance and the like are improved, on the other hand, the Miller effect is effectively restrained, a dominant pole is pushed to high frequency, and therefore the circuit bandwidth is greatly expanded.

An antenna tuner receives outputs of detectors coupled to an input and / or an output of each power amplifier (PA) of a plurality of PAs of a multiple antenna system. A processor of the antenna tuner is configured to process the detector outputs and to generate at least one of a gm gate bias value and a cascode gate bias value to be applied to gm and cascode gates, respectively, of a last stage of each of the PAs to change the shape of an input amplitude-to-output amplitude (AM-AM) response of each of the PAs independently of one another. The processor can also be configured to process the detector outputs to generate a varactor bias value to be applied to a terminal of a varactor of each of the PAs to change the shape of an input amplitude-to-output phase shift (AM-PM) response of each of the PAs independently of one another.

The application relates to a silicon-based millimeter wave broadband compact double-drive high-efficiency Doherty power amplifier, belonging to the technical field of radio frequency integrated circuits, comprising an input quadrature coupler, a main and auxiliary two power amplifier paths and a broadband load modulation output network; wherein the power amplifier path adopts a differential common source and common gate unit with cross-coupling capacitance and a double-mode drive topology to improve the gain and efficiency of the millimeter wave frequency band; the output network adopts a slow wave transmission line structure combined with a cascade coupling line pair to realize broadband active load modulation and absorb transistor parasitic capacitance, and simultaneously optimize the chip area. Thus, the problem that the efficiency and bandwidth are difficult to be considered simultaneously due to the limited load modulation bandwidth and the decreased transistor gain of the traditional silicon-based millimeter wave Doherty power amplifier is solved.