617 results about "Cascode" patented technology

The invention provides a low-noise amplification circuit and a radio frequency power amplifier module, and the low-noise amplification circuit comprises an input matching circuit, a cascode amplification structure, an output matching circuit and a path switching assembly. The input matching circuit comprises a first inductor, a second inductor, a first capacitor and a third inductor; the output matching circuit comprises a fourth inductor, a second capacitor, a fifth inductor, a third capacitor and a fourth capacitor; and the access switching assembly is used for selecting channels of the low-noise amplification circuit, so that a radio frequency signal accessed by the first inductor is directly output or output after being amplified by the cascode amplification structure. According to the low-noise amplification circuit, on the premise that the noise coefficient is reduced and the gain is matched, the order of an input and output matching network does not need to be increased, and correspondingly, the cost and the area of the low-noise amplification circuit are not increased.

The invention discloses a cascode cascade type switching device with a cascode current limiting structure. The cascode cascade type switching device comprises a grid end, a source end, a drain end, a low-voltage enhancement type field effect transistor, a high-voltage depletion type field effect transistor and the current limiting structure. The current limiting structure comprises a plurality of common-gate current limiting depletion type field effect transistors and a current limiting resistor. According to the current-limiting depletion type field-effect transistor, when a switching device is turned on, the grid current of the high-voltage depletion type field-effect transistor can be limited through the current-limiting resistor and the series internal resistors of the plurality of current-limiting depletion type field-effect transistors, so that the working reliability of the current-limiting depletion type field-effect transistor and the whole switching device is improved.

The invention discloses a C / X wave band ultra-wideband GaAs MMIC low-noise amplifier, and mainly relates to the technical field of radio frequency front ends. Comprising an input matching network used for receiving a radio frequency signal and performing impedance matching so as to effectively transmit the signal to a subsequent active amplification part; and the active amplification part adopts an improved cascode-cascode cascade amplification structure and is used for amplifying the radio frequency signal transmitted by the input matching network. The amplifier has the advantages that an improved cascode-cascode cascade amplification structure is adopted, the gain is improved through an improved Cascode structure, the noise coefficient of the circuit is reduced, and the performance indexes of ultra wide band, low noise and high gain are achieved. The design of the structure not only improves the overall performance of the amplifier, but also enables the amplifier to keep stable gain output in a broadband range, and effectively solves the problems of low gain and high noise of a traditional low-noise amplifier in broadband application.

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

Disclosed herein is a single photon avalanche diode (SPAD) pixel circuit, including a SPAD having an anode coupled to a negative voltage and a cathode and a cascode transistor having a drain coupled to the cathode of the SPAD, a gate controlled by a cascode control signal, and a source. A readout circuit is coupled to the source of the cascode transistor and configured to detect a voltage change at the source of the cascode transistor and generate a pulse indicating an occurrence of an avalanche event. An active quenching circuit is coupled to the cathode of the SPAD and configured to detect an onset of the avalanche event and pull the cathode of the SPAD to a negative voltage to quench the avalanche event.

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

The invention discloses a reference voltage generation module, a power supply system, an image sensor, equipment and a vehicle, the reference voltage generation module comprises a self-bias current source, a micro-current source, a first current mirror and a first reference circuit, the self-bias current source comprises the micro-current source used for generating bias current with a positive temperature coefficient, and the micro-current source is used for generating bias current with a negative temperature coefficient; the first current mirror is connected with the micro current source, and the first current mirror is of a low-voltage cascode structure and is used for performing mirror image output on the bias current; the first reference circuit is connected with the first current mirror, and the first reference circuit is used for generating a current with a negative temperature coefficient and generating a first reference voltage based on the bias current and the current with the negative temperature coefficient. The reference voltage generation module does not need to be compensated by a capacitor, so that the starting time and the response speed of the system are ensured.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

The present invention provides a stacked cascade GaN-based power device and a packaging method thereof. The device structure is a DBC double-sided ceramic substrate with through holes and grooves bonded on a TO-220 frame, a GaN-based chip bonded in the groove of the DBC ceramic substrate, and a vertically structured silicon-based MOSFET stacked on the source of the GaN-based chip to form a Cascode cascade structure. The present invention realizes the Cascode cascade structure by rationally arranging the GaN-based chip and the silicon-based MOSFET chip, thereby reducing the area of ​​the frame occupied by the chip, reducing the volume of the package body and improving the selectivity of the packaging form; the high thermal conductivity DBC double-sided ceramic substrate with through holes and groove structures increases the contact area between the chip and the high thermal conductivity material, improves the heat dissipation performance of the chip, optimizes the process steps, and improves the reliability and practicality of the device.

A bandgap reference circuit includes a first, a second and a third current source, a first and a second amplifier. The first, the second and the third current source each includes two cascode PMOS transistors for reducing the voltage stress applied to PMOS transistors when receives a high power supply voltage. The first amplifier controls the PMOS transistors in the first and the second current source to ensure that the PMOS transistors have enough headroom when receives a low power supply voltage. The second amplifier provides a gain-boosting loop to prevent the system mismatch of the PMOS transistors in the first, the second and the third current source. A temperature coefficient adjustment unit introduces positive temperature coefficients and negative temperature coefficients in the currents generated by the first and second current source, and a resistor generates the reference voltage according to a current duplicated by the third current source.

An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.

A cascode switch device includes a normally-on switch device, a normally-off switch device, and a gate driver. The normally-on switch device has a first terminal, a second terminal and a control terminal. The normally-off switch device has a first terminal, a second terminal and a control terminal. The first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device. The gate driver is configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device. The normally-on switch device is turned on or turned off in response to the gate driver signal.

The embodiment of the utility model discloses a cascode cascade device which is applied to the technical field of semiconductor manufacturing. In a cascode cascade device, a source electrode and a grid electrode of a low-voltage enhanced field effect transistor are respectively used as a source electrode end and a grid electrode end of the cascade device, and a drain electrode of a high-voltage enhanced field effect transistor is used as a drain electrode end of the cascade device, so that a balancing circuit and an adjusting circuit can be integrated on the low-voltage enhanced field effect transistor; and the balancing circuit and the adjusting circuit only relate to the resistor and the diode, and when the resistor and the diode are integrated on the low-voltage enhanced field effect transistor, only one mask needs to be added, so that the process cost is relatively low. And redundant devices do not need to be integrated on the high-voltage field-effect tube in the cascade device, so that the area of the high-voltage field-effect tube is saved, and the overall cost of the cascade device is relatively low.

The invention discloses a gain boosting type floating anti-phase dynamic amplifier circuit, and relates to the technical field of integrated circuits, the gain boosting type floating anti-phase dynamic amplifier circuit comprises a power supply, a main amplifier, a first auxiliary amplifier and a second auxiliary amplifier, and the main amplifier and the auxiliary amplifiers both adopt a cascode floating anti-phase dynamic amplifier structure; the main amplifier comprises a first power supply capacitor, a second power supply capacitor, a plurality of first common-source transistors and a plurality of first common-gate transistors; a plurality of drain electrodes of the plurality of first common-source transistors are respectively connected with the input ends of the first auxiliary amplifier and the second auxiliary amplifier, and a plurality of grid electrodes of the first common-gate transistors are respectively connected with the output ends of the first auxiliary amplifier and the second auxiliary amplifier; the first auxiliary amplifier and the second auxiliary amplifier each comprise a plurality of second common-gate transistors, and a plurality of gates of the second common-gate transistors are directly connected to the common-mode level. According to the amplifier circuit, the gain of the amplifier is improved on the premise that the speed and the stability are guaranteed.

The invention provides a low-noise amplifier and a radio frequency front-end module, and the low-noise amplifier comprises an input matching circuit, a first-stage power amplification circuit, an inter-stage matching circuit, a second-stage power amplification circuit and an output matching circuit. The inter-stage matching circuit comprises a first inductor, a second inductor and a first capacitor; the second-stage power amplification circuit is of a cascode structure; and the output matching circuit comprises a third inductor and a fourth inductor which are coupled with each other. According to the low-noise amplifier, the high-frequency gain, the in-band gain flatness, the isolation degree, the stability and the output matching bandwidth of the low-noise amplifier can be improved.

According to another disclosed embodiment, an energy efficient implantable neurostimulator for delivering one or more electrical pulses to a target region within a patient's body is provided. The neurostimulator includes a converter for generating the stimulation current, wherein the converter includes a voltage increasing circuit and a voltage reducing circuit. The stimulator may also include a current source that includes a pair of cascode arranged transistors that are controlled to maintain an amplitude of the stimulation current substantially constant. The neurostimulator may also include a bias voltage power supply that powers a selecting circuit for selecting one of the voltage increasing or voltage decreasing circuits.

A voltage regulator includes an input power supply node, an output regulated power supply node, a flipped voltage follower circuit, and a compensation capacitor. The flipped voltage follower circuit includes an output transistor configured as a common-source amplifier circuit. A source terminal of the output transistor is coupled to the input power supply node and a drain terminal of the output transistor is coupled to the output regulated power supply node. The flipped voltage follower circuit includes a folded cascode feedback circuit. The folded cascode feedback circuit includes a folding node. The folded cascode feedback circuit is configured to receive an output regulated voltage on the output regulated power supply node and to provide a feedback signal to a gate terminal of the output transistor. The compensation capacitor is coupled to the output regulated power supply node and the folding node.

An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.

The invention discloses a low-noise amplifier applied to millimeter waves, the low-noise amplifier comprises a first-pole cascode amplification circuit and a second-pole cascode amplification circuit, the first-pole cascode amplification circuit comprises NMOS (N-channel metal oxide semiconductor) transistors NM1 to NM2, mutual inductor inductors L1 to L2 with the mutual inductance coefficient of K1, capacitors C1 to C3, mutual inductor inductors L4 to L5 with the mutual inductance coefficient of K2 and an inductor L3; and the second-stage common-source amplification circuit comprises an NMOS transistor NM3, inductors L6-L8 and a capacitor C4. The input end of the low-noise amplifier disclosed by the invention uses the coupled resonator to carry out impedance matching for compensating a narrower working bandwidth caused by the single resonant frequency of the source degeneration inductor amplifier, so that the working bandwidth of the low-noise amplifier is improved. The low-noise amplifier is simple in function implementation mode, and has high gain flatness and noise flatness on the basis of function implementation.

Composite cascode power amplifiers for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a composite cascode power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The composite cascode power amplifier includes an enhancement mode (E-MODE) field-effect transistor (FET) for amplifying the RF signal and a depletion mode (D-MODE) FET in cascode with the E-MODE FET.

An electronic device may include wireless circuitry having a transformer with a primary coil and a secondary coil, a first series inductor coupled to the primary coil, a second series inductor coupled to the primary coil, and a filter inductor inductively coupled to the first and second series inductors and operable to produce a first filter response when the wireless circuitry is operable in a first mode and a second filter response when the wireless circuitry is operable in a second mode. The transformer can be coupled to another filter inductor. The transformer can be coupled to an active circuit. The active circuit can include input transistors and cascode transistors. The cascode transistors can be coupled to resistors and / or capacitors that are selectively activated using associated filter switches.

The invention provides a millimeter wave digital power amplifier based on a serial transmission line balun synthesis network, and belongs to the technical field of millimeter wave digital power amplifiers. According to the millimeter wave digital power amplifier, firstly, a driving power distribution network based on a bridge and a transformer is adopted, and radio frequency power is subjected to differential conversion and then input into a digital power amplifier unit array; secondly, the digital power amplifier unit adopts a differential Cascode structure with a neutralizing capacitor, so that the gain and the output impedance of the digital power amplifier unit can be effectively improved; finally, a synthesis network based on a series transmission line balun is adopted, the synthesis network can realize active load modulation optimization of the digital power amplifier, the impedance matching condition of the digital power amplifier under the maximum and partial rollback output power levels is improved and balanced, and the overall efficiency is improved.

The invention discloses a high-linearity medium-power amplifier based on cascode RC negative feedback and a composite matching network. The high-linearity medium-power amplifier comprises a common-source transistor M1, a common-gate transistor M2, a single power supply VDD with an active bias circuit, an input matching network, an output matching network and a negative feedback loop, the input matching network comprises an inductor Lb and an inductor Lg, the output skin matching network comprises an inductor Ld1 and an inductor Ld2, and the negative feedback loop comprises a resistor Rf and a capacitor Cf; the source electrode of the common source transistor M1 is connected with the drain electrode of the common gate transistor M2, one side of the active bias circuit is connected to the grid electrode of the common source transistor M1 through the inductor Lb and the inductor Lg in sequence, the common end of the inductor Lb and the inductor Lg is connected with the input end, and the resistor Rf and the capacitor Cf are connected in series and connected between the grid electrode of the common source transistor M1 and the output end. One side of the inductor Ld2 is connected with the source electrode of the common-gate transistor M2, the other side of the inductor Ld2 is connected with one side of the inductor Ld1, the other side of the inductor Ld1 is connected with the single power supply VDD, and the common end of the inductor Ld1 and the inductor Ld2 is connected with the capacitor Cf and the output end; the method is suitable for radar and communication systems in industrial application, and has important significance for developing high-performance, low-cost and high-integration-level multifunctional chips.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.

The invention relates to a low-noise transconductance amplifier, a chip, a receiver and electronic equipment, the low-noise transconductance amplifier comprises a first-stage amplification circuit and a second-stage amplification circuit, the first-stage amplification circuit comprises a first-stage input end, a cascode amplification module, a common-source module, a feedback resistor and a first-stage output end, and the second-stage amplification circuit comprises a second-stage input end and a second-stage output end; the cascode amplification module is used for carrying out input matching and amplification processing on an input signal and outputting an obtained first-stage output signal through a first-stage output end; the common source module is used for carrying out noise elimination on an input signal; the second-stage amplification circuit comprises a second-stage input end, a transconductance amplification module and a second-stage output end which are connected in sequence, and the transconductance amplification module is used for conducting transconductance amplification and linearity adjustment on the first-stage output signal and outputting the obtained second-stage output signal through the second-stage output end. According to the low-noise transconductance amplifier, the performance of high gain, high linearity and large bandwidth of the low-noise transconductance amplifier is achieved.

The invention discloses a low-voltage cascode NMOS (N-channel Metal Oxide Semiconductor) current mirror circuit which comprises a basic current mirror circuit, a biasing circuit and an operational amplifier feedback network, the basic current mirror circuit is used for forming a current mirror by adopting an NMOS (N-channel metal oxide semiconductor) transistor pair, and generating a corresponding output current IOUT after mirroring the received reference current IIN; the bias circuit is used for providing bias voltage for the basic current mirror circuit; the operational amplifier feedback network is used for forming a closed-loop feedback network of the basic current mirror circuit through the operational amplifier, so that the voltage of the input end of the basic current mirror circuit is equal to the voltage of the output end of the basic current mirror circuit. According to the invention, the operational amplifier is introduced to form a closed loop feedback network, so that the potentials of the input / output branches of the basic current mirror circuit are strictly matched, and the problem that the mirror image precision of a traditional structure is reduced due to drain electrode voltage mismatch is solved.

The invention discloses a layout processing method for reducing parasitic RC through a cascode structure, and relates to the technical field of integrated circuit design. According to the method, parasitic RC is reduced through a cascode structure, the performance of a high-frequency module of a chip is improved, MOS transistor and metal wire parameters are extracted by analyzing a layout file, a report is generated by utilizing a parasitic parameter extraction tool, a distribution map is generated through mapping to identify a high parasitic area, an optimizable MOS transistor combination is identified according to the distribution map, a cascode structure diagram is designed, and the high-frequency module performance of the chip is improved. Guiding re-layout and re-wiring of MOS (Metal Oxide Semiconductor) tubes in layout software, combining a source end and a drain end, optimizing a connection path, performing layout verification and circuit simulation, comparing parasitic parameters and working frequencies before and after optimization, and generating a simulation report; the parasitic effect can be accurately quantified, the layout is optimized, parasitic parameters are reduced, the module working frequency is effectively improved, and the design requirement of a high-performance chip is met.

The invention discloses a monolithic integrated vertical GaN Cascode device structure and a preparation method thereof. The monolithic integrated vertical GaN Cascode device structure comprises a GaN MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a depletion type vertical GaN HEMT (High Electron Mobility Transistor) which are integrated on a Si-based substrate, wherein the drain electrode of the GaN MOSFET is connected with the source electrode of the GaN HEMT, the grid electrode of the GaN MOSFET serves as the grid electrode of the vertical GaN Cascode device structure, the source electrode of the GaN MOSFET is connected with the grid electrode of the GaN HEMT and then serves as the source electrode of the vertical GaN Cascode device structure, and the drain electrode of the GaN HEMT serves as the drain electrode of the vertical GaN Cascode device structure. The invention can solve the problems that the traditional cascade Cascode device is large in size, complex in packaging, large in parasitic parameter, low in mobility and limited by the material performance of the Si tube.