3543results about "Amplifier combinations" patented technology

A modular broadband transmission system and method include an input signal connector that receives an input signal which is then divided into N parts and amplified with an amplifier have N power amplifier modules. Outputs of the N power amplifier modules are passed through transmission lines and to a radial combiner that combines the outputs. The radial combiner, transmission lines and power amplifier modules are configured such that if one of the power amplifier modules fails, the other power amplifier modules may still operate acceptable well, with minimal impact on total output power. An output of the amplifier is provided to a coupler that measures a power level of the output signal and feeds the measured power level back to a controller where the controller adjust an overall output power based on the number of the power amplifier modules that are functioning properly. Each of the power amplifier modules have a processor such that respective of the power amplifier modules may be taken off-line, and replaced while the other power amplifier modules continue to operate in a transmit mode of operation. The modular broadband transmission system and method may conveniently be used as either a broadband booster for amplifying a plurality of input signals, or a head and transmitter configured to amplify one or more different input signals.

An amplification architecture or system is provided having a multiple amplifier system that switches modes of operation between operation in a component mode and a composite mode based on a characteristic of an input signal relative to a threshold level. In the component mode, the components of the input signal are employed to different terminals of the multiple amplifier system that provide a reconstructed amplified representation of the input signal. In the composite mode, the input signal is amplified to provide an amplified representation of the input signal.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

A high linearity Doherty power amplifier with phase delay generation and control via passive and active components. In one embodiment, phase delay generation and control is implemented by an active phase shifter comprising a lower differential unit for generating a first differential output signal, an upper differential unit for generating a second differential output signal, and a phase control unit for tuning a phase difference between the first and second differential output signals within a phase tolerance. In addition, to improve efficiency and linearity characteristics, the power amplifier receives a voltage control signal to bias a supplemental amplifier so that the power amplifier operates in a Doherty mode in a low output power range and in a non-Doherty mode in a high output power range.

Optimization methods via various circuital arrangements for amplifier with variable supply power are presented. In one embodiment, a switch can be controlled to include or exclude a feedback network in a feedback path to the amplifier to adjust a response of the amplifier dependent on a region of operation of the amplifier arrangement (e.g. linear region or compression region).

A predistortion circuit for a microwave amplifier and more particularly to predistortion circuit configured as a Doherty amplifier. The predistortion circuit is adapted to be coupled to a downstream Doherty amplifier to precompensate for the gain compression and phase expansion of the downstream Doherty amplifier as the input power level is increased while simultaneously reducing the intermodulation (IM) distortion. In order to provide precompensation, the precompensation circuit is operated at bias level to provide gain expansion and phase compression to cancel out the gain compression and phase expansion of the downstream Doherty amplifier to provide a higher overall linear power added efficiency (PAE).

A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

A switched-mode Class F power amplifier is provided for parallel connection with at least one other like amplifier, within a Chireix architecture, for combining the signals output therefrom. An input component includes at least one active device configured to be alternately switched by a signal input thereto to present an amplified signal corresponding to the input signal and constituting a low output impedance voltage source. A lumped element impedance inverter is provided between the input component and an output resonator component, the impedance inverter being configured for transforming the low output impedance voltage source to instead constitute a high output impedance current source configured for said parallel connection. In accordance with the invention, the negative reactive component values required by the impedance inverter are eliminated and effectively provided by incorporating those values into pre-selected reactive components of the input and output components. Further, a source-drain parasitic capacitance across the active device is eliminated by one or more pre-selected reactive components of the input component, the value(s) of which effectively compensate for the parasitic capacitance.

An amplifier that modulates a carrier frequency according to a digital signal and amplifies the modulated signal includes a determining portion that determines at least one of a sound quality required for the digital signal, a sound source of the digital signal, and a type of sound of the digital signal, a carrier frequency setting portion that sets a carrier frequency according to a result of the determination, and a pulse-width modulating portion that pulse-width modulates the carrier frequency according to the digital signal.

A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (V_cc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.

A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first switching converter and the multi-stage filter form a feedback loop, which is used to regulate the first switching power supply output signal based on the setpoint. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

Systems, methods, and devices relating to the provision of deliberate predistortion to an input signal to compensate for distortions introduced by an amplifier subsystem. An input signal is received by a predistortion subsystem which applies deliberate predistortions to the input signal to arrive at a predistorted signal. The predistorted signal is received by an amplifier subsystem which decomposes the signal, processes the decomposed signal, and then recombines the components to arrive at a system output signal. The predistortion subsystem adaptively adjusts the predistortions based on characteristics of the system output signal. A feedback signal, a replica of the system output signal, is used in updating lookup table entries used to determine the predistortion.

A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers. The complementary self-biased comparators can be used for receiving binary or multi-level-transition (MLT) inputs by selecting different voltage references for threshold comparison. Using the same reference on both differential inputs eliminates a second reference for multi-level inputs having three levels. Thus binary and MLT inputs can be detected and decoded by the same decoder.

A polar modulation transmitter circuit provides reduced ACPR in its output signal by controlling the relative delay between its envelope and phase modulation operations based on direct or indirect feedback measurement the output signal's ACPR. Such measurement and associated control may be based on a delay controller that includes an ACPR measurement circuit and a delay control circuit. Additionally, or alternatively, the polar modulation transmitter circuit provides a greatly extended transmit power control range by using a staged amplifier circuit that includes a driver amplifier circuit operating in combination with a power amplifier circuit to impart desired envelope modulation. In an exemplary embodiment, the driver amplifier circuit is implemented as differential transistor pairs responsive to tail current modulation. As such, the driver amplifier circuit is suited in particular for economical and space saving integration within a transmitter or transceiver integrated circuit (IC).

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

The present invention relates to a preamplifier suitable for use with Electret Condenser Microphones such as used within telecommunication equipment. More particularly the invention relates to a preamplifier specially suited for the demands to such a preamplifier within telecommunication equipment: low input capacitance, gain and a combined terminal for output and supply voltage, thus making the preamplifier suitable for two terminal microphone assemblies. These features are obtained with a two stage amplifier with a first stage optimised for low input capacitance and the second stage being able to provide gain. The preamplifier may be implemented using an ASIC, thus making the preamplifier suitable for applications with very limited space available, such as for integration within microphone assemblies.