79 results about "Adaptive bias" patented technology

An adaptive bias circuit is provided for an amplifier module including a RF power amplifier for amplifying an input signal to generate an output signal, wherein the bias circuit receives the input signal to adjust a driving current to control a quiescent current of the RF power amplifier. The adaptive bias circuit includes means for providing the driving current to the bias circuit and means for drawing a bypass current from the providing means to reduce the driving current in response to the input signal, wherein the quiescent current is reduced when the driving current is reduced and the bypass current increases when the input signal is reduced.

Disclosed are a circuit and a method for adaptively biasing a voltage regulator with minimal output overshoot. The circuit includes an adaptive bias current mirror circuit further including a first transistor and a second transistor, the first transistor and the second transistor having source nodes coupled to a drain node of the first transistor. The circuit includes a common node coupled to the source node of the first transistor and the source node of the second transistor, wherein a source degenerate resistor is coupled to the adaptive bias current mirror circuit and is coupled to the common node and wherein the source degenerate resistor is configured to limit an output peak current of the voltage regulator circuit.

A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages arc supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.

Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

A power amplifier includes a LDMOS transistor having a source, a drain, a control gate and a shielding electrode positioned between the control gate and the drain, and means for adaptively biasing the drain and shielding electrode power information for a RF signal.

An amplifier circuit using an adaptive bias control comprises an envelope detector for detecting an envelope of an input signal from a coupler, envelope shaping circuits for transforming of the envelope voltage from the envelope detector. The one transformed envelope voltage is applied to a drain bias for the peaking amplifier and the other is add by VDC to be applied to a gate bias for the carrier amplifier. In the Doherty amplifier, the gate voltage of the peaking amplifier and the drain voltage of the peaking amplifier are controlled in accordance with the input signal envelope to maximize efficiency with a desired linearity.

Linear-in-dB current-steering VGAs with an adaptive bias current operable so that as the gain of the amplifier decreases, the DC current consumption also decreases. The modified VGA circuits result in power consumption savings, which are of particular value in wireless (battery powered) applications.

In a comparator circuit having a differential amplifier, which makes a logical judgment by comparing an input voltage with a reference voltage, generates and outputs a resulting output voltage thereof, a current source generates and supplies a bias current of a predetermined minute current to the differential amplifier, and a first inverter circuit inverts a differential voltage from the differential amplifier. An adaptive bias current generator circuit detects the bias current of the current source, and a through current of the first inverter circuit. The adaptive bias current generator circuit generates and supplies an adaptive bias current for executing adaptive bias current control to the differential amplifier to allow the differential amplifier to operate with the bias current upon no logical judgment, and to allow the differential amplifier to operate by using the adaptive bias current obtained by increasing the bias current upon logical judgment.

A method and circuits to improve the stability of low dropout voltage regulators having an adaptive biased driving stage. Said improvement of stabilization is valid through the total range of output current possible. A serial impedance is added to the gate capacitance of the PMOS pass device of said LDO. Said serial impedance could be a resistor or a transistor. In case of low load currents said impedance is not dominating, for high load currents said impedance keeps the gate pole close to the resonance frequency of the output tank. In case of medium load currents, wherein the inner resistance of the driving stage is about equal to said serial impedance, the gate pole could get too low. This problem is solved by reducing said serial impedance by shunting. Said shunting can be performed stepwise depending on the size of the load current. A special circuitry detects the condition of medium load currents and can initialize the shunting of said serial impedance accordingly in order to keep the gate pole on the optimum frequency.

The invention discloses an adaptive bias circuit with low loss and temperature compensation. The adaptive bias circuit comprises a first NPN type triode having a current mirror structure, a second NPN type triode, a transistor, a bias capacitor and a first resistor. By means of a specific circuit connecting structure, the potential of the bias capacitor can be kept unchanged when the input power is increased and does not exceed the critical value, therefore the current of the collector of a power tube is increased with the increase of the input power, and when the input power is further increased and exceeds the critical value, the potential of the bias capacitor is reduced, therefore the current of the collector of the power tube is reduced with the increase of the input power and finally trends to be stable. In addition, the temperature of the power tube can be compensated by the first resistor to improve the thermal temperature. The invention further discloses a wireless transmitting system comprising the above circuit, and the beneficial effects are as mentioned above.

A differential amplifier circuit includes a differential operational amplifier that includes a differential pair circuit and operates based on a constant bias current supplied from a bias current source circuit, and the differential amplifier circuit includes a bias current generator circuit. A current monitor circuit detects two currents flowing through the differential pair circuit in correspondence with differential input voltages inputted to the differential pair circuit, and detect a minimum current of the two currents for a difference voltage of the differential input voltages as a monitored current. A current comparator circuit compares the monitored current with the constant bias current. A current amplifier circuit amplifies a voltage corresponding to the comparison result, and controls currents flowing through the differential pair circuit based on an amplified voltage, and the bias current generator circuit performs negative feedback adaptive control such that the bias current increases as the monitored current decreases.

A low-dropout (LDO) voltage regulator includes an adaptive bias source for generating a bulk-bias signal to a pass device in the LDO voltage regulator, wherein the adaptive bias source generates the bulk-bias signal based on a signal obtained at an output of the LDO voltage regulator. The signal includes a current signal, which is proportional to a current at the output of the LDO voltage regulator, and/or a feedback signal from a feedback path connected between the adaptive bias source and the output of the LDO voltage regulator for sensing negative and/or positive spikes.

The invention discloses a positive and negative voltage dynamic bias level shifting circuit based on negative voltage detection and band-gap references, comprising a power supply voltage detector, an adaptive bias circuit and a level shifting circuit, wherein the power supply voltage detector is used for detecting the negative power supply voltage and positive power supply voltage of a chip, respectively comparing the negative power supply voltage and the positive power supply voltage with a ground level, and outputting a negative power supply voltage signal when the positive power supply voltage reaches a set value and the negative power supply voltage reaches a threshold; the adaptive bias circuit is used for adaptively adjusting bias current according to the negative power supply voltage signal and the power supply voltage; and the level shifting circuit is used for implementing level shifting on a driving signal according to the positive power supply voltage, the negative power supply voltage signal and the bias current to obtain a switch signal which cannot be changed with the power supply voltage and has fixed rising and falling edge delays. According to the positive and negative voltage dynamic bias level shifting circuit disclosed by the invention, the signal transmission distortion caused by power supply voltage changes even the negative voltage can be solved, and thus high reducibility of the signals in a level shifting process under high-speed signal transmission can be improved.

In one aspect, a method of reducing power consumption in a circuit by adaptive bias current generation of a bias current configured to bias, at least in part, at least one amplifier of the circuit is provided. The method comprises establishing the bias current based, at least in part, on a reference frequency of a reference clock providing a clock signal to at least one component of the circuit, and changing the bias current in response to a change in the reference frequency of the at least one reference clock, the bias current being change non-linearly with respect to the change in the reference frequency of the at least one reference clock. In another aspect, the method comprises establishing the bias current based, at least in part, on a capacitance of a reference capacitor, and changing the bias current in response to a change in the capacitance of the reference capacitor such that the bias current is changed non-linearly with respect to changes in the capacitance of the reference capacitor.

Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.