199 results about "Current sense amplifier" patented technology

An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

A data path including a local input/output (LIO) line and a global input/output (GIO) line coupled together through an input/output (IO) line coupling circuit. The coupling circuit is coupled to an internal voltage supply, and couples and decouples signal lines of the GIO line from the supply terminal according to read data coupled to the LIO line. The GIO line is coupled to a current sense amplifier to generate output voltage signals that are coupled to an output buffer. An example of a current sense amplifier coupled to the GIO line includes first and second load circuits and first and second n-channel MOS (NMOS) transistors coupled to a respective load circuit. The gates of NMOS transistors are cross coupled, and input current signals are coupled to source terminals of the NMOS transistors and the output voltage signals are coupled from the drain terminals of the NMOS transistors.

An amplifier configuration including first and second amplifier inputs and a bias input adapted to receive a common mode signal indicative of a common mode input voltage. First and second amplifier input stage sections, each having first and second inputs coupled to respective ones of the first and second amplifier inputs, are provided. Operating mode circuitry switches the amplifier configuration between first and second operating modes in response to the common mode signal, where in the first operating mode the first and second amplifier input stage sections are active and inactive, respectfully and where in the second operating mode the first and second amplifier input stage sections are inactive and active, respectfully. The active first and second amplifier input stage sections are capable of operating with common mode voltages in excess of the upper and lower power supply rails, respectively.

The present invention provides a battery health condition detection module and a battery with a detection module. The problem of the health state monitoring of each single battery in a battery pack is solved, the voltage, current, battery capacity and temperature state monitoring of the single battery in the battery pack is carried out, and the detection module and each single battery are made into an integrated battery with the detection module which is integratedly formed. The invention also provides a battery health condition detection system, the measurement and record data obtained by the detection module is sent to an external data receiving and controlling system in a wireless mode, the external data receiving control system carries out analysis processing, and even the battery pack is sealed, the monitoring of the health condition of each single battery in the battery pack by the external data receiving and controlling system is not affected. The battery health condition detection module comprises a current sensing amplifier circuit, a battery voltage detector circuit, a temperature sensing amplifier circuit, an RTC time controller, a micro control unit, and a module power supply circuit.

The present invention belongs to the field of integrated circuit technology, and is especially one kind of current mode sense amplifier for embedded SRAM. The current mode sense amplifier consists of mainly bit line clamp circuit, cross coupling inverter, equalizing circuit and I/O buffer. The sense amplifier can realize both the read operation and the write operation on SRAM unit by means of the differential current signal, rather than traditional differential voltage signal, resulting in very small bit line voltage swing and effectively lowered memory read/write power consumption. Simulation result shows that the sense amplifier has delay insensitive on capacitance variance.

A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled to the sense amplifier output line pair to amplify the differential output voltages on the sense amplifier output line pair. The voltage sense amplifier is activated at the time later than a time of activation of the current sense amplifier. The output stabilizing circuit is coupled to the sense amplifier output line pair to stabilize the differential output voltages on the sense amplifier output line pair. The output stabilizing circuit has a positive input resistance. Accordingly, the sense amplifier circuit reduces power consumption and an occupied area on a semiconductor chip.

A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of cross-coupled transistors, a pair of output nodes and a first pair of load transistors. The pair of cross-coupled transistors may be coupled for receiving a pair of differential currents and for generating a pair of differential voltages, which may then be supplied to the pair of output nodes. The first pair of load transistors may have mutually-connected gate terminals, mutually-connected drain terminals, and a source terminal coupled to a different one of the output nodes. In a unique aspect of the invention, an equalization transistor may coupled between the pair of output nodes for equalizing the pair of differential voltages for a predetermined amount of time at the beginning of a sense cycle. As such, the equalization transistor may be added to prevent the current sense amplifier circuit from generating erroneous results during the predetermined time period.

The selected bit line in a non-volatile memory carries a cell conduction current to be measured and also a leakage current or noise due to weak coupling with neighboring array structures. In a first phase, a sense amplifier senses the bit line current by discharging a capacitor with the combined current (cell conduction current plus the leakage current) over a predetermined time. In a second phase, the cell conduction current is minimized and significantly the leakage current in the selected bit line is used to recharge in tandem the capacitor in a time same as the predetermined time, effectively subtracting the component of the leakage current measured in the first sensing phase. The resultant voltage drop on the capacitor over the two sensing phases provides a measure of the cell conduction current alone, thereby avoiding reading errors due to the leakage current present in the selected bit line.

Disclosed is a memory architecture where current sense amplifiers are used instead of voltage sense amplifiers, and where the memory cells normally disposed along a single bit line are divided between two half bit lines. Each half bit line is coupled to a respective input of the current sense amplifier. When one of the memory cells is selected for reading, it couples a current related to its stored data state to the half bit line that it is coupled to. During this operation, a reference current is generated on the other half bit line. Also disclosed are novel current sense amplifiers.

A sense amplifier has a pair of internal nodes that are precharged to a power-supply level. A first pair of n-channel transistors supplies current to the internal nodes responsive to a pair of data signals, both of which are initially high. When one of the data signals begins falling toward the low level, the corresponding n-channel transistor immediately reduces the current supplied to one of the internal nodes. A second pair of n-channel transistors, cross-coupled to the internal nodes, amplifies the resulting potential difference between the internal nodes, thereby pulling down the potential of one of the internal nodes. An output signal is generated from one or both of the internal nodes. The output signal is obtained quickly, because amplification begins without delay.

An improved interface circuit is provided herein for translating a relatively high input voltage into a relatively low output voltage using only low voltage transistors and a single, low voltage power supply. According to one embodiment, the interface circuit includes a power supply, a pair of input transistors with source terminals coupled together for receiving a relatively low voltage from the power supply, and a current sense amplifier with a pair of input terminals, each coupled to a drain terminal of a different one of the pair of input transistors for receiving a pair of differential currents and for generating a pair of differential voltages therefrom.

The invention provides an LED (Light-Emitting Diode) lamp and an electronic breaker thereof. The electronic breaker is connected in series between a power supply input end and the LED lamp, and comprises a sampling resistor, a field effect transistor and a current detection chip, wherein one end of the sampling resistor is coupled with the LED lamp; a source electrode of the field effect transistor is coupled with the power supply input end; a grid electrode of the field effect transistor is coupled with the other end of the sampling resistor; the current detection chip comprises a current detection amplifier and a voltage comparator; two detection pins of the current detection amplifier are coupled with the two ends of the sampling resistor respectively; an output pin of the current detection amplifier is coupled with an LED alternating-direct (AD) current conversion port, and earthed by a resistance voltage-dividing network; and a locking output pin of the voltage comparator is coupled with a drain electrode of the field effect transistor. The electronic breaker limits current on the LED lamp, timely disconnects a power supply and a load in case of overcurrent, and can detect real-time working current of an LED.

During a blanking period of a video signal, an element driving transistor for controlling a drive current supplied to an EL element is operated in its saturation region to thereby set the EL element to an emission level, and a current flowing through the EL element at that time is detected. Each current detector includes a current detection amplifier and a successive approximation type AD converter, and a DA converter of the successive approximation type AD converter is commonly shared among a plurality of the AD converters. With this arrangement, sufficient AD converting speed can be attained while using a simple structure to execute current detection for correcting display variations.