The invention provides a power device design method and
system, and relates to the technical field of
chip design, and the method comprises the steps: determining the expected
breakdown voltage of a power
field effect transistor; determining epitaxial layer
doping concentration, epitaxial
layer thickness and epitaxial layer resistivity of the power
field effect transistor; determining the well width and the well depth of the power
field effect transistor by combining an
electric field uniformity principle; calculating estimated on-resistance of the power
field effect transistor under different geometric unit types and different well spacing by combining a distribution mode of an
electric field in a
depletion region of the power
field effect transistor; determining a target geometric
unit type; calculating the optimal well spacing of the power
field effect transistor based on the target geometric
unit type; and outputting the epitaxial layer
doping concentration, the epitaxial
layer thickness, the epitaxial layer resistivity, the well width, the well depth, the target geometric
unit type and the optimal well spacing as design parameters. While high performance of the power device design is ensured, the design period is shortened, and the design cost is reduced.