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High speed low power consumption current sensitive amplifier

A technology of sense amplifiers and amplifiers, applied in instruments, static memory, digital memory information, etc., can solve the problem of high power consumption caused by full swing charging and discharging, and achieve reduced power consumption and delay, and small voltage swing. Effect

Inactive Publication Date: 2006-01-04
FUDAN UNIV
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AI Technical Summary

Problems solved by technology

[0005] The write operation to the static memory cell usually needs to fully charge the two bit lines connected to the memory cell to the power supply voltage or discharge to the ground potential. When the parasitic capacitance on the bit line is large, the full swing charge of the bit line Discharging will introduce a lot of power consumption

Method used

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  • High speed low power consumption current sensitive amplifier
  • High speed low power consumption current sensitive amplifier
  • High speed low power consumption current sensitive amplifier

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Embodiment Construction

[0040] exist figure 1 In the circuit diagram shown, the bit line clamping circuit is composed of NMOS transistors M11 and M12 that are normally turned on. M11 and M12 are biased in the linear region, providing a low-impedance path from the bit line to the reference voltage Vref, so that the two bit lines BL1 and BL2 are clamped near Vref. Vref is a low voltage used to precharge the two bit lines. Its value can be set between 0 and 1 / 3Vdd. In the following analysis, Vref is grounded. The read and write operations of this sensitive amplifier are introduced respectively below.

[0041] The process of reading data from the memory cell is divided into two stages, precharge and amplification. In the pre-charging phase, the two transistors M11 and M12 are turned on and work in the linear region, so that the bit lines BL1 and BL2 are clamped at a fixed low voltage to realize the pre-charging of the bit lines. The signal ENA is at a low level, so that the transistors M13 and M14 are...

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Abstract

The present invention belongs to the field of integrated circuit technology, and is especially one kind of current mode sense amplifier for embedded SRAM. The current mode sense amplifier consists of mainly bit line clamp circuit, cross coupling inverter, equalizing circuit and I / O buffer. The sense amplifier can realize both the read operation and the write operation on SRAM unit by means of the differential current signal, rather than traditional differential voltage signal, resulting in very small bit line voltage swing and effectively lowered memory read / write power consumption. Simulation result shows that the sense amplifier has delay insensitive on capacitance variance.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-speed, low-power consumption current-sensing amplifier for peripheral devices of semiconductor memories. Background technique [0002] Semiconductor memories are generally considered to be very important components in digital integrated circuits, and they play a vital role in building application systems based on microprocessors (Microprocessor). In recent years, people increasingly embed various memories (RAM or ROM) inside the processor in order to make the processor have higher integration and faster working speed. Therefore, the performance of the memory array and its peripheral circuits (decoder, charge pump, sense amplifier, etc.) largely determines the working conditions of the entire system, including speed and power consumption. [0003] The most important among various peripheral devices of the semiconductor memory is the sense amplifier ...

Claims

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Application Information

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IPC IPC(8): G11C11/419G11C7/00
Inventor 朱贺飞顾沧海周电周晓方
Owner FUDAN UNIV
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