12results about How to "Save power consumption" patented technology

The invention discloses a phase-locked loop circuit, a phase locking method and a frequency synthesizer, and the phase-locked loop circuit employs a phase rolling clock signal generation unit to carry out integer frequency division processing on a plurality of oscillation clock signals with uniformly-changed phases, obtains a plurality of feedback clock signals with uniformly-changed phases, and carries out frequency division processing on the feedback clock signals according to a preset clock period. The feedback clock signals with the corresponding phase sequence are selected from the multiple feedback clock signals with the uniformly-changed phases to be spliced, the phase rolling clock signal is generated, and the N-fractional frequency division phase-locked loop can be achieved, and compared with the mode that an SDM circuit is used for achieving the N-fractional frequency division phase-locked loop, the N-fractional frequency division phase-locked loop can be achieved more accurately. The occupied area and power consumption of the circuit are saved, and the performance of the phase-locked loop circuit is improved.

This invention provides a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances, and a ring voltage-controlled oscillator, comprising: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation transistor; the threshold voltage disturbance sensing module outputs differential voltage signals VP and VN reflecting the disturbance; the input terminals of the sensing signal processing module are respectively connected to the output terminals of a first constant current and a second constant current, and respectively receive VP and VN, for proportional subtraction amplification of VP and VN, and outputting an adaptive bias voltage; the control terminal of the branch current compensation transistor M8 is connected to VOUT, providing compensation current. This invention avoids phase noise degradation; reduces mass production costs; has a simple circuit architecture, achieves real-time adaptive calibration only through a pure analog path, and is suitable for precision frequency synthesis, RF and analog integrated circuits, and highly integrated electronic systems.

The application discloses an SNN hardware accelerator, belongs to the technical field of integrated circuits, and provides a hardware architecture for realizing an STDP+DFA algorithm, and realizes the calculation of each network layer of an SNN network based on a LIF neuron array; a plurality of activity counters corresponding to each neuron in the SNN network are arranged in the SNN hardware accelerator; the number of pulse firings of the corresponding neuron is recorded through the activity counter; when a network training request is received, the neuron with the number of pulse firings greater than a preset activity threshold is taken as an active neuron, the active neuron firing a pulse at a current time step t is taken as a neuron to be updated, and when the corresponding error signal is calculated, only the column vector under the column index corresponding to the neuron to be updated in the preset sparse matrix is multiplied by the corresponding error loss gradient vector, so that the SNN hardware accelerator with high precision can be realized with lower calculation resource consumption.

Embodiments of the present disclosure relate to a method of calibrating a clock signal and corresponding electronic device and system. A method comprising: providing a reference clock signal having a reference period; providing a sampling clock signal having a sampling clock period that is shorter than the reference period of the reference clock signal; measuring a first sub-period as a first ratio of the first sub-period to a period of the sampling clock signal; measuring a second sub-period as a second ratio of the second sub-period to the period of the sampling clock signal; detecting a start edge of a clock signal having a clock period that is greater than the reference period; generating a reconstructed reference signal based on the first ratio, the second ratio, and the detected start edge; comparing the clock period of the clock signal to a period of the reconstructed reference signal to obtain a difference signal indicative of a difference therebetween; and providing the difference signal to user circuitry for calibrating the clock signal.

This utility model relates to the field of concrete chute technology, specifically a movable bifurcated concrete pouring chute, including a chute body and a support body. The chute body consists of an upper chute, a middle chute, and a lower bifurcated chute connected in sequence. The support body includes a frame constructed of welded steel bars and movable wheels installed at the bottom of the frame. The chute body is fixedly installed on the support body through connectors. This utility model, through the design of the lower bifurcated chute, can simultaneously deliver a stream of concrete to three different working faces, realizing synchronous and continuous pouring on multiple working faces. It completely solves the problem of low efficiency caused by the frequent movement and alternating pouring of traditional single chutes or pump trucks. It is particularly suitable for large-volume concrete projects that require continuous one-time molding, greatly shortening the construction cycle.

The invention discloses an ADC time domain error background calibration method and system based on digital output statistics. The system comprises a digital signal monitoring module, a gain error calibration module and a hierarchical offset error calibration module. The front end and the rear end of the ADC are connected, and digital signals are monitored in real time, so that the digital signals output by the front end stage and the rear end stage are obtained; extracting a gain error direction of a voltage-time converter (VTC) and adjusting the gain error direction by using a similarity relationship between a saturation state of a rear-end ADC and front and rear-end MSBs; constructing a hierarchical imbalance calibration loop, and carrying out decoupling calibration on the inherent imbalance of the VTC and the imbalance of each path of the TDC; on the premise of no interruption and low overhead, simultaneous, real-time and high-robustness calibration is carried out on the gain error and the multi-source offset error; belongs to the technical field of mixed signal integrated circuits.

The application provides a terminal, a clock synchronization circuit, a system, a method and a storage medium. The clock synchronization circuit comprises: a crystal oscillator which is started to provide a first clock signal in a working state of the terminal; an RC oscillator which is started to provide a second clock signal different from the first clock signal in a sleep state of the terminal; a timer which is connected to the RC oscillator and is started to time based on the second clock signal in the sleep state of the terminal; the timing time reaches a preset time, the terminal is in the working state, the crystal oscillator is started, and the RC oscillator is kept started; a calibrator which is connected to the crystal oscillator and the RC oscillator, detects the first clock signal and the second clock signal in the working and sleep states, and judges whether a preset condition is met, and if not, calibrates the second clock signal based on the first clock signal; and a controller which is connected to and controls the crystal oscillator, the RC oscillator, the timer and the calibrator to start or stop and controls the terminal to switch between the working state and the sleep state, so that a trade-off among low cost, low power consumption and clock accuracy is realized.

The invention relates to the technical field of air dust removal, and discloses phosphorite mining underground air dust removal equipment which comprises a dust removal box, a top shell, a cloth bag dust removal mechanism, a cleaning mechanism and an ash removal period regulation and control system. The ash removal period regulation and control system is based on the inlet dust mass concentration, the treatment air volume, the pressure difference of the two sides of a filter bag, the gas humidity and dew point margin, the pressure drop recovery rate after last round of ash removal, the initial pressure difference base line after ash removal and the resistance recovery rate. And calculating a dust load impact coefficient, a dynamic resistance coefficient of the filter bag, an environment adaptability degree and a dust cleaning potential coefficient of the filter bag in real time, and dynamically determining a target dust cleaning period according to the parameters. According to the invention, the self-adaptive precise regulation and control of the dust removal period under the instantaneous change of dust load and high-humidity environment is realized, excessive dust removal or insufficient dust removal is effectively avoided, the dust removal efficiency is improved, the energy consumption is reduced, and the service life of the filter bag is prolonged.

This invention relates to the field of environmental protection and wastewater treatment technology, specifically disclosing a method for accelerating short-cut nitrification start-up through sludge pretreatment. The method includes: (1) pretreating activated sludge in a biological reactor for 1-20 days in the presence of low-ammonia-nitrogen water to obtain starved sludge; wherein the ammonia-nitrogen concentration of the low-ammonia-nitrogen water is 0-10 mg / L; and controlling the dissolved oxygen concentration of the pretreatment to 0-4 mg / L; (2) contacting the ammonia-nitrogen wastewater with the starved sludge for short-cut nitrification to obtain effluent. This invention provides a method for accelerating short-cut nitrification start-up through sludge pretreatment. By using starvation coupled with oxygen-limiting regulation, it can achieve rapid start-up and steady-state maintenance of short-cut nitrification, and has advantages such as high ammonia oxidation rate and high nitrite accumulation rate, maintaining the activity of ammonia-oxidizing bacteria (AOB) during short-cut nitrification.

The invention discloses a broadband radio frequency transceiving multifunctional chip covering a low frequency band and having an internal multi-module multiplexing structure, and belongs to the technical field of semiconductor radio frequency devices. A five-bit numerical control attenuator, four single-pole double-throw switches, a two-stage amplifier, a fixed attenuator, a biasing circuit and a TTL level driving circuit are integrated in the chip. Through a specific topological connection structure, hardware multiplexing of the first amplifier and the five-bit numerical control attenuator between a receiving channel and a transmitting channel is realized by using four single-pole double-throw switches, and the chip area and power consumption are remarkably reduced. The broadband coverage from a hundred MHz level low frequency to a ten GHz level high frequency is realized through a biasing circuit structure with multiple levels of inductors connected in series and RC grounded between the levels. A static working point adjusting port is led out from the chip, and power consumption and linearity can be flexibly configured through an external resistor. The invention has the advantages of high integration level, low power consumption, large bandwidth, strong universality and good index consistency, and is particularly suitable for multi-channel transmit-receive systems such as phased array radars and the like.

Embodiments of the present disclosure provide a decryption method, a variable storage method, and related devices, equipment, media and products. The decryption method monitors the current signal of the chip through the current probe, monitors the electromagnetic signal of the SRAM through the electromagnetic probe, determines the key bit value corresponding to the coordinate value stored in the SRAM based on the signal change mode of the current signal and the electromagnetic signal, and then obtains the decryption result. Through the current-electromagnetic dual-channel acquisition and analysis scheme, the ability to obtain effective information in the decryption process is improved, the redundant information processing process is reduced, and the password cracking efficiency is improved. The variable storage method stores the coordinate values of at least two coordinate dimensions of at least one password intermediate variable in at least two SRAMs, or stores the coordinate values of at least one coordinate dimension of at least two password intermediate variables in the same SRAM, which can avoid local electromagnetic radiation analysis and the storage process does not affect the execution efficiency of the encryption algorithm.

The application is suitable for the field of chip and digital circuit design, and provides a hardware circuit, method, equipment and medium for floating point matrix multiplication, wherein the hardware circuit comprises: a floating point multiplication unit, which is used for multiplying a first standard floating point format multiplier and a second standard floating point format multiplicand, and outputs a product in a first self-defined floating point format; a floating point accumulation unit, which is used for adding the product and an accumulation input value, and outputs an accumulation sum in a second self-defined floating point format; and a format conversion unit, which is used for converting the accumulation sum in the second self-defined floating point format into a third standard floating point format and then outputting. The scheme can balance between maintaining calculation accuracy and limiting hardware overhead.