Hardware circuit, method, device and medium for floating point matrix multiplication operation
By using a two-level precision design with a custom floating-point format, the problem of increased hardware resources and power consumption in floating-point matrix multiplication operations is solved, achieving a balance between computational precision and hardware overhead, and improving computational frequency and timing performance.
CN121070309BActive Publication Date: 2026-06-23GUANGDONG LEAPFIVE TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN Β· China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG LEAPFIVE TECH CO LTD
- Filing Date
- 2025-11-05
- Publication Date
- 2026-06-23
Smart Images
Figure CN121070309B_ABST
Abstract
The application is suitable for the field of chip and digital circuit design, and provides a hardware circuit, method, equipment and medium for floating point matrix multiplication, wherein the hardware circuit comprises: a floating point multiplication unit, which is used for multiplying a first standard floating point format multiplier and a second standard floating point format multiplicand, and outputs a product in a first self-defined floating point format; a floating point accumulation unit, which is used for adding the product and an accumulation input value, and outputs an accumulation sum in a second self-defined floating point format; and a format conversion unit, which is used for converting the accumulation sum in the second self-defined floating point format into a third standard floating point format and then outputting. The scheme can balance between maintaining calculation accuracy and limiting hardware overhead.
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
configurable floating point vector multiplication IP core based on an FPGA
CN109828744A