A ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbance and a ring voltage-controlled oscillator

Abstract

This invention provides a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances, and a ring voltage-controlled oscillator, comprising: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation transistor; the threshold voltage disturbance sensing module outputs differential voltage signals VP and VN reflecting the disturbance; the input terminals of the sensing signal processing module are respectively connected to the output terminals of a first constant current and a second constant current, and respectively receive VP and VN, for proportional subtraction amplification of VP and VN, and outputting an adaptive bias voltage; the control terminal of the branch current compensation transistor M8 is connected to VOUT, providing compensation current. This invention avoids phase noise degradation; reduces mass production costs; has a simple circuit architecture, achieves real-time adaptive calibration only through a pure analog path, and is suitable for precision frequency synthesis, RF and analog integrated circuits, and highly integrated electronic systems.

Description

Technical Field

[0001] This invention relates to the field of voltage-controlled oscillator technology, and in particular to a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances, and a ring voltage-controlled oscillator. Background Technology

[0002] Voltage-controlled oscillators (VCOs) are core functional units in radio frequency (RF) / analog integrated circuits, widely used in high-precision signal processing scenarios such as communications, radar, and precision measurement and control. Ring-type VCOs, relying on their topology without on-chip inductors and capacitors, offer significant advantages in terms of small chip footprint and strong CMOS process compatibility, making them highly adaptable and practical in portable, highly integrated precision RF / analog systems. However, during actual fabrication and operation, the MOS devices within the VCO are inevitably affected by a combination of factors, including manufacturing mismatches, doping fluctuations, gate oxide thickness deviations, and changes in the chip's operating environment (such as temperature), leading to significant disturbances in their threshold voltages. These disturbances directly alter the conduction characteristics and bias operating points of the MOS transistors, causing fluctuations in the output impedance of the oscillation unit. Ultimately, this significantly impacts the center output frequency of the ring-type VCO, causing it to deviate from the design target and severely restricting the system's frequency stability and chip yield.

[0003] The following techniques are currently available to reduce the impact of MOS threshold voltage disturbances on the center output frequency of a ring VCO:

[0004] (1) By increasing the tuning gain, the frequency coverage of the ring VCO can be broadened, thereby compatibility with the VCO oscillation center frequency shift caused by threshold voltage disturbances due to different MOS process angles and environmental factors. However, increasing the tuning gain will exacerbate the conversion of the inherent noise of the devices in the VCO into the phase noise of the output signal, directly deteriorating the phase noise performance of the VCO itself.

[0005] (2) By using off-chip excitation laser or fuse tuning technology, the bias resistor and current source parameters of the ring VCO are adjusted to initialize and calibrate the frequency offset introduced by the MOS threshold voltage disturbance. However, this method requires individual calibration of each chip after fabrication, which significantly increases the time cost in the mass production process; and it relies on dedicated high-precision equipment, which raises the manufacturing cost and greatly weakens the low-cost advantage of the ring VCO based on CMOS process, making it difficult to adapt to the needs of large-scale mass production.

[0006] (3) On-chip digital calibration technology is adopted. The center output frequency of the ring VCO is monitored in real time by a frequency detection unit. After the frequency deviation is obtained by digital logic circuit, the frequency shift caused by the MOS threshold voltage disturbance is calibrated by adjusting the configuration of the capacitor array or resistor network. However, this technology requires a high-precision frequency detection and digital calculation module, which significantly increases the complexity of the circuit. At the same time, the discrete calibration method cannot track the center frequency drift caused by the threshold voltage fluctuation caused by the coupling between the MOS and environmental factors in real time. Summary of the Invention

[0007] In view of this, the purpose of this invention is to provide a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances and a ring voltage-controlled oscillator. This invention does not require adjustment of VCO tuning gain, thus avoiding phase noise degradation; it does not require off-chip tuning equipment, thus reducing mass production costs; the circuit architecture is simple, and real-time adaptive calibration is achieved only through a pure analog path, making it suitable for precision frequency synthesis, RF and analog integrated circuits, and highly integrated electronic systems.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: a ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbance, comprising: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation transistor M8;

[0009] The threshold voltage disturbance sensing module is used to capture MOS threshold voltage disturbances and output differential voltage signals VP and VN that reflect the disturbances.

[0010] The threshold voltage disturbance sensing module includes a dual constant current source unit, a first diode-configured PMOS transistor M6, and a second diode-configured NMOS transistor M7. The dual constant current source unit provides a first constant current and a second constant current of equal magnitude. The source of the first diode-configured PMOS transistor M6 is connected to the power supply, and the drain of the first diode-configured PMOS transistor M6 is shorted to the gate and then connected to the output terminal of the first constant current; this connection point serves as VP. The source of the second diode-configured NMOS transistor M7 is grounded, and the drain of the second diode-configured NMOS transistor is shorted to the gate and then connected to the output terminal of the second constant current; this connection point serves as VN.

[0011] The input terminal of the sensing signal processing module is connected to the output terminal of the first constant current and the output terminal of the second constant current respectively, and receives VP and VN respectively. It is used to perform proportional subtraction amplification processing on VP and VN, and output an adaptive bias voltage VOUT.

[0012] The control terminal of the branch current compensation transistor M8 is connected to the output terminal of the sensing signal processing module to receive the adaptive bias voltage VOUT. The first terminal of the branch current compensation transistor M8 is connected to the power supply, and the second terminal of the branch current compensation transistor M8 is used to connect to the oscillation unit of the target ring voltage-controlled oscillator to provide compensation current.

[0013] In a preferred embodiment, the dual constant current source unit includes a reference constant current source, a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, and a third NMOS transistor M5;

[0014] The first end of the reference constant current source is connected to the power supply, and the second end of the reference constant current source is connected to the drain and gate of the first NMOS transistor M1; the source of the first NMOS transistor M1 is grounded; the gate of the second NMOS transistor M2 is connected to the gate of the first NMOS transistor M1, and the source of the second NMOS transistor M2 is grounded; the source of the first PMOS transistor M3 is connected to the power supply, and the gate and drain of the first PMOS transistor M3 are shorted and then connected to the drain of the second NMOS transistor M2;

[0015] The gate of the second PMOS transistor M4 is connected to the gate of the first PMOS transistor M3, and the source of the second PMOS transistor M4 is connected to the power supply. The gate and drain of the second diode-configured NMOS transistor M7 are shorted and then connected to the drain of the second PMOS transistor M4 as the output terminal of the second constant current. The gate of the third NMOS transistor M5 is connected to the gate of the second NMOS transistor M2, and the source of the third NMOS transistor M5 is grounded. The gate and drain of the first diode-configured PMOS transistor M6 are shorted and then connected to the drain of the third NMOS transistor M5 as the output terminal of the first constant current.

[0016] In a preferred embodiment, the sensing signal processing module includes: a first operational amplifier A1, a second operational amplifier A2, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, and a sixth resistor R6;

[0017] The two ends of the first resistor R1 are connected to the output terminal of the first constant current and the non-inverting input terminal of the first operational amplifier A1, respectively. The two ends of the second resistor R2 are connected to the output terminal of the second constant current and the inverting input terminal of the first operational amplifier A1, respectively. The two ends of the third resistor R3 are connected to the output terminal and the non-inverting input terminal of the first operational amplifier A1, respectively. The two ends of the fifth resistor R5 are connected to the output terminal of the first operational amplifier A1 and the non-inverting input terminal of the second operational amplifier A2, respectively. The two ends of the sixth resistor R6 are connected to the output terminal and the non-inverting input terminal of the second operational amplifier A2, respectively. The output terminal of the second operational amplifier A2 outputs an adaptive bias voltage VOUT.

[0018] In a preferred embodiment, the sensing signal processing module further includes a fourth resistor R4, a first reference bias voltage terminal VB1, and a second reference bias voltage terminal VB2; the first reference bias voltage terminal VB1 is connected to the inverting input terminal of the first operational amplifier A1 through the fourth resistor R4, and is used to provide a DC offset correction term for the proportional amplification; the second reference bias voltage terminal VB2 is connected to the inverting input terminal of the second operational amplifier A2, and is used to adjust the DC level of the final output.

[0019] In a preferred embodiment, the branch current compensation transistor M8 is a PMOS transistor, with its source connected to the power supply, its drain connected to the branch in the oscillation unit of the target ring voltage-controlled oscillator that determines the output impedance, and its gate connected to the output terminal of the second operational amplifier A2 to receive the adaptive bias voltage VOUT.

[0020] The present invention also provides a ring voltage-controlled oscillator, including the ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances.

[0021] This invention also provides a ring VCO bias adaptive calibration method for suppressing MOS threshold voltage disturbances. The method utilizes the aforementioned ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances and includes the following steps:

[0022] Step 1: Using the first diode configuration PMOS transistor M6 and the second diode configuration NMOS transistor M7 placed adjacent to the target oscillation unit, the MOS threshold voltage disturbance is sensed in real time and converted into a changing DC voltage signal;

[0023] Step 2: The changing DC voltage signal is proportionally amplified and the DC level is adjusted by the sensing signal processing module to generate an adaptive bias voltage VOUT that is adaptive to the current threshold voltage disturbance state.

[0024] Step 3: Apply the adaptive bias voltage VOUT to the control terminal of a branch current compensation transistor M8, and the branch current compensation transistor M8 generates a compensation current Icomp that is adaptive to the disturbance state.

[0025] Step 4: Inject the compensation current Icomp into the oscillation unit of the target ring voltage-controlled oscillator, dynamically adjust the output impedance of the oscillation unit, and thereby calibrate the center output frequency to the target range.

[0026] In a preferred embodiment, step 1 specifically includes:

[0027] The first diode-configured PMOS transistor M6 and the second diode-configured NMOS transistor M7 are respectively excited by constant current.

[0028] The VP of the excited terminal of the first diode-configured PMOS transistor M6 is collected as the first DC voltage signal, and the VN of the excited terminal of the second diode-configured NMOS transistor M7 is collected as the second DC voltage signal.

[0029] The difference between the first DC voltage signal and the second DC voltage signal changes monotonically with the disturbance of the threshold voltage of the PMOS and NMOS transistors.

[0030] In a preferred embodiment, step 2 employs a proportional subtraction amplification topology with a DC offset correction term to amplify the differential voltage signal characterizing the threshold voltage disturbance. The amplification factor and the DC offset correction value are set independently by adjusting the resistor ratio and the external reference bias voltage.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] (1) This invention relies on the inherent physical characteristics of the device to realize real-time sensing and dynamic calibration of MOS threshold voltage disturbance. Through the diode-configured MOS transistor and constant current source structure, the threshold voltage disturbance is converted into a detectable voltage signal. The sensed signal is processed and amplified by a proportional subtraction amplifier circuit to generate an adaptive bias voltage of the control branch current compensation transistor M8. The center frequency of the ring VCO is calibrated through current compensation. Figure 4 The experimental results show that the module can significantly reduce the impact of different threshold voltage disturbances on the center frequency of the ring VCO without changing the basic performance of the VCO. In 100 sets of test results, the standard deviation of the center output frequency distribution of the VCO after using the TVAC circuit is improved by 1267% compared with that before calibration, which greatly improves the working stability of the VCO.

[0033] (2) Compared with the prior art, the invention has many advantages. 1) Compared with the traditional scheme of increasing the tuning gain, the circuit can achieve adaptive calibration without adjusting the tuning gain parameter, avoiding the problem of deterioration of the phase noise of the ring VCO itself caused by the increase of the tuning gain; 2) Compared with laser / fuse tuning technology, the circuit has adaptive characteristics, does not require offline calibration of each chip, does not rely on dedicated high-precision equipment, and greatly reduces mass production time and equipment costs; 3) Compared with digital calibration technology, the circuit architecture is simple, has no additional module overhead, significantly saves chip area and power consumption, and can adaptively calibrate the continuous frequency offset caused by the process-environment coupling, improving product stability. Attached Figure Description

[0034] Figure 1 This is a block diagram of a VCO using a ring VCO bias adaptive calibration circuit (TVAC) technology to suppress MOS threshold voltage disturbances, according to a preferred embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the threshold voltage disturbance sensing module in a preferred embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of the sensing signal processing module in a preferred embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the VOUT output voltage distribution under random threshold voltage disturbance in a preferred embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram comparing the experimental results of the randomness of the center output frequency of the ring VCO before and after calibration using a TVAC circuit, which is a preferred embodiment of the present invention.

[0039] Figure 6 This is a schematic diagram comparing the phase noise performance of a TVAC circuit and a tuned gain-enhanced VCO, representing a preferred embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0041] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0042] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0043] A ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances, reference Figure 1-6 It includes: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation tube M8;

[0044] The threshold voltage disturbance sensing module is used to capture MOS threshold voltage disturbances and output differential voltage signals VP and VN that reflect the disturbances.

[0045] The threshold voltage disturbance sensing module includes a dual constant current source unit, a first diode-configured PMOS transistor M6, and a second diode-configured NMOS transistor M7. The dual constant current source unit provides a first constant current and a second constant current of equal magnitude. The source of the first diode-configured PMOS transistor M6 is connected to the power supply, and the drain of the first diode-configured PMOS transistor M6 is shorted to the gate and then connected to the output terminal of the first constant current; this connection point serves as VP. The source of the second diode-configured NMOS transistor M7 is grounded, and the drain of the second diode-configured PMOS transistor is shorted to the gate and then connected to the output terminal of the second constant current; this connection point serves as VN.

[0046] The input terminal of the sensing signal processing module is connected to the output terminal of the first constant current and the output terminal of the second constant current respectively, and receives VP and VN respectively. It is used to perform proportional subtraction amplification processing on VP and VN, and output an adaptive bias voltage VOUT.

[0047] The control terminal of the branch current compensation transistor M8 is connected to the output terminal of the sensing signal processing module to receive the adaptive bias voltage VOUT. The first terminal of the branch current compensation transistor M8 is connected to the power supply, and the second terminal of the branch current compensation transistor M8 is used to connect to the oscillation unit of the target ring voltage-controlled oscillator to provide compensation current.

[0048] refer to Figure 2 The dual constant current source unit includes a reference constant current source, a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, and a third NMOS transistor M5; the first NMOS transistor M1, the second NMOS transistor M2, and the first PMOS transistor M3 constitute a mirror current source bias network;

[0049] The first end of the reference constant current source is connected to the power supply, and the second end of the reference constant current source is connected to the drain and gate of the first NMOS transistor M1; the source of the first NMOS transistor M1 is grounded; the gate of the second NMOS transistor M2 is connected to the gate of the first NMOS transistor M1, and the source of the second NMOS transistor M2 is grounded; the source of the first PMOS transistor M3 is connected to the power supply, and the gate and drain of the first PMOS transistor M3 are shorted and then connected to the drain of the second NMOS transistor M2;

[0050] The gate of the second PMOS transistor M4 is connected to the gate of the first PMOS transistor M3, and the source of the second PMOS transistor M4 is connected to the power supply. The gate and drain of the second diode-configured NMOS transistor M7 are shorted and then connected to the drain of the second PMOS transistor M4 as the output terminal of the second constant current. The gate of the third NMOS transistor M5 is connected to the gate of the second NMOS transistor M2, and the source of the third NMOS transistor M5 is grounded. The gate and drain of the first diode-configured PMOS transistor M6 are shorted and then connected to the drain of the third NMOS transistor M5 as the output terminal of the first constant current.

[0051] refer to Figure 3 The sensing signal processing module includes: a first operational amplifier A1, a second operational amplifier A2, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, and a sixth resistor R6;

[0052] The two ends of the first resistor R1 are connected to the output terminal of the first constant current and the non-inverting input terminal of the first operational amplifier A1, respectively. The two ends of the second resistor R2 are connected to the output terminal of the second constant current and the inverting input terminal of the first operational amplifier A1, respectively. The two ends of the third resistor R3 are connected to the output terminal and the non-inverting input terminal of the first operational amplifier A1, respectively. The two ends of the fifth resistor R5 are connected to the output terminal of the first operational amplifier A1 and the non-inverting input terminal of the second operational amplifier A2, respectively. The two ends of the sixth resistor R6 are connected to the output terminal and the non-inverting input terminal of the second operational amplifier A2, respectively. The output terminal of the second operational amplifier A2 outputs an adaptive bias voltage VOUT.

[0053] The sensing signal processing module further includes a fourth resistor R4, a first reference bias voltage terminal VB1, and a second reference bias voltage terminal VB2. The first reference bias voltage terminal VB1 is connected to the inverting input terminal of the first operational amplifier A1 through the fourth resistor R4, and is used to provide a DC offset correction term for the proportional amplification. The second reference bias voltage terminal VB2 is connected to the inverting input terminal of the second operational amplifier A2, and is used to adjust the DC level of the final output.

[0054] The branch current compensation transistor M8 is a PMOS transistor. Its source is connected to the power supply, its drain is used to connect to the branch that determines the output impedance in the oscillation unit of the target ring voltage-controlled oscillator, and its gate is connected to the output terminal of the second operational amplifier A2 to receive the adaptive bias voltage VOUT.

[0055] The function of a ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances is to introduce a MOS threshold voltage disturbance calibration mechanism for the oscillator cell (VCO cell) in a ring voltage-controlled oscillator. This mechanism involves adding a current compensation stage outside the oscillator cell. This current compensation stage, controlled by a DC calibration voltage VOUT, generates a compensation current Icomp that adapts to the threshold voltage disturbance, thereby compensating for the oscillator cell. By dynamically adjusting the control voltage VOUT of the current compensation branch based on the threshold voltage disturbance, the output impedance of each oscillator cell can be maintained approximately constant, thus ensuring that the VCO's center output frequency remains stable within the design target range.

[0056] The TVAC circuit operates in three stages: threshold voltage disturbance sensing, sensing signal processing, and branch current compensation. First, in the threshold voltage disturbance sensing stage, a diode-configured MOSFET and constant current source structure convert the threshold voltage disturbance into a detectable voltage signal. Next, in the sensing signal processing stage, a proportional-to-subtractive amplifier circuit processes the sensing signal to generate a DC calibration voltage VOUT adapted to the current process disturbance. Finally, the branch current compensation stage, based on the obtained VOUT, controls the M8 transistor to generate a compensation current to compensate the VCO cell, thereby achieving adaptive calibration of the VCO oscillation unit and ultimately calibrating the VCO's center output frequency.

[0057] (1) Working principle of MOS threshold voltage disturbance sensing module

[0058] To ensure that the threshold voltage perturbations of the first diode-configured PMOS transistor M6 and the second diode-configured NMOS transistor M7 are similar to those of the target VCO, the first diode-configured PMOS transistor M6 and the second diode-configured NMOS transistor M7 should be placed as close as possible to the voltage-controlled oscillator (VCO) cell to be calibrated in the layout. When the MOS transistors placed near the target VCO generate threshold voltage perturbations, the MOS threshold voltage perturbation sensing module will activate.

[0059] The above principle is based on the example of a decrease in the threshold voltage of both NMOS and PMOS transistors to analyze the operation of the TVAC circuit. Here, we introduce two disturbance values: Δ|Vthp| and ΔVthn. When the threshold voltages of both NMOS and PMOS transistors decrease, both Δ|Vthp| and ΔVthn are negative. At this time, due to the decrease in the absolute value of the threshold voltage, the current flowing through the ring VCO oscillation unit increases, the output impedance decreases, and the center output frequency of the ring VCO will be higher than the typical design value, requiring calibration. The operating state of the threshold voltage disturbance sensing module at this time is as follows:

[0060] For the first diode configuration PMOS transistor M6: the absolute value of its threshold voltage |Vthp| decreases after the introduction of Δ|Vthp|, and the on-resistance decreases; while the bias current IM5 provided by the third NMOS transistor M5 remains constant, at which point VP satisfies:

[0061]

[0062] because As the voltage drops through the first diode configuration PMOS transistor M6, the voltage drop decreases, thus VP will increase accordingly; I M5 For the circuit through the third NMOS transistor M5, ron M6 The DC on-resistance of PMOS transistor M6 in diode configuration is given.

[0063] For the diode-configured NMOS transistor M7: its threshold voltage Vthn decreases after the introduction of ΔVthn, and the on-resistance also decreases; since the bias current provided by the second PMOS transistor M4 remains constant, according to Ohm's law, the node voltage VN generated by the current of the second PMOS transistor M4 flowing through the diode-configured NMOS transistor M7 will decrease accordingly. At this time, two voltages related to the threshold voltage fluctuation are obtained, thus completing the perception of the decrease in the threshold voltage of both the NMOS and PMOS transistors.

[0064] As described above, during threshold voltage sensing, the generation of the sensing signal relies solely on the threshold voltage characteristics of the MOS transistor placed near the target VCO cell. A dual constant current source structure directly converts the threshold voltage disturbance of the MOS transistor into a directly processable differential voltage signal. Real-time VCO calibration can be achieved without external calibration signals, high-precision detection equipment, or complex digital sampling circuits, offering the advantages of low cost and simple structure while enabling real-time tracking of process disturbances. Furthermore, compared to VCOs with increased tuning gain, this technology eliminates the need for center frequency drift caused by threshold voltage disturbances. Therefore, it avoids the need to increase the tuning gain of VCOs to expand frequency coverage and mitigate phase noise degradation caused by increased tuning gain.

[0065] (2) Working principle of the sensing signal processing module

[0066] After obtaining the output of the MOS threshold voltage disturbance sensing module, the sensing signal processing module processes the output voltages VP and VN of the threshold voltage disturbance sensing module. This module is divided into two stages based on the first operational amplifier A1 and the second operational amplifier A2. Here, the offset values ​​of the typical values ​​of the signal given by the threshold voltage sensing module are defined as ΔVP and ΔVN:

[0067] First, the operational amplifier network is analyzed. The first stage, dominated by the first operational amplifier A1, preprocesses the sensed signal. Based on the operational amplifier's "virtual short" (equal voltage at both input terminals) and "virtual open" (zero current at the input terminal) characteristics, we can obtain the following:

[0068]

[0069] (3)

[0070]

[0071] All parameters in the formula and Figure 3 Corresponding components: VP and VN are the output voltages of the MOS threshold voltage disturbance sensing module; VB1, V x1 V x2 for Figure 3 The voltage shown; 3. R1, R2, R3, and R4 are Figure 3 The resistor shown;

[0072] Combining equations (2) and (4), we can obtain:

[0073]

[0074] The second stage signal, dominated by the operational amplifier A2, mainly amplifies the pre-processed signal from the first stage and calibrates the output based on the values ​​of the first reference bias voltage terminal VB1 and the second reference bias voltage terminal VB2 to adapt to different processes. Based on the same "virtual short" and "virtual open" conditions, the final result after combining the two stages is shown in equation (6):

[0075]

[0076] Taking the difference between both sides of equation (6) simultaneously yields:

[0077]

[0078] Analyzing equations (6)-(7), the sensing signal processing module can provide a DC correction term for the output voltage VOUT based on the difference between VB1 and VB2. At the same time, it can adjust the first-order correction term of VOUT by dynamically adjusting the ratio of the sixth resistor R6 to the fifth resistor R5 to multiply the difference between ΔVP and ΔVN.

[0079] The above principle takes the simultaneous reduction of the threshold voltage of NMOS and PMOS as an example. Due to the introduction of ΔVthn and Δ|Vthp|, the value of ΔVP-ΔVN increases, and the value of VOUT will increase at this time.

[0080] As can be seen from the above signal processing and adaptive calibration process, this module uses a two-stage analog operational amplifier architecture to amplify the disturbance sensing signal and correct the DC level. The calibration intensity is flexibly adjusted by the resistor ratio and bias voltage. It can form a closed-loop real-time adjustment without digital sampling, clock control, external calibration equipment and complex logic circuits. From the circuit principle, it realizes accurate dynamic calibration of VCO bias. This is also the core reason why this invention can combine calibration accuracy, circuit simplicity and low application cost.

[0081] (3) Working principle of branch current calibration tube M8

[0082] For a ring voltage-controlled oscillator (VCO), its oscillation frequency is directly affected by the output impedance of the oscillation unit: the higher the output impedance, the lower the frequency; conversely, the lower the impedance, the higher the frequency. Threshold voltage disturbances cause changes in output impedance, resulting in frequency shift. To suppress this effect, the branch current compensation transistor M8 dynamically compensates for the current flowing through the VCO cell, keeping the VCO cell's output impedance constant, thereby calibrating the VCO's center output frequency. Specifically, the branch current compensation transistor M8 generates a compensation circuit Icomp adapted to the current threshold voltage disturbance based on the output signal VOUT of the sensing signal processing module. Icomp changes the branch current flowing through the VCO cell, compensating for the VCO cell's output impedance, and thus calibrating the VCO's center output frequency. Specifically, as... Figure 1 As shown, when the voltage signal VOUT generated by TVAC is applied to tube M8, the current through tube M8 connected to the VCO oscillation unit (VCO CELL) will change dynamically based on the value of VOUT. At this time, the current value of the core impedance branch in the VCO CELL will be dynamically calibrated to a stable value. At this time, the output impedance of the VCO is constant, and the influence of threshold voltage disturbance on the center output frequency will be reduced.

[0083] The above principle also uses the example of both PMOS and NMOS threshold voltages decreasing. When the threshold voltages of both PMOS and NMOS decrease, if not calibrated, the output impedance of the VCO will decrease due to the threshold voltage disturbance, thereby increasing the center output frequency of the VCO. When VOUT generated by the threshold voltage disturbance sensing module and the sensing signal processing module is applied to M8, as analyzed above, the value of VOUT generated by the sensing signal processing module will increase. At this point, according to... Figure 1It can be seen that as the gate voltage VOUT of transistor M8 increases, the gate-source voltage difference Vgs of transistor M8 will decrease. Here, let the compensation current through transistor M8 be Icomp. According to the saturation region MOSFET current formula:

[0084]

[0085] μ p The mobility of the PMOS transistor is a fixed process parameter; C ox The capacitance per unit area of ​​the gate oxide layer is given by fixed process parameters; W is the channel width of the MOSFET; and L is the channel length of the MOSFET.

[0086] It can be seen that when the value of Vgs decreases, the compensation current Icomp through the M8 transistor decreases. Here, Icomp is used to compensate for the output impedance of the VCO cell. It is assumed that without compensation, the drain current of the MOSFET that dominates the output impedance of the VCO cell is Id. After compensation, this value is Ideff, at which point:

[0087]

[0088] For the AC output impedance Rds of the saturation region MOSFET, we have:

[0089]

[0090] Where λ is a process constant, which does not change with external disturbances. Furthermore, differentiating both sides of the equation yields:

[0091]

[0092] According to Equation (11), when the threshold voltages of both PMOS and NMOS decrease, causing the center output frequency of VCO to rise, due to the introduction of ΔIdeff, the AC output impedance Rds of the dominant impedance MOS transistor increases after being superimposed with ΔRds, and the output impedance of VCO CELL increases accordingly, thereby reducing the center output frequency of VCO and finally calibrating it to the design target range, thus completing the adaptive bias calibration process.

[0093] Similarly, for the other three cases of NMOS and PMOS threshold voltage changes, the TVAC circuit operates as follows: When both NMOS and PMOS threshold voltages increase, the current through the VCO CELL decreases, the VCO CELL's output impedance increases, and the VCO's center output frequency decreases. At this time, in the TVAC circuit, since both ΔVthn and Δ|Vthp| are positive, the value of VOUT decreases, the compensation current of the branch current compensation transistor M8 increases, which reduces the VCO CELL's output impedance and thus increases the VCO's center output frequency, completing the calibration for this disturbance.

[0094] Regarding the threshold voltages of NMOS and PMOS, when one increases and the other decreases, the current value through the VCO CELL branch remains approximately constant due to the increasing and decreasing on-resistance of the PMOS and NMOS. In the TVAC circuit, since the introduced values ​​of ΔVthn and Δ|Vthp| are positive and negative respectively, the value of VOUT remains almost constant. The compensation current through the branch current compensation transistor M8 is also kept constant under the control of VOUT, thus keeping the output impedance of the VCO CELL constant and the center output frequency of the VCO constant.

[0095] Based on the above analysis, it can be concluded that the TVAC circuit can calibrate the VCO center output frequency for all four threshold voltage disturbance conditions.

[0096] Based on the working principles described in (1) to (3) above, it can be seen that the TVAC calibration process for the VCO does not require a digital calibration circuit or an off-chip calibration device. It can complete the real-time calibration of the center output frequency of the target VCO using only the signal generated by the TVAC circuit itself. This balances application cost and circuit complexity while being able to track process disturbances in real time. Furthermore, since the influence of threshold voltage disturbances on the center output frequency is reduced, the frequency coverage requirement of the VCO can be met without the need for tuning gain increase technology. This avoids the phase noise degradation problem caused by the increase in tuning gain. Therefore, the VCO using the TVAC circuit also has a phase noise advantage.

[0097] To verify the performance characteristics of the ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances under different MOS threshold voltage disturbance conditions, based on Figure 1 The circuit architecture shown was used to conduct 100 sets of random threshold voltage perturbation experiments on a VCO calibrated using a TVAC circuit. In the experiments, the threshold voltage perturbations of PMOS and NMOS were set to follow a Gaussian distribution. This is because in actual semiconductor manufacturing processes, random fluctuations in threshold voltage usually exhibit Gaussian distribution characteristics, and using a Gaussian distribution can more realistically simulate the actual working environment. Figure 4 The distribution curves of the output voltage VOUT generated by the TVAC circuit during 100 sets of experiments are presented. It can be seen that under random experimental conditions where the threshold voltage perturbation exhibits a Gaussian distribution, the TVAC circuit can dynamically calibrate according to different perturbation conditions.

[0098] Figure 5 The figure shows the distribution of the calibration voltage VOUT generated by the TVAC circuit under 100 sets of random threshold voltage perturbations. Figure 4 As shown in the figure, an uncalibrated VCO and a VCO calibrated with calibration voltage VOUT are compared. The experimental results comparing the center output frequencies of the two are as follows. Figure 5 As shown in the figure. The results indicate that the standard deviation of the center output frequency of the ring VCO was 127.47 MHz before calibration, while it dropped to 10.06 MHz after calibration. The difference is 1267%. The above experimental data shows that due to the compensation effect of the TVAC circuit on the VCO cell, the output impedance of the VCO cell remains at a constant value, enabling the TVAC circuit to calibrate the center output frequency of the ring VCO caused by the threshold voltage offset without the need for external devices and digital calibration circuits. The effect before and after calibration is significant.

[0099] Furthermore, to verify the phase noise performance advantage of the ring VCO based on the TVAC circuit of this invention compared to the traditional tuned gain-enhanced VCO, based on... Figure 1 The circuit architecture shown is used to compare the phase noise performance of the two VCO schemes. The results are as follows: Figure 6 As shown in the figure. Experimental results show that, at the same oscillation frequency, the phase noise performance of the ring VCO calibrated using this invention has an advantage of more than 2 dB across the entire frequency band compared to the VCO with increased tuning gain, while the phase noise improvement using existing calibration techniques is typically only about 0.5 to 1 dB. The above experiments fully verify that, due to the compensation effect of the TVAC circuit on the VCO cell, the output impedance of the VCO cell remains at a constant value, allowing the functional requirements of the VCO to be met without increasing the tuning gain. This advantage effectively avoids the phase noise degradation problem caused by increasing the tuning gain, significantly improving the overall RF performance of the VCO while ensuring frequency stability.

[0100] This invention (TVAC circuit) is an innovative optimization of the traditional MOS threshold voltage disturbance calibration circuit for ring voltage-controlled oscillators (VCOs). It generates an adaptive calibration voltage through a diode-configured MOS sensing unit and a proportional-to-subtractive amplifier module. This calibration voltage, in conjunction with the branch current compensation transistor M8, generates Icomp to calibrate the oscillator. This calibration process relies on the inherent threshold voltage characteristics of the device for real-time dynamic response, eliminating the need for additional frequency detection, digital computation, and sampling units. This avoids introducing additional noise and circuit delays, ensuring the VCO's phase noise performance. The TVAC eliminates traditional control signals and timing signals, such as... Figure 1 As shown, this circuit generates an output DC voltage signal VOUT internally through the TVAC. The DC voltage value of VOUT controls the compensation current of the M8 transistor, thereby compensating for the output impedance of the VCO cell and calibrating the center output frequency of the VCO. The Icomp generated by the TVAC circuit, together with the DC control signal VCTRL, controls the center output frequency FOUT of the VCO to ensure that the fluctuation of the VCO center output frequency FOUT is as small as possible under different threshold voltage disturbances and the same DC signal VCTRL. Figure 5 As shown, during the experiment, TVAC generates a corresponding DC output voltage VOUT by detecting perturbations in the threshold voltage, thereby ensuring that the VCO's center output frequency remains as consistent as possible. This invention utilizes standard CMOS process-compatible devices to construct the core circuit, eliminating the need for dedicated process technology and high-precision tuning equipment. Furthermore, as a universal MOS threshold voltage perturbation calibration module in integrated circuits, this invention is compatible with mainstream integrated circuit design platforms such as Cadence, Synopsys, and Mentor, and can be integrated with ring VCO circuits on various design platforms.

[0101] use:

[0102] This invention is an innovative approach to MOS threshold voltage perturbation calibration for ring-type VCOs, and it can be widely applied in precision frequency synthesis, RF / analog integrated circuits, and highly integrated electronic systems. This invention retains the advantages of ring-type VCOs, such as small chip area and high CMOS process compatibility, while optimizing the impact of MOS threshold voltage perturbation on the VCO center output frequency through dynamic calibration. Therefore, it can be used in electronic devices with stringent frequency stability requirements and sensitive process consistency, such as precision phase-locked loops (PLLs), RF transceivers, and frequency synthesizers. Specific applications include RF front-ends for 5G communication terminals, automotive radar systems, high-precision measurement and control instruments, portable medical electronic devices (RF modules for vital signs monitors), frequency generators for industrial control, and clock generation units for consumer electronics chips.

Claims

1. A ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances, characterized in that, include: Threshold voltage disturbance sensing module, sensing signal processing module, and branch current compensation tube M8; The threshold voltage disturbance sensing module is used to capture MOS threshold voltage disturbances and output differential voltage signals VP and VN that reflect the disturbances. The threshold voltage disturbance sensing module includes a dual constant current source unit, a first diode-configured PMOS transistor M6, and a second diode-configured NMOS transistor M7. The dual constant current source unit provides a first constant current and a second constant current of equal magnitude. The source of the first diode-configured PMOS transistor M6 is connected to the power supply, and the drain of the first diode-configured PMOS transistor M6 is shorted to the gate and then connected to the output terminal of the first constant current; this connection point serves as VP. The source of the second diode-configured NMOS transistor M7 is grounded, and the drain of the second diode-configured NMOS transistor is shorted to the gate and then connected to the output terminal of the second constant current; this connection point serves as VN. The input terminal of the sensing signal processing module is connected to the output terminal of the first constant current and the output terminal of the second constant current respectively, and receives VP and VN respectively. It is used to perform proportional subtraction amplification processing on VP and VN, and output an adaptive bias voltage VOUT. The control terminal of the branch current compensation transistor M8 is connected to the output terminal of the sensing signal processing module to receive the adaptive bias voltage VOUT. The first terminal of the branch current compensation transistor M8 is connected to the power supply, and the second terminal of the branch current compensation transistor M8 is used to connect to the oscillation unit of the target ring voltage-controlled oscillator to provide compensation current.

2. The ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbance according to claim 1, characterized in that, The dual constant current source unit includes a reference constant current source, a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, and a third NMOS transistor M5; The first terminal of the reference constant current source is connected to the power supply, and the second terminal of the reference constant current source is connected to the drain and gate of the first NMOS transistor M1; the source of the first NMOS transistor M1 is grounded. The gate of the second NMOS transistor M2 is connected to the gate of the first NMOS transistor M1, and the source of the second NMOS transistor M2 is grounded; the source of the first PMOS transistor M3 is connected to the power supply, and the gate and drain of the first PMOS transistor M3 are shorted and then connected to the drain of the second NMOS transistor M2. The gate of the second PMOS transistor M4 is connected to the gate of the first PMOS transistor M3, the source of the second PMOS transistor M4 is connected to the power supply, and the gate and drain of the second diode-configured NMOS transistor M7 are shorted and connected to the drain of the second PMOS transistor M4 as the output terminal of the second constant current. The gate of the third NMOS transistor M5 is connected to the gate of the second NMOS transistor M2, and the source of the third NMOS transistor M5 is grounded. The gate and drain of the first diode-configured PMOS transistor M6 are shorted and then connected to the drain of the third NMOS transistor M5 as the output terminal of the first constant current.

3. The ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbance according to claim 1, characterized in that, The sensing signal processing module includes: a first operational amplifier A1, a second operational amplifier A2, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, and a sixth resistor R6; The two ends of the first resistor R1 are connected to the output terminal of the first constant current and the non-inverting input terminal of the first operational amplifier A1, respectively. The two ends of the second resistor R2 are connected to the output terminal of the second constant current and the inverting input terminal of the first operational amplifier A1, respectively. The two ends of the third resistor R3 are connected to the output terminal and the non-inverting input terminal of the first operational amplifier A1, respectively. The two ends of the fifth resistor R5 are connected to the output terminal of the first operational amplifier A1 and the non-inverting input terminal of the second operational amplifier A2, respectively. The two ends of the sixth resistor R6 are connected to the output terminal and the non-inverting input terminal of the second operational amplifier A2, respectively. The output terminal of the second operational amplifier A2 outputs an adaptive bias voltage VOUT.

4. The ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbance according to claim 3, characterized in that, The sensing signal processing module further includes a fourth resistor R4, a first reference bias voltage terminal VB1, and a second reference bias voltage terminal VB2. The first reference bias voltage terminal VB1 is connected to the inverting input terminal of the first operational amplifier A1 through the fourth resistor R4, and is used to provide a DC offset correction term for the proportional amplification. The second reference bias voltage terminal VB2 is connected to the inverting input terminal of the second operational amplifier A2, and is used to adjust the DC level of the final output.

5. The ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbance according to claim 1, characterized in that, The branch current compensation transistor M8 is a PMOS transistor. Its source is connected to the power supply, its drain is used to connect to the branch that determines the output impedance in the oscillation unit of the target ring voltage-controlled oscillator, and its gate is connected to the output terminal of the second operational amplifier A2 to receive the adaptive bias voltage VOUT.

6. A ring voltage-controlled oscillator, characterized in that, Includes a ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances as described in any one of claims 1 to 5.

7. A ring VCO bias adaptive calibration method for suppressing MOS threshold voltage disturbances, comprising using a ring VCO bias adaptive calibration circuit for suppressing MOS threshold voltage disturbances as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: Using the first diode configuration PMOS transistor M6 and the second diode configuration NMOS transistor M7 placed adjacent to the target oscillation unit, the MOS threshold voltage disturbance is sensed in real time and converted into a changing DC voltage signal; Step 2: The changing DC voltage signal is proportionally amplified and the DC level is adjusted by the sensing signal processing module to generate an adaptive bias voltage VOUT that is adaptive to the current threshold voltage disturbance state. Step 3: Apply the adaptive bias voltage VOUT to the control terminal of a branch current compensation transistor M8, and the branch current compensation transistor M8 generates a compensation current Icomp that is adaptive to the disturbance state. Step 4: Inject the compensation current Icomp into the oscillation unit of the target ring voltage-controlled oscillator, dynamically adjust the output impedance of the oscillation unit, and thereby calibrate the center output frequency to the target range.

8. The ring VCO bias adaptive calibration method for suppressing MOS threshold voltage disturbance according to claim 7, characterized in that, Step 1 specifically includes: The first diode-configured PMOS transistor M6 and the second diode-configured NMOS transistor M7 are respectively excited by constant current. The VP of the excited terminal of the first diode-configured PMOS transistor M6 is collected as the first DC voltage signal, and the VN of the excited terminal of the second diode-configured NMOS transistor M7 is collected as the second DC voltage signal. The difference between the first DC voltage signal and the second DC voltage signal varies monotonically with the disturbance of the threshold voltage of the PMOS and NMOS transistors.

9. The ring VCO bias adaptive calibration method for suppressing MOS threshold voltage disturbance according to claim 7, characterized in that, In step 2, a proportional subtraction amplification topology with DC offset correction is used to amplify the differential voltage signal characterizing the threshold voltage disturbance. The amplification factor and DC offset correction value are set independently by adjusting the resistor ratio and the external reference bias voltage.

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