Goa driving unit, goa driving circuit and display device

Abstract

The application is suitable for the technical field of display, and provides a GOA driving unit, a GOA driving circuit and a display device. The GOA driving unit comprises: a pull-up control module, configured to output a high-level pull-up control signal to a pull-up control node according to a high-level first input signal; a pull-up module, configured to output a gate driving signal from an output node according to the pull-up control signal and a scan clock signal; a pull-down module, configured to pull down the pull-up control node to a low level according to a high-level second input signal; an inversion module, configured to invert the pull-up control signal according to the high-level first input signal and a preset high-level signal, and output an inverted signal of the pull-up control signal to a pull-down control node; a pull-down maintenance module, configured to maintain the pull-up control node and the output node at a low level according to the inverted signal; and a reset module, configured to pull down and reset the pull-up control node and the output node according to a reset signal, so as to improve the working stability of the GOA driving unit.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving unit, a GOA driving circuit and a display device. Background Technology

[0002] Integrating gate driver on array (GOA) circuitry onto a glass substrate involves integrating the gate driver circuitry of the display panel onto the glass substrate, forming a scanning drive for the display panel. Compared to traditional gate chip-based driving technologies, GOA driving technology can significantly reduce manufacturing costs and reduce the left and right bezels of the display panel. A GOA driving circuit typically includes cascaded multi-stage GOA driving units. Each stage of the GOA driving unit drives one row of pixel units on the display panel. By cascading multiple stages of GOA driving units, line-by-line scanning of the display panel can be achieved.

[0003] In existing GOA driver units, the output of the inverting module is entirely controlled by the pull-up control node. When the potential of the pull-up control node changes from low to high, the inverting module begins to convert its output pull-down control signal from high to low. However, if the pull-down control signal changes slowly, the transistor it controls may not turn off in time, continuously pulling the potential of the pull-up control node low. This makes it difficult to pull the pull-up control node high, preventing the GOA driver unit from completing its driving operation correctly and reducing its operational stability. Summary of the Invention

[0004] In view of this, embodiments of this application provide a GOA driving unit, a GOA driving circuit, and a display device to solve the technical problem of low working stability of existing GOA drivers.

[0005] In a first aspect, embodiments of this application provide a GOA driving unit, including:

[0006] A pull-up control module, connected to a pull-up control node, is used to output a pull-up control signal to the pull-up control node based on a first input signal;

[0007] A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the scan clock signal;

[0008] A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal;

[0009] An inverting module, connected to the pull-up control node and the pull-down control node, is used to invert the pull-up control signal according to the first input signal and a preset high-level signal, and output the inverted signal of the pull-up control signal to the pull-down control node;

[0010] A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal;

[0011] A reset module, connected to the pull-up control node and the output node, is used to pull down and reset the pull-up control node and the output node according to a high-level reset signal.

[0012] In one alternative implementation of the first aspect, the pull-up control module includes a first transistor;

[0013] The gate and source of the first transistor are used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.

[0014] In one alternative implementation of the first aspect, the pull-up module includes a second transistor and a first capacitor;

[0015] The gate of the second transistor and the first terminal of the first capacitor are both connected to the pull-up control node. The source of the second transistor is used to connect to the scan clock signal. The drain of the second transistor and the second terminal of the first capacitor are both connected to the output node.

[0016] In one alternative implementation of the first aspect, the pull-down module includes a third transistor;

[0017] The gate of the third transistor is used to receive the second input signal, the source of the third transistor is connected to the pull-up control node, and the drain of the third transistor is connected to the low-level terminal.

[0018] In one alternative implementation of the first aspect, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0019] The gate, source, and source of the fourth transistor are used to connect to a preset high-level signal. The drain of the fourth transistor and the source of the fifth transistor are connected to the gate of the sixth transistor. The gate of the fifth transistor is connected to the pull-up control node. The gate of the seventh transistor is used to connect to the first input signal. The drains of the fifth transistor and the seventh transistor are connected to a low-level terminal. The drain of the sixth transistor and the source of the seventh transistor are connected to the pull-down control node.

[0020] In one alternative implementation of the first aspect, the pull-down sustaining module includes an eighth transistor and a ninth transistor;

[0021] The gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-down control node. The source of the eighth transistor is connected to the pull-up control node. The source of the ninth transistor is connected to the output node. The drains of the eighth transistor and the drains of the ninth transistor are connected to a low-level terminal.

[0022] In one alternative implementation of the first aspect, the reset module includes a tenth transistor and an eleventh transistor;

[0023] The source of the tenth transistor is connected to the pull-up control node, the source of the eleventh transistor is connected to the output node, the gates of the tenth and eleventh transistors are used to receive the reset signal, and the drains of the tenth and eleventh transistors are connected to a low-level terminal.

[0024] In one alternative implementation of the first aspect, the first capacitor is a bootstrap capacitor.

[0025] Secondly, embodiments of this application provide a GOA driving circuit, including cascaded multi-stage GOA driving units as described in any optional implementation of the first aspect; the first input signal connected to each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, and the second input signal connected to each stage of the GOA driving unit is the gate driving signal output by the lower j-stage GOA driving unit; k and j are positive integers.

[0026] Thirdly, embodiments of this application provide a display device including the GOA driving circuit described in the second aspect.

[0027] Implementing the GOA driving unit, GOA driving circuit, and display device provided in the embodiments of this application has the following beneficial effects:

[0028] The GOA driving unit provided in this application synchronously inputs a high-level first input signal to the inverting module and the pull-up control module. This allows the pull-up control module to pull the pull-up control node to a high level while the inverting module quickly pulls the potential of the pull-down control node low. This effectively reduces the potential pull phenomenon between the pull-up control node and the pull-down control node, enabling the pull-up control node to be pulled up to a high level more quickly and reliably, thereby improving the working stability of the GOA driving unit. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application;

[0031] Figure 2 A waveform diagram of each signal accessed when a GOA driving unit is working normally, provided for an embodiment of this application;

[0032] Figure 3 A waveform diagram of each node / access signal in the GOA drive unit after the display device is powered off, provided as an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. Detailed Implementation

[0034] The following embodiments are only used to illustrate the technical solutions of this application more clearly, and are therefore only examples and should not be used to limit the scope of protection of this application.

[0035] In the description of the embodiments of this application, the technical terms "comprising," "including," "having," and any variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the description of the embodiments of this application, unless otherwise stated, the technical term "multiple" refers to two or more, and the technical terms "at least one" or "one or more" refer to one, two, or more than two. The technical terms "first," "second," etc., are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary / secondary relationship of the indicated technical features. The technical term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0036] This application first provides a GOA driving circuit, which may include cascaded multi-level GOA driving units. Each level of GOA driving unit can be used to drive a row of pixels on the display panel. The cascading of multiple levels of GOA driving units enables line-by-line scanning of the display panel.

[0037] This application also provides a GOA driving unit. Please refer to [link / reference]. Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application. Figure 1 As shown, in one optional implementation, the GOA driver unit may include a pull-up control module 10, a pull-up module 20, a pull-down module 30, an inverting module 40, a pull-down sustaining module 50, and a reset module 60. Wherein:

[0038] The pull-up control module 10 can be connected to the pull-up control node Qn. The pull-up control module 10 can be used to receive the first input signal G(nk) and output a high-level pull-up control signal to the pull-up control node Qn according to the high-level first input signal G(nk).

[0039] Pull-up module 20 can be connected to pull-up control node Qn. Pull-up module 20 can be used to receive scan clock signal CLK, and output gate drive signal G(n) from output node Rn according to pull-up control signal and scan clock signal. For example, pull-up control module 20 can output high-level gate drive signal G(n) from output node Rn according to high-level pull-up control signal and high-level scan clock signal. Gate drive signal G(n) can be used to drive a row of pixel units corresponding to the current GOA driving unit, or it can be used as an input signal for other GOA driving units.

[0040] The pull-down module 30 can be connected to the pull-up control node Qn. The pull-down module 30 can be used to receive a second input signal G(n+j) and, based on the second input signal G(n+j), pull the pull-up control node Qn down to a low level VSS. For example, the pull-down module 30 can pull the pull-up control node Qn down to a low level VSS based on the high-level second input signal G(n+j).

[0041] The inverting module 40 can be connected to the pull-up control node Qn and the pull-down control node Kn. The inverting module 40 can be used to receive the first input signal G(nk) and the preset high-level signal VGH, invert the pull-up control signal according to the high-level first input signal G(nk) and the preset high-level signal VGH, and output the corresponding inverted signal to the pull-down control node Kn.

[0042] The pull-down sustaining module 50 can be connected to the pull-up control node Qn, the pull-down control node Kn, and the output node Rn. The pull-down sustaining module 50 can be used to maintain the pull-up control node Qn and the output node Rn at a low level VSS based on an inverted signal. For example, the pull-down sustaining module 50 can maintain the pull-up control node Qn and the output node Rn at a low level VSS based on an inverted high signal.

[0043] The reset module 60 can be connected to the pull-up control node Qn and the output node Rn. The reset module 60 can be used to pull down the pull-up control node Qn and the output node Rn according to a reset signal. For example, the reset module 60 can pull down the pull-up control node Qn and the output node Rn to a low level VSS according to a high-level reset signal.

[0044] Wherein, the first input signal G(nk) can be the gate drive signal output by the k-th stage GOA drive unit, and the second input signal G(n+j) can be the gate drive signal output by the j-th stage GOA drive unit, where k and j are positive integers. k and j can be determined according to the number of cycles of the scan clock signal connected to the pull-up module 20.

[0045] Figure 2 This is a waveform diagram of various signals received by a GOA driving unit during operation, provided in an embodiment of this application. Figure 3 This diagram illustrates the voltage level changes of the pull-up and pull-down control nodes in the GOA driver unit. Figure 3 (a) in the diagram is a schematic diagram of the level changes of the pull-up control node and pull-down control node in the existing GOA driver unit. Figure 3 (b) is a schematic diagram of the level changes of the pull-up control node and the pull-down control node in a GOA driving unit provided in an embodiment of this application.

[0046] The following combination Figure 2and Figure 3 The working principle of the GOA driving unit will be explained.

[0047] like Figure 2 As shown, during stage A to B, the first input signal G(nk) is high, while the scan clock signal CLK and the second input signal G(n+j) are low. Based on this, as... Figure 3 As shown in (a) of this embodiment, the inverting module 40 can quickly pull down the pull-down control Kn to a low level according to the high-level first input signal G(nk), thereby enabling the pull-up control module 10 to quickly pull up the pull-up control node Qn to a first high level according to the high-level first input signal G(nk). Figure 3 As can be seen, by synchronously inputting the high-level first input signal G(nk) to the pull-up control module 10 and the inverting module 40, the time for the pull-up control node Qn to transition from low to high level can be significantly shortened in this embodiment. Furthermore, since the pull-up control node Qn is pulled up to the first high level and the scan clock signal CLK is low, the pull-up module 20 outputs a low-level signal to the output node Rn, making the output node Rn low. Because the second input signal G(n+j) is low, the pull-down module 30 is turned off.

[0048] During stages B to C, the scan clock signal CLK is high, and both the first input signal G(nk) and the second input signal G(n+j) are low. At this time, both the pull-up control module 10 and the pull-down module 30 are off. Due to the presence of the bootstrap capacitor in the pull-up module 20, the pull-up control node Qn is maintained at a second high level. This second high level is greater than the first high level. The inverting module 40 inverts the high-level pull-up control signal according to the preset high-level signal VGH and outputs a low-level inverted signal to the pull-down control node Kn, making Kn low. Since both the scan clock signal CLK and the pull-up control node Qn are high, the pull-up control module 20 outputs a high-level gate drive signal G(n) based on the high-level scan clock signal CLK and the pull-up control signal, making the output node Rn high.

[0049] During stages C to D, the scan clock signal CLK, the first input signal G(nk), and the second input signal G(n+j) are all at low levels. At this time, both the pull-up control module 10 and the pull-down module 30 are off, and the pull-up control node Qn remains at the first high level. The inverting module 40 inverts the high-level pull-up control signal according to the preset high-level signal VGH and outputs a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low. Since the pull-up control node Qn is high and the scan clock signal CLK is low, the pull-up control module 20 outputs a low-level signal to the output node Rn, making the output node Rn low.

[0050] During stages D to E, the second input signal G(n+j) is high, while the first input signal G(nk), the scan clock signal CLK, and the reset signal Reset are all low. At this time, the pull-down module 30 pulls the pull-up control node Qn low. Since both the pull-up control node Qn and the scan clock signal CLK are low, the pull-up module 20 outputs a low-level signal to the input node Rn, pulling the gate drive signal G(n) low. The inverting module 40 inverts the low-level pull-up control signal according to the preset high-level signal VGH and outputs a high-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn high.

[0051] During stages F to G, the reset signal Reset is high, while the first input signal G(nk), the second input signal G(n+j), and the scan clock signal CLK are all low. At this time, the reset module 60 pulls the pull-up control node Qn down to low and pulls the output node Rn down to low, keeping the gate drive signal G(n) low.

[0052] As can be seen from the above, by synchronously inputting a high-level first input signal to the inverting module and the pull-up control module, the inverting module can quickly pull the potential of the pull-down control node down while the pull-up control module starts to pull the pull-up control node to a high level. This effectively reduces the potential pull phenomenon between the pull-up control node and the pull-down control node, allowing the pull-up control node to be pulled up to a high level more quickly and reliably, thereby improving the working stability of the GOA driver unit.

[0053] Please see Figure 4 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below:

[0054] like Figure 4As shown, the pull-up control module 10 may include a first transistor T1. The gate and source of the first transistor T1 can be used to connect to the first input signal G(nk), and the drain of the first transistor T1 can be connected to the pull-up control node Qn.

[0055] The pull-up module 20 may include a second transistor T2 and a first capacitor C1. The gate of the second transistor T2 may be connected to the pull-up control node Qn along with the first terminal of the first capacitor C1. The source of the second transistor T2 may be used to connect to the scan clock signal CLK, and the drain of the second transistor T2 may be connected to the output node Rn along with the second terminal of the first capacitor C1. For example, the first capacitor C1 may be a bootstrap capacitor.

[0056] The pull-down module 30 may include a third transistor T3. The gate of the third transistor T3 can be used to connect to the second input signal G(n+j), the source of the third transistor T3 can be connected to the pull-up control node Qn, and the drain of the third transistor T3 can be connected to a low-level terminal. The low-level terminal is used to provide a low level VSS.

[0057] The inverting module 40 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate and source of the fourth transistor T4 and the source of the sixth transistor T6 can be connected to a preset high-level signal VGH. The drain of the fourth transistor T4 and the source of the fifth transistor T5 can be connected to the gate of the sixth transistor T6. The gate of the fifth transistor T5 can be connected to the pull-up control node Qn. The gate of the seventh transistor T7 can be connected to the first input signal G(nk). The drains of the fifth transistor T5 and the seventh transistor T7 can be connected to a low-level terminal. The drain of the sixth transistor T6 and the source of the seventh transistor T7 can be connected to the pull-down control node Kn.

[0058] The pull-down sustaining module 50 may include an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 and the gate of the ninth transistor T9 may be connected to the pull-down control node Kn, the source of the eighth transistor T8 may be connected to the pull-up control node Qn, the source of the ninth transistor T9 may be connected to the output node Rn, and the drain of the eighth transistor T8 and the drain of the ninth transistor T9 may be connected to a low-level terminal.

[0059] The reset module 60 may include a tenth transistor T10 and an eleventh transistor T11. The source of the tenth transistor T10 may be connected to the pull-up control node Qn, and the source of the eleventh transistor T11 may be connected to the output node Rn. The gates of the tenth transistor T10 and the eleventh transistor T11 may be used to receive the reset signal Reset, and the drains of the tenth transistor T10 and the eleventh transistor T11 may be connected to a low-level terminal.

[0060] The following combination Figure 2 and Figure 3 The working principle of the GOA driving unit will be further explained.

[0061] During phase A to B, the first input signal G(nk) is high, while the scan clock signal CLK, the second input signal G(n+j), and the reset signal Reset are all low. At this time, the seventh transistor T7 in the inverter module 40 and the first transistor T1 in the pull-up control module 10 are synchronously turned on, thereby quickly pulling down the pull-down control node Kn to a low level, thus enabling the pull-up control node Qn to be pulled up to the first high level. According to... Figure 3 As can be seen, by synchronously inputting the high-level first input signal G(nk) to the pull-up control module 10 and the inverting module 40, the time for the pull-up control node Qn to transition from low to high level can be significantly shortened in this embodiment. Furthermore, since the pull-up control node Qn is pulled up to the first high level and the scan clock signal CLK is low, the second transistor T2 in the pull-up module 20 is turned on, and the pull-up module 20 outputs a low-level signal to the output node Rn, making the output node Rn low. Since the second input signal G(n+j) is low, the third transistor T3 in the pull-down module 30 is turned off, thereby turning off the pull-down module 30.

[0062] During stages B to C, the scan clock signal CLK is high, and both the first input signal G(nk) and the second input signal G(n+j) are low. At this time, the first transistor T1 in the pull-up control module 10 is off, thus turning off the pull-up control module 10. The third transistor T3 in the pull-down module 30 is off, thus turning off the pull-down module 30. Due to the presence of the bootstrap capacitor in the pull-up module 20, the pull-up control node Qn is maintained at a second high level, which is greater than the first high level. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the inverter module 40 are on, and the seventh transistor T7 is off, enabling the inverter module 40 to output a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low. Since both the scan clock signal CLK and the pull-up control node Qn are high, the second transistor T2 in the pull-up control module 20 is on, outputting a high-level gate drive signal G(n), making the output node Rn high.

[0063] During stages C to D, the scan clock signal CLK, the first input signal G(nk), and the second input signal G(n+j) are all at low levels. Since the first input signal G(nk) is low, the first transistor T1 in the pull-up control module 10 is off, thus turning off the pull-up control module 10. The third transistor T3 in the pull-down module 30 is off, thus turning off the pull-down module 30, and the pull-up control node Qn remains at a high level. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the inverter module 40 are on, and the seventh transistor T7 is off, enabling the inverter module 40 to output a low-level inverted signal to the pull-down control node Kn, making the pull-down control node Kn low. Since the pull-up control node Qn is high and the scan clock signal CLK is low, the second transistor T2 in the pull-up module 20 is on, outputting a low-level signal to the output node Rn, making the output node Rn low.

[0064] During stages D to E, the second input signal G(n+j) is high, while the first input signal G(nk), the scan clock signal CLK, and the reset signal Reset are all low. At this time, the third transistor in pull-down module 30 is on, pulling the pull-up control node Qn low. Since both the pull-up control node Qn and the scan clock signal CLK are low, the second transistor T2 in pull-up module 20 is off, and pull-up module 20 outputs a low-level signal to input node Rn, pulling the gate drive signal G(n) low. The fourth transistor T4 and the sixth transistor T6 in inverter module 40 are on, while the fifth transistor T5 and the seventh transistor T7 are off, enabling inverter module 40 to output a high-level inverted signal to pull-down control node Kn, making pull-down control node Kn high.

[0065] During stages F to G, the reset signal Reset is high, while the first input signal G(nk), the second input signal G(n+j), and the scan clock signal CLK are all low. At this time, the tenth transistor T10 and the eleventh transistor T11 in the reset module 60 are both turned on, thereby pulling the pull-up control node Qn down to a low level and pulling the output node Rn down to a low level.

[0066] This application also provides a display device, which includes the above-described GOA driving circuit.

[0067] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the GOA driver circuit can be divided into different functional units to complete all or part of the functions described above. Furthermore, the specific names of each functional unit are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.

[0069] It should be noted that, unless otherwise specified, all technical terms used in the embodiments of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The technical terms used in the embodiments of this application are only used to explain specific embodiments of this application and are not intended to limit this application.

[0070] The term "embodiment" as used in the description of embodiments in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0071] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0072] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A GOA driving unit, characterized in that, include: A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal; A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the scan clock signal; A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal; An inverting module, connected to the pull-up control node and the pull-down control node, is used to invert the pull-up control signal according to the first high-level input signal and a preset high-level signal, and output the inverted signal of the pull-up control signal to the pull-down control node; A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal; A reset module, connected to the pull-up control node and the output node, is used to pull down and reset the pull-up control node and the output node according to a high-level reset signal.

2. The GOA driving unit according to claim 1, characterized in that, The pull-up control module includes a first transistor; The gate and source of the first transistor are used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.

3. The GOA driving unit according to claim 1, characterized in that, The pull-up module includes a second transistor and a first capacitor; The gate of the second transistor and the first terminal of the first capacitor are both connected to the pull-up control node. The source of the second transistor is used to connect to the scan clock signal. The drain of the second transistor and the second terminal of the first capacitor are both connected to the output node.

4. The GOA driving unit according to claim 1, characterized in that, The pull-down module includes a third transistor; The gate of the third transistor is used to receive the second input signal, the source of the third transistor is connected to the pull-up control node, and the drain of the third transistor is connected to the low-level terminal.

5. The GOA driving unit according to claim 1, characterized in that, The inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate, source, and source of the fourth transistor are used to connect to a preset high-level signal. The drain of the fourth transistor and the source of the fifth transistor are connected to the gate of the sixth transistor. The gate of the fifth transistor is connected to the pull-up control node. The gate of the seventh transistor is used to connect to the first input signal. The drains of the fifth transistor and the seventh transistor are connected to a low-level terminal. The drain of the sixth transistor and the source of the seventh transistor are connected to the pull-down control node.

6. The GOA driving unit according to claim 1, characterized in that, The pull-down sustaining module includes an eighth transistor and a ninth transistor; The gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-down control node. The source of the eighth transistor is connected to the pull-up control node. The source of the ninth transistor is connected to the output node. The drains of the eighth transistor and the drains of the ninth transistor are connected to a low-level terminal.

7. The GOA driving unit according to claim 1, characterized in that, The reset module includes a tenth transistor and an eleventh transistor; The source of the tenth transistor is connected to the pull-up control node, the source of the eleventh transistor is connected to the output node, the gates of the tenth and eleventh transistors are used to receive the reset signal, and the drains of the tenth and eleventh transistors are connected to a low-level terminal.

8. The GOA driving unit according to claim 3, characterized in that, The first capacitor is a bootstrap capacitor.

9. A GOA driving circuit, characterized in that, The system includes cascaded multi-stage GOA driving units as described in any one of claims 1-8; the first input signal of each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, and the second input signal of each stage of the GOA driving unit is the gate driving signal output by the lower j-stage GOA driving unit; k and j are positive integers.

10. A display device, characterized in that, Includes the GOA driving circuit as described in claim 9.

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