Method of calibrating a clock signal and corresponding electronic device and system
By employing high-speed clock signal sampling and synchronization error self-compensation in microcontrollers and integrated circuits, the problem of insufficient clock signal accuracy is solved, improving the synchronization and communication security of the device, while reducing cost and complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STMICROELECTRONICS SRL
- Filing Date
- 2023-03-10
- Publication Date
- 2026-06-26
AI Technical Summary
In existing technologies, microcontrollers and integrated circuits suffer from insufficient precision and accuracy in calibrating clock signals, which particularly affects device tracking and communication security in IoT environments.
By sampling a reference clock using a high-speed clock signal and aligning it with the clock signal to be calibrated, and utilizing a synchronization error self-compensation method, the clock signal can be calibrated periodically or in an event-triggered manner, thereby reducing silicon area and power consumption.
It achieves high-precision calibration of clock signals, improves device synchronization and communication security, and reduces cost and complexity.
Smart Images
Figure CN116736934B_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims the benefit of Italian patent application number 102022000004736, filed on March 11, 2022, which is incorporated herein by reference. Technical Field
[0003] This description relates to, for example, a method for calibrating clock signals in a system-on-a-chip (SoC). One or more embodiments can be applied to integrated circuits (ICs) and / or electronic devices in various environments, such as microcontrollers (MCUs) used in Internet of Things (IoT) applications. Background Technology
[0004] Microcontrollers and other ICs use various clock signals to synchronize their internal operations.
[0005] Depending on the application, these circuits can benefit from the process of calibrating clock signals to provide certain functionalities involving high signal precision and accuracy.
[0006] For example, in IoT environments involving multiple small and low-cost electronic devices, calibrated clock signals facilitate device tracking and secure communication between devices.
[0007] Therefore, an improved method for calibrating the clock signal is needed. Summary of the Invention
[0008] The purpose of one or more embodiments is to contribute to providing solutions that offer such improvements.
[0009] According to one or more embodiments, this objective can be achieved by a method having the features set forth in the appended claims.
[0010] For example, one or more embodiments may relate to a corresponding device (such as an integrated circuit).
[0011] One or more embodiments may relate to a corresponding system-on-a-chip (SoC).
[0012] The claims are an integral part of the technical teachings provided herein with reference to the embodiments.
[0013] One or more embodiments involve calibrating a clock signal by providing a high-speed clock, sampling a reference clock using the high-speed clock, and aligning the reference clock with the clock signal to be calibrated.
[0014] In one or more embodiments, synchronization errors can be conveniently self-compensated.
[0015] One or more embodiments can interface with various types of standard or custom buses.
[0016] In one or more embodiments, clock calibration may be performed periodically or triggered by a specific event (e.g., such as the detection of a hacking attempt).
[0017] One or more embodiments can, for example, facilitate a reduction in cost and complexity by saving silicon area and power consumption. Attached Figure Description
[0018] One or more embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:
[0019] Figure 1 This is an example diagram of a clock calibration circuit based on this disclosure;
[0020] Figure 2 It is a timing diagram of signals that can be used in one or more embodiments;
[0021] Figure 3 It is another timing diagram of signals that can be used in one or more embodiments;
[0022] Figure 4 These are example diagrams of the device based on this disclosure; and
[0023] Figure 5 This is an example diagram of a system-on-a-chip based on this disclosure.
[0024] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to the corresponding parts.
[0025] The accompanying drawings are provided to clearly illustrate relevant aspects of the embodiments, and the drawings are not necessarily drawn to scale.
[0026] The edges of features drawn in the figure do not necessarily indicate the end of the feature range. Detailed Implementation
[0027] In the following description, one or more specific details are illustrated to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details, or through other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been illustrated or described in detail so that certain aspects of the embodiments will not be obscured.
[0028] References to “embodiment” or “one embodiment” within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear at one or more points in this specification do not necessarily refer to one embodiment or the same embodiment.
[0029] Furthermore, in one or more embodiments, a particular construction, structure, or characteristic may be combined in any suitable manner.
[0030] The accompanying diagram is a simplified version and is not drawn to scale.
[0031] Throughout the accompanying figures, similar parts or elements are indicated by similar reference numerals / numbers unless the context otherwise requires, and for the sake of brevity, the corresponding descriptions for each figure will not be repeated.
[0032] The reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of embodiments.
[0033] For simplicity, the same reference numerals may be used in the following detailed description to indicate nodes / lines in the circuit and signals that may appear at those nodes or lines.
[0034] like Figure 1 As illustrated, the clock calibration circuit 10 includes:
[0035] The clock input node CK0 is configured to provide the clock signal to be calibrated.
[0036] The reference clock signal REF is provided, for example, by an integrated time base oscillator circuit in a manner known per se;
[0037] Sampling circuit block 12 is coupled to reference input node REF to receive reference clock signal REF from reference input node REF. Sampling circuit block 12 is configured to receive sampling signal HSCK and thereby sample reference clock signal REF to obtain at least one clock parameter M, N of reference clock signal REF, such as the high phase length N and low phase length M of reference clock REF measured in units of the period of sampling signal HSCK, or their sum (e.g. N+M).
[0038] Reconstruction circuit block 14 is coupled to sampling circuit block 12 to receive clock parameters M and N from sampling circuit block 12, and is coupled to synchronization circuit 16 via data storage circuit block 17 to receive start signal START from synchronization circuit 16. Reconstruction circuit block 14 is configured to reconstruct clock signal CKR using at least one clock parameter N and M. Clock signal CKR has the same period as reference clock REF, which has a clock edge aligned with the clock edge of sampled clock signal CKS, as discussed below.
[0039] Synchronization circuit block 16 is coupled to clock input node CK0 and configured to receive sampling signal HSCK. Synchronization circuit block 16 is configured to sample the input clock signal CK0 thereby obtaining a sampled clock signal CKS to be provided to reconstruction circuit block 14.
[0040] Data storage circuit block 17 (e.g., a flip-flop) is coupled to synchronization circuit block 16 to receive a sampled clock signal CKS as a clock, thereby temporating data storage circuit block 17 to release the start signal START, and
[0041] Comparator circuit block 18 (e.g., a frequency counter known per se) is configured to receive a reconstructed clock signal CKR and a sampled clock signal CKS (in phase between them). The comparator circuit block 18 is configured to perform a comparison of the clock periods of the clock signal and the reconstructed reference signal, and as a result of the comparison, obtain a differential (e.g., error) signal CKN indicating the difference between them.
[0042] For example, an error signal CKN is provided to a user circuit device U (e.g., a set of various peripheral devices), which is configured to compensate the clock signal based on the differential signal CKN in a manner known per se (e.g., direct or indirect frequency compensation). Therefore, for the sake of brevity, the corresponding description will not be repeated.
[0043] For simplicity, the following mainly concerns reference periods T that are shorter than half-cycle T0 / 2 of the clock signal CK0 to be calibrated. REF The reference clock signal (which is the reciprocal of the frequency) is discussed in connection with one or more embodiments to facilitate a faster calibration process. Such an example of the reference period is purely exemplary and is by no means limiting; for example, in one or more embodiments, the reference period may also be equal to or longer than half a period T0 / 2 of the clock signal CK0 to be calibrated.
[0044] like Figure 2 As illustrated, the sampled signal HSCK has a period T that is longer than that of the reference signal REF. REFA much shorter sampling period T (corresponding to a higher frequency) HSCK For example, the frequency of the sampled signal HSCK is a multiple of the frequency of the reference signal REF (e.g., at least twice, preferably at least ten times, in order to reduce errors).
[0045] like Figure 2 As illustrated, the provided sampled signal HSCK has a reduced quality (e.g., accuracy) relative to the reference signal REF. For example, the sampled signal HSCK may have a duty cycle slightly different from 50%.
[0046] like Figure 1 As illustrated, sampling circuit block 12 measures the high and low phases of the reference clock CK at any period, obtaining the phases of the reference clock CK during period T. REF The clock period T of the sampled signal HSCK within HSCK The quantities N and M.
[0047] For example, these clock parameters N and M can be expressed as:
[0048] N = T REF,H / T HSCK
[0049] M = T REF,L / T HSCK
[0050] in
[0051] T REF,H It is the duration of the time interval in which the reference clock signal has its first (e.g., high) logic value, and
[0052] T REF,L It is the duration of the time interval in which the reference clock signal has a second (e.g., low) logic value.
[0053] For example, such as Figure 2 As illustrated in the example scenario where the signal changes over time, sampling circuit block 12 measures the period T of the sampled signal HCSK. HCSK The reference period T included in the reference signal REF REF The number of times in the sequence, for example, N=2, M=2.
[0054] like Figure 1 and 3 Examples in:
[0055] Synchronization circuit block 16 generates a synchronization clock signal CKS that is synchronized with the sampling signal HSCK, and
[0056] The reconstruction circuit block 14 generates a reconstruction clock signal CKR that is synchronized with the sampling signal HSCK, based on clock parameters N and M and triggered by the start signal START provided via flip-flop 17 (e.g., via a programmable oscillator circuit in a manner known per se).
[0057] like Figure 3 As illustrated, since the two signals CKS and CKR are synchronized on the HSCK clock, the synchronization error is automatically compensated.
[0058] As used in this article, a "synchronous clock signal" refers to a clock signal that has a rising (or falling) edge at the beginning of a time interval, such as... Figure 3 As illustrated in the example, it is determined to start from the start signal START.
[0059] like Figure 1 As illustrated, signals CKS and CKR are provided to comparator circuit block 18 (known per se), which is configured to generate error signal CKN, for example, which is then provided to user circuit device U to thereby calibrate (in a manner known per se) clock signal CK0.
[0060] like Figures 1 to 3 As illustrated in the example, one method includes:
[0061] Provides a reference period T REF The reference clock signal REF, which is in the first sub-period T of the reference period. REF,H During this period, it has a first logic value, and in the second sub-period T of the reference period. REF,L The period has a second logical value;
[0062] Provides a sampling clock period T HSCK The sampling clock signal HSCK, where the sampling clock period (T) HSCK It has a shorter reference period than the reference clock signal;
[0063] The first sub-period is measured as 12, which is the first sub-period T. REF,H The first ratio N to the period of the sampling clock signal HSCK;
[0064] The second sub-period is measured as the second sub-period T. REF,L The second ratio M to the period of the sampling clock signal;
[0065] Detect the start edge START of clock signal CK0, which has a clock period T0 larger than the reference period.
[0066] A 14-reconstruction reference signal CKR is generated based on the first ratio, the second ratio, and the detected start edge;
[0067] The clock period T0 of the execution clock signal is compared with the period of the reconstructed reference signal 18, and a differential signal CKN indicating the difference between them is obtained as a result of the comparison.
[0068] The differential signal is provided to a user circuit device U that is configured to calibrate a clock signal based on the differential signal.
[0069] For example, the reconstructed reference signal CKR has a reconstruction period equal to the reference period and is synchronized with the detected start edge.
[0070] like Figures 1 to 3 As illustrated in the example, the method includes:
[0071] The clock signal is sampled 16 times via the sampling clock signal to obtain the sampled clock signal CKS, wherein the sampled clock signal and the reconstructed reference signal have corresponding clock edges that are synchronized at the same time.
[0072] A comparison 18 is made between the clock period of the execution clock signal and the period of the reconstructed reference signal, and a differential signal CKN indicating the difference between them is obtained as a result of the comparison.
[0073] The differential signal is provided to a user circuit device configured to calibrate a clock signal based on the differential signal.
[0074] like Figures 1 to 3 As illustrated, the method includes setting the time interval length START_CAL_INT, and repeating 45 comparisons 18 after the set time interval has elapsed.
[0075] For example, the clock period of a clock signal is affected by at least one physical quantity.
[0076] like Figures 1 to 3 As illustrated in the example, the method includes:
[0077] Receive a set of sensing signals TS, VS, TTS indicating at least one physical quantity affecting the clock signal, and
[0078] The 42START_CAL_sel comparison is triggered in response to a sense signal indicating a physical quantity that affects the clock cycle.
[0079] For example, the method includes enabling 48 to perform a comparison in response to receiving at least one enable calibration signal START_CAL_int, START_CAL_sel, START_CAL.
[0080] like Figure 4 As illustrated, circuit 10 can be embedded in electronic device 40, such as a clock reconstruction peripheral.
[0081] like Figure 4 As illustrated, circuit 10 can be connected to any standard or custom bus architecture (such as AHB, APB, OBI, which are known in themselves).
[0082] like Figure 4 As illustrated, the circuit 10 can be triggered to periodically or in response to certain significant events that can be detected via trigger signals TS, VS, TTS to calibrate the clock signal CK0. For example, the trigger signals can indicate battery level, temperature changes, device reset, hacking attempt detection, and can be provided by dedicated sensors (e.g., voltage detector VS, temperature sensor TS, tamper sensor TTS) in a manner known per se.
[0083] like Figure 4 As illustrated, device 40 includes:
[0084] The start input node START_CAL is configured to receive a start signal to force the start of the calibration process of circuit 10.
[0085] The bus node BUS is configured to couple to any standard or custom bus architecture to provide it with the calibration clock signal CKN.
[0086] The calibration trigger circuit block 42 is configured to be coupled to a set of sensors TS, VS, and TTS to receive sensing signals VS, TS, and TTS indicating faults or abnormal conditions. The calibration trigger circuit block 42 generates a calibration trigger signal START_CAL_sel based on the received sensing signals VS, TS, and TTS.
[0087] Bus interface 44 is coupled to bus node BUS to transfer data to / from it, such as standard interfaces known in themselves (e.g., AHB, APB, OBI, AXI, etc.).
[0088] (Optional) Timer 45 can be configured to periodically generate a trigger signal START_CAL_INT to ignite circuit 10.
[0089] A logic "OR" port, coupled to the start node START, coupled to the calibration trigger circuit block 42, and optionally coupled to the timer 45, receives from it the corresponding trigger signals START_CAL, START_CAL_sel, and START_CAL_INT. This logic "OR" is coupled to circuit 10 to provide it with an OR'd trigger signal, which is configured to initialize the clock calibration process in circuit 10.
[0090] (Optional) Status register 46 is used to store configuration data about circuit 10, as discussed below.
[0091] Note that although they are shown as components outside of circuit 10, in one or more embodiments, timer 45 and status register 46 may have been integrated into circuit 10.
[0092] like Figures 1 to 4 As illustrated, electronic device 40 includes:
[0093] The reference clock node REF is configured to provide a reference period T. REF The reference clock signal REF, which is in the reference period T REF The first sub-period T REF,H During the period, it has a first logic value, and in the second sub-period T of the reference period. REF,L The period has a second logical value;
[0094] The sampling clock node HSCK is configured to receive a sampling clock period T. HSCK The sampling clock signal HSCK, where the sampling clock period T HSCK It has a shorter reference period than the reference clock signal;
[0095] Measurement circuit block 12 is configured as follows:
[0096] The first sub-period is measured as the first sub-period T. REF,H The first ratio N to the period of the sampling clock signal;
[0097] The second sub-period is measured as the second sub-period T. REF,L The second ratio M to the period of the sampling clock signal,
[0098] Detection circuit block 16 is configured to detect the start edge START of a clock signal CK0 having a clock period T0 that is larger than the reference period.
[0099] Reconstruction circuit block 14 is configured to generate a reconstruction reference signal CKR based on the measured number of first and second cycles of the sampling clock and the detected start edge.
[0100] Comparator circuit block 18 is configured to perform a comparison between the clock period of the clock signal and the period of the reconstructed reference signal, and obtain a differential signal CKN indicating the difference between them as a result of the comparison. The comparator circuit block is configured to provide the differential signal to the user circuit device U for calibrating the clock signal based on the differential signal.
[0101] For example, the reconstruction circuit block is configured to generate a reconstruction reference signal having a reconstruction period equal to the reference period and starting at a time equal to the detected start edge.
[0102] like Figures 1 to 4 As illustrated, the detection circuit block is configured to sample the clock signal via the sampling clock signal, and as a result obtain a sampled clock signal CKS, wherein the sampled clock signal and the reconstructed reference signal have clock edges START that start at the same time, and wherein the comparator circuit block is configured to perform a comparison of the clock period of the clock signal with the period of the reconstructed reference signal, and as a result of the comparison obtain a differential signal CKN indicating the difference between them.
[0103] For example, a comparator circuit block is configured to provide a differential signal to a user circuit device to calibrate a clock signal based on the differential signal.
[0104] like Figure 4 As illustrated, the electronic device includes: a register circuit block 46 configured to store the time length of a time interval START_CAL_INT; and a timer circuit block 45 configured to trigger a comparator circuit to repeat the comparison after a set time length has elapsed.
[0105] For example, the clock period of a clock signal is affected by at least one physical quantity.
[0106] like Figure 4 As illustrated, the electronic device includes an event selection circuit device 42, configured to receive a set of sensing signals TS, VS, TTS indicating at least one physical quantity affecting a clock signal, and configured to trigger a 42START_CAL_sel comparator circuit block for repeated comparison in response to the sensing signals indicating the physical quantity affecting the clock cycle.
[0107] like Figure 4 As illustrated, the electronic device includes a logic circuit device 48 configured to enable a comparator circuit block to perform a comparison in response to receiving at least one enable calibration signal START_CAL_int, START_CAL_sel, START_CAL.
[0108] like Figure 4 As illustrated, a user can (re)write the operating mode of circuit 10 in the internal register 46 of device 40 via BUS interface 44, for example, by determining whether to use an internal or external timer.
[0109] For example, with the internal timer source 45 selected, calibration can be scheduled by the timer using a standard BUS cycle in a manner known per se.
[0110] For example, in the case of an external trigger source 42, the user can select which event or type of event to trigger calibration from a set of sensing signals VS, TS, TTS by using configuration data provided by the user via the bus interface 44.
[0111] like Figure 4 As illustrated, circuit 10 can be adjusted to provide an interrupt signal INT and an error signal CKN.
[0112] For example, the interrupt generating an INT can be used to indicate that the system calibration process is complete and that a frequency error value is available. For instance, the central processing unit (CPU) can use such a value to (readjust) its internal clock source.
[0113] like Figure 5 As illustrated, clock reconstruction circuitry 10 and / or device 40 can be integrated into a system-on-a-chip (SoC) architecture as a general-purpose peripheral device that interfaces via a standard bus, thereby providing increased flexibility.
[0114] like Figures 1 to 5 As illustrated, the System-on-Chip (SoC) 50 includes:
[0115] A set of processing cores 52 is configured to operate based on at least one clock signal CK0.
[0116] Equipment 40, such as Figures 1 to 4 As illustrated in the diagram, the device is coupled to the set of processing cores and is configured to receive at least one clock signal CK0 and provide the user circuit device U with a differential signal indicating the difference between the clock period T0 of the CKN clock signal and the period of the reconstructed reference signal CKR.
[0117] like Figure 5 As exemplified in , the SoC 50 includes:
[0118] A set of processing circuit blocks (or processing cores) 52 are coupled to corresponding cache memory blocks 520 and are coupled to one or more flash memory blocks 54 (and corresponding flash memory interfaces 540) in a manner known per se via one or more bus matrices (e.g., AHB1 bus matrix 58).
[0119] like Figure 5 As illustrated, cache 520 can be coupled to the corresponding processing core 52 via (e.g., 128-bit) C bus in a manner known per se, while S bus can be employed to couple processing core 52 to bus matrix 58.
[0120] like Figure 5 As illustrated, flash memory 54 can be coupled to interface 540 via a corresponding BUS configured to transmit 128-bit blocks plus ECC signals.
[0121] For example, device 40 can communicate with the processing circuit core via peripheral interface 56 in a manner known per se, so the corresponding description is omitted for brevity.
[0122] One or more embodiments may be adapted for use with SoC architectures, such as the architecture of microcontrollers (e.g., memory and peripherals) provided by STMicroelectronics under the commercial names 32U575 / 585.
[0123] like Figure 4 As illustrated, the electronic device 40 can be integrated into the SoC 50 via a standard bus architecture as a peripheral interface 56, thereby increasing versatility. For example, the peripheral device 40 can be used to provide an error signal for calibrating a clock signal in the SoC, wherein clock calibration based on the error signal CKN can be performed in a manner known per se, depending on the type of oscillator that generates the clock signal for calibration.
[0124] It will also be understood that the various individual implementation options illustrated throughout the accompanying drawings are not necessarily intended to be used in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.
[0125] Details and embodiments may vary, even significantly, relative to what has been described by way of example only, without departing from the scope of protection. The scope of protection is defined by the appended claims.
Claims
1. A method for calibrating a clock signal, comprising: A reference clock signal with a reference period is provided, the reference clock signal having a first logic value during a first sub-period of the reference period and a second logic value during a second sub-period of the reference period; A sampling clock signal with a sampling clock period is provided, wherein the sampling clock period is shorter than the reference period of the reference clock signal; The first sub-cycle is measured as a first ratio of the first sub-cycle to the sampling clock cycle; The second sub-cycle is measured as a second ratio of the second sub-cycle to the sampling clock cycle; Detect the start edge of a first clock signal having a first clock period longer than the reference period; A reconstruction reference signal is generated based on the first ratio, the second ratio, and the detected start edge; A differential signal indicating the difference between the first clock period of the first clock signal and the period of the reconstructed reference signal is obtained as a result of the comparison. as well as The differential signal is provided to a user circuit device configured to calibrate the first clock signal based on the differential signal.
2. The method of claim 1, wherein the reconstructed reference signal has a reconstruction period equal to the reference period and is synchronized with the detected start edge.
3. The method according to claim 1, further comprising: The first clock signal is sampled via the sampling clock signal to obtain a sampled clock signal, wherein the sampled clock signal and the reconstructed reference signal have corresponding clock edges that are synchronized at the same time.
4. The method according to claim 1, further comprising: Set the duration of the time interval; as well as The comparison is repeated after the set time period has elapsed.
5. The method of claim 1, wherein the first clock period of the first clock signal is affected by at least one physical quantity, and wherein the method comprises: Receive a set of sensing signals indicating at least one physical quantity affecting the first clock signal; as well as The comparison is triggered in response to the sensing signal indicating at least one physical quantity affecting the first clock cycle.
6. The method according to claim 1, further comprising: The comparison is enabled in response to receiving at least one enable calibration signal.
7. An electronic device, comprising: A reference clock node is configured to provide a reference clock signal having a reference period, the reference clock signal having a first logic value during a first sub-period of the reference period and a second logic value during a second sub-period of the reference period; A sampling clock node is configured to receive a sampling clock signal having a sampling clock period, wherein the sampling clock period is shorter than the reference period of the reference clock signal; The measurement circuit block is configured as follows: The first sub-cycle is measured as a first ratio of the first sub-cycle to the period of the sampling clock signal; as well as The second sub-cycle is measured as a second ratio of the second sub-cycle to the period of the sampled clock signal; The detection circuit block is configured to detect the start edge of a first clock signal having a first clock period longer than the reference period; The reconstruction circuit block is configured to generate a reconstruction reference signal based on the first and second cycle counts of the measured sampling clock signal and the detected start edge. as well as The comparator circuit block is configured as follows: A differential signal indicating the difference between the first clock period of the first clock signal and the period of the reconstructed reference signal is obtained as a result of the comparison. as well as The differential signal is provided to the user circuitry to calibrate the first clock signal based on the differential signal.
8. The electronic device of claim 7, wherein the reconstruction circuit block is configured to generate the reconstruction reference signal having a reconstruction period equal to the reference period and starting at a time equal to the detected start edge.
9. The electronic device of claim 7, wherein the detection circuit block is configured to sample the first clock signal via the sampling clock signal to obtain a sampled clock signal as a result, wherein the sampled clock signal and the reconstructed reference signal have corresponding clock edges that start at the same time.
10. The electronic device according to claim 7, further comprising: The register circuit block is configured to store the duration of a time interval. as well as A timer circuit block is configured to trigger the comparator circuit block to repeat the comparison after the stored time length has elapsed.
11. The electronic device of claim 7, wherein the first clock period of the first clock signal is affected by at least one physical quantity, and wherein the electronic device includes an event selection circuit means configured to: Receive a set of sensing signals indicating at least one physical quantity affecting the first clock signal; and The comparator circuit block is triggered in response to the sensing signal indicating at least one physical quantity affecting the first clock cycle to repeat the comparison.
12. The electronic device according to claim 7, further comprising: A logic circuit device is configured to enable the comparator circuit block to perform the comparison in response to receiving at least one enable calibration signal.
13. The electronic device of claim 7, wherein the comparator circuit block is further configured to provide an interrupt signal indicating that the differential signal is available to the user circuit device.
14. A system-on-a-chip, comprising: A set of processing cores is configured to operate based on at least one clock signal; A device, coupled to the set of processing cores and configured to receive the at least one clock signal, the device comprising: A reference clock node is configured to provide a reference clock signal having a reference period, the reference clock signal having a first logic value during a first sub-period of the reference period and a second logic value during a second sub-period of the reference period; A sampling clock node is configured to receive a sampling clock signal having a sampling clock period, wherein the sampling clock period is shorter than the reference period of the reference clock signal; The measurement circuit block is configured as follows: The first sub-period is measured as a first ratio of the first sub-period to the period of the sampled clock signal; and The second sub-cycle is measured as a second ratio of the second sub-cycle to the period of the sampled clock signal; The detection circuit block is configured to detect the start edge of the at least one clock signal having at least one clock cycle longer than the reference period; The reconstruction circuit block is configured to generate a reconstruction reference signal based on the first and second cycle numbers of the measured sampling clock signal and the detected start edge; and The comparator circuit block is configured as follows: A comparison is performed between the at least one clock period of the at least one clock signal and the period of the reconstructed reference signal, and a differential signal indicating the difference between the at least one clock period of the at least one clock signal and the period of the reconstructed reference signal is obtained as a result of the comparison; and The differential signal is provided to the user circuitry to calibrate the at least one clock signal based on the differential signal.
15. The system-on-a-chip of claim 14, wherein the reconstruction circuit block is configured to generate the reconstruction reference signal having a reconstruction period equal to the reference period and starting at a time equal to the detected start edge.
16. The system-on-a-chip of claim 14, wherein the detection circuit block is configured to sample the at least one clock signal via the sampling clock signal to obtain a sampled clock signal as a result, wherein the sampled clock signal and the reconstructed reference signal have corresponding clock edges that start at the same time.
17. The system-on-a-chip of claim 14, wherein the device further comprises: The register circuit block is configured to store the duration of a time interval. as well as A timer circuit block is configured to trigger the comparator circuit block to repeat the comparison after the stored time length has elapsed.
18. The system-on-a-chip of claim 14, wherein the at least one clock cycle of the at least one clock signal is affected by at least one physical quantity, and wherein the device includes an event selection circuit arrangement configured to: Receive a set of sensing signals indicating at least one physical quantity affecting at least one clock signal; and The comparator circuit block is triggered in response to the sensing signal indicating the at least one physical quantity affecting the at least one clock cycle to repeat the comparison.
19. The system-on-a-chip of claim 14, wherein the device further comprises: A logic circuit device is configured to enable the comparator circuit block to perform the comparison in response to receiving at least one enable calibration signal.
20. The system-on-a-chip of claim 14, wherein the comparator circuit block is further configured to provide an interrupt signal indicating that the differential signal is available to the user circuitry device.