1486results about "Analogue/digital conversion calibration/testing" patented technology

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a multi-channel acquisition module, system and method based on trigger synchronization automatic calibration, and belongs to the field of electronic measurement, the acquisition module comprises a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit and an FPGA receiving and synchronous calibration circuit; the method has the advantages that the multi-channel synchronization precision is high, convenient channel expansion is supported, pairwise interconnection delay calibration can be carried out between modules in parallel, the system calibration time does not increase linearly along with the increase of the number of the channels, the interconnection relation is realized through annular connection, and a large fan-out cable is not needed.

The invention provides an FI-DAC system peak nonlinear amplitude-frequency error pre-calibration method based on SVR-LWL, belongs to the technical field of amplitude-frequency error calibration, and solves the problems that the fitting precision of passband signals is reduced and the calibration effect is affected due to the fact that a traditional amplitude-frequency error calibration method is difficult to meet the actual application requirement. Comprising the following steps: step 1, pre-distortion processing is carried out on a target input signal of an FI-DAC system, ideal frequency division processing is carried out on the target input signal after pre-distortion processing by adopting a linear phase FIR digital filter, and a high-frequency sub-path signal and a low-frequency sub-path signal are obtained; 2, performing frequency mixing, filtering, analog-to-digital conversion and combination operation on the high-frequency sub-path signal and the low-frequency sub-path signal, and inputting the signals into an analog link to generate a broadband signal; and step 3, carrying out dynamic calibration on amplitude-frequency errors caused by nonlinear characteristics based on an amplitude-frequency error pre-equalizer in the analog link, generating a calibrated target signal waveform table, and outputting the calibrated target signal waveform table.

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

The invention relates to a capacitor mismatch foreground calibration method suitable for an SARADC, and the method comprises the steps: S1, enabling an analog input signal, a random jitter signal and a dynamic element to be matched with each other, and jointly inputting the signals into a capacitive digital-to-analog converter; s2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing to obtain an output digital code; s3, calculating an evaluation value of the corresponding output digital code; s4, obtaining an error between the actual output value and the reference output value estimation value; s5, iterating the capacitance weight and the random signal according to the size of the error by utilizing an LMS (Least Mean Square) algorithm; and S6, continuously changing the capacitance weight and the random signal to enable the error to be within an allowable range, and obtaining more accurate output. According to the invention, no additional analog circuit needs to be added for capacitor mismatch calibration, and parameters such as the significant bit number and the spurious-free dynamic range of the ADC are obviously improved.

The invention discloses a multipath signal conversion crosstalk-free optimization system and method, and relates to the technical field of data acquisition and signal processing, and the system comprises a detection module which is used for generating an initial calibration parameter based on a synchronization signal phase deviation detection result, and an adjustment module which is used for adjusting the frequency and phase of a sampling clock according to the initial calibration parameter, the calibration module is used for carrying out alignment calibration on multiple paths of data to obtain an alignment error value, and the optimization module is used for further optimizing a sampling clock based on the alignment error value to realize accurate calibration; compared with a traditional hardware phase-locked loop system, the multipath signal conversion crosstalk-free optimization system and method have higher adjustment flexibility and synchronization precision, are suitable for a high-frequency and high-precision data acquisition application environment, and improve overall sampling accuracy and data analysis reliability while maintaining system stability.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

An apparatus as discussed herein can be configured to include a first analog-to-digital converter operative to convert a first analog voltage into a first digital signal; a digital-to-analog converter operative to convert the first digital signal into a second analog voltage; a switched capacitor circuit coupled to the digital-to-analog converter, the switched capacitor circuit is operative to store a sample of the second analog voltage; and a second analog-to-digital converter operative to convert an analog error voltage into a second digital signal, the analog error voltage based on a difference between the sample of the second analog voltage received from the switched capacitor circuit and a sample of the first analog voltage.

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

The embodiment of the invention provides a capacitor array calibration method, a controller, a medium and a product, which are applied to the technical field of analog-to-digital signal conversion and applied to a capacitor array calibration system, the system comprises a basic capacitor array, a plurality of temperature decoding capacitor arrays and an A / D conversion module, the method comprises the following steps: acquiring residual voltages of to-be-calibrated capacitors in a basic capacitor array and temperature decoding capacitor arrays; performing analog-to-digital conversion on each residual voltage through an A / D conversion module to obtain a digital code of each capacitor to be calibrated; through a preset mismatch code calculation formula, mismatch codes of the to-be-calibrated capacitors are obtained through calculation according to the digital codes; and calibrating the basic capacitor array and each temperature decoding capacitor array according to each mismatch code. According to the embodiment of the invention, the basic capacitor array and each temperature decoding capacitor array are calibrated through each mismatch code, so that the phenomenon of electric leakage of the capacitor arrays can be avoided, and the accuracy of the circuit is improved.

The invention discloses a sampling circuit and a calibration method thereof, a battery management system and a power utilization device. The calibration method comprises the following steps: acquiring the voltage of a first type of sampling points and the voltage of a second type of sampling points; determining a calibration factor corresponding to the first type of sampling points according to the voltage of the first type of sampling points and the voltage of the second type of sampling points; and based on the calibration factor, correcting the voltage of the first type of sampling points to obtain the corrected voltage of the first type of sampling points. The problem that the sampling precision of the sampling points in the sampling circuit is poor can be solved.

The invention discloses a dual-channel analog-to-digital conversion chip synchronization control method and system, and relates to the technical field of analog-to-digital conversion, and the method comprises the following steps: a system initialization step: carrying out the initialization operation of a dual-channel analog-to-digital conversion chip, a synchronization signal generator, a control circuit and a data processing module; configuring a working mode, a sampling rate and a data output format of the dual-channel analog-to-digital conversion chip; configuring clock parameters of the synchronizing signal generator; setting a control algorithm and initialization parameters of the control circuit; the dual-channel analog-to-digital conversion chip is used for presetting processing parameters such as filtering and calibration of the data processing module, the dual-channel analog-to-digital conversion chip comprises two independent analog-to-digital conversion channels which are respectively used for processing two paths of analog signals, a high-precision synchronous control signal is generated through the synchronous signal generator, accurate synchronization of sampling moments of the two paths of analog signals is realized, and the sampling precision of the two paths of analog signals is improved. The synchronization precision of dual-channel analog-to-digital conversion is effectively improved, signal processing errors caused by asynchronous sampling are reduced, and the system performance is improved.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

A method for calibrating a machine-learning unit includes generating an analog calibration signal from an input sequence; generating a digital calibration signal by taking digital samples representing the value of the analog calibration signal at a predetermined sample rate; and applying the analog calibration signal as an input to a physical parallel array analog-to-digital converter (PA ADC) to produce a digital response. The method further includes producing an output by the machine-learning unit, at least in part based on the digital response; modifying a parameter of the machine-learning unit to reduce an error between the output and the digital calibration signal; and determining that the error is not less than a predetermined threshold.

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

The invention relates to the technical field of semiconductor detection, and discloses an ATE equipment high-speed AC signal calibration system and method, and the system comprises at least one FPGA module which is provided with a plurality of channels for bidirectional signal transmission; each PE module is correspondingly positioned on one channel of the FPGA and is used for receiving the driving signal output by the FPGA and an external input signal and sending a feedback signal to the FPGA module according to the driving signal; the signal calibration module is located in the FPGA and used for receiving the feedback signals and comparing time delays between the feedback signals input from different channels; the delay compensation module is positioned in the FPGA and is configured to adjust the time delay of each channel based on the comparison result of the signal calibration module so as to realize the synchronization of the signals of the plurality of channels; and when a plurality of FPGAs exist, the system also comprises a PLL module, and the PLL module is configured to provide synchronous clock signals with the same frequency and fixed phase to the plurality of FPGAs at the same time, so as to ensure that the internal clocks of the FPGAs are synchronous.

The invention discloses a multi-harmonic quantum voltage synthesis device based on an optimal phase plane, which comprises a signal generation module, a delta-sigma modulator, a pulse code pattern driving module and a Josephson junction array, and is characterized in that the signal generation module is sequentially connected with the delta-sigma modulator, the pulse code pattern driving module and the Josephson junction array; according to the invention, through phase plane optimization, signals are more uniformly distributed in a phase plane, and excellent performance in the aspects of test efficiency and coverage rate is shown; the multi-harmonic design based on R can maximize the ADC test coverage rate and better describe analog-to-digital conversion error distribution, and the optimized signal generates a predetermined multi-harmonic quantum voltage signal through an ACJVS system; the ACJVS is a very ideal waveform generator, the problems of high distortion and high background noise of a conventional synthesis mode do not exist, quantum accuracy of synthesized voltage signals can be guaranteed, and therefore ADC testing and work in other measurement fields can be better carried out.

The invention discloses a calibration method for sampling time offset mismatch of TI-ADC for SerDes and a storage medium. The calibration method comprises the following steps: performing operation on a current output value obtained by quantization of each sub-ADC and a previous beat of data recovered by judgment of SerDes; taking a certain sub-ADC channel as a reference to obtain an error function of offset of sampling time of other sub-ADCs relative to the reference time; and the sampling time of the sub-ADCs is adjusted by adopting an LMS algorithm to minimize an error function, so that the calibration of the sampling time offset mismatch is completed. The storage medium is used for storing a computer program for executing the method. The method has the advantages of simple principle, simplicity and convenience in operation, wide application range, good calibration effect, high precision and the like.

The invention provides a linearity correction circuit and a linearity correction method for a successive approximation analog-to-digital converter, which are applied to the technical field of semiconductor integrated circuit design and are used for multiplexing part of capacitors in an analog-to-digital converter capacitor array to inject jitter noise so as to improve the linearity of an SAR ADC under small input amplitude and improve the linearity of the SAR ADC under small input amplitude in a sampling stage. An input signal is coupled to an upper pole plate of the DAC capacitor array, and meanwhile, a lower pole plate of the multiplexing capacitor unit is connected to a reference voltage controlled by a dither signal; after a phase is sampled and before the phase is converted, a lower pole plate of a multiplexing capacitor unit is switched to a fixed reference voltage, random jitter noise is injected at the moment, after the voltage of a top pole plate of a capacitor array is established stably, a comparator is enabled, successive approximation conversion is started, and the jitter noise is injected by multiplexing part of capacitors in the existing CDAC capacitor array, so that the random jitter noise is generated. The random jitter noise injection by using an extra capacitor array is avoided, the circuit design is simplified, the circuit cost and power consumption are reduced, and the linearity of the SAR ADC is improved.

The invention discloses a gain-dependent rapid hybrid direct current offset correction circuit, which comprises a direct current correction controller, a hybrid direct current offset corrector and a digital domain direct current offset corrector, the direct current offset correction controller is used for outputting a first control signal enable mix according to state information rxstate sent by a state controller of the zero intermediate frequency receiver so as to start the hybrid direct current offset corrector; the hybrid direct-current offset corrector is used for operating a hybrid direct-current offset correction algorithm to perform hybrid direct-current offset correction to obtain a correction code word when the first control signal enable signal is a first value; and the digital domain direct current offset corrector is used for operating a digital domain direct current offset correction algorithm when the first control signal enable mix signal is a second value, and performing digital domain direct current correction according to the correction code word. Compared with a traditional direct current offset correction method, the method provided by the invention has the characteristics that the correction speed is high, the correction precision is high, and the correction precision and the correction speed are not sensitive to the gain change of a receiver.

The present application relates to a signal processing apparatus, comprising: a first switch unit configured to receive a first analog signal; a first analog-to-digital conversion unit coupled to the first switch unit and configured to convert the first analog signal into a first digital signal; a core processing unit coupled to the first analog-to-digital conversion unit and configured to process the first digital signal and output a second digital signal at least comprising digital pre-distortion information; a first digital-to-analog conversion unit coupled to the core processing unit and configured to convert the second digital signal into a second analog signal; and the second switch unit is coupled to the first digital-to-analog conversion unit and is configured to output the second analog signal. The invention further relates to a signal processing method and electronic equipment. According to the invention, the problems of performance and linearity caused by a power amplifier can be overcome, and the processing performance and the adaptability are relatively high.

The invention discloses a digital measurement system channel error automatic calibration method, a storage medium and a system, and aims to automatically calibrate zero drift and multiplying power change errors from the angle of reducing DMS analog measurement channel tool errors. The method comprises the following steps of: firstly, connecting an input end of the DMS with a digital-to-analog converter (DAC), a circuit ground and a reference source Vref respectively, then measuring corresponding output voltages Dos, Dx and Dref of the DMS, and finally obtaining a calibration voltage Ui after error elimination by utilizing a formula # imgabs0 #. The calibration circuit required by the invention is simple in structure, low in cost, suitable for different types of DMS equipment, free of synchronism requirements on a measurement system, low in operation difficulty, capable of calibrating relative errors and absolute errors, high in automation degree, and capable of improving the measurement precision of the DMS on the premise of considering the measurement time; and the working reliability and stability of the measuring equipment are improved.

The invention discloses an ambient light adaptive correction system based on feedback control, which comprises a photodiode, a TIA module, a TIA DC compensation module, an analog-to-digital conversion module, a feedback control module and a data register, and is characterized in that the photodiode is used for converting an optical signal into a light current, and the light current is transmitted to the analog-to-digital conversion module after being processed by the TIA module and the TIA DC compensation module; the analog-to-digital conversion module converts the optical current into a digital signal and transmits the digital signal to the feedback control module; the feedback control module is electrically connected with the TIA direct current compensation module and the data register; wherein the feedback control module is used for realizing an ambient light self-adaptive correction method based on feedback control, and the self-adaptive correction method feeds back and adjusts TIA bias current in real time according to light current, ensures the working consistency of the TIA, ensures that the current sampled by the ADC is within a certain range, and calibrates the proportion of the sampled current, so that the current measurement precision of the ADC is improved; and adaptive calibration under chip distance measurement is realized.

The invention relates to the technical field of radio frequency signal processing, and discloses a digital filtering repair method and system for signal distortion, and the method comprises the steps: obtaining a frequency domain amplitude-frequency response and a phase response; constructing a phase compensation amount by adopting piecewise polynomial fitting and a phase inversion mechanism; a complex number logarithm domain mapping mechanism is adopted to execute composite frequency response inversion; constructing a switchable hybrid digital filter with an amplitude path and a phase path coupled in parallel; multi-band adaptive scheduling is executed; and outputting the radio frequency baseband signal stream. The technical problems that in the prior art, frequency response nonlinear distortion in a broadband range cannot be dealt with by adopting a fixed template or a single-path filter, and particularly, a high-precision and low-delay dynamic compensation effect cannot be realized in a scene that multi-band coupling interference exists in a radio frequency ADC channel with the bandwidth exceeding 800MHz are solved. Due to the fact that the switchable hybrid digital filter is constructed, accurate modeling and flexible recovery of distortion characteristics in broadband signals are achieved.

The invention relates to the field of electronic signal processing, and discloses a 3D rocker sensor-based digital quantity center point adaptive verification system, which comprises a data acquisition layer used for acquiring an analog signal of a 3D rocker sensor through an analog-to-digital converter and converting the analog signal into a digital signal; the data preprocessing layer is used for carrying out filtering processing and center point correction on the acquired digital signals and dynamically adjusting the maximum value and the minimum value of the signals; the signal conversion layer is used for converting the corrected signal into a standardized data format so as to adapt to a control system; and the signal output layer is used for smoothing the standardized signal and compensating the signal according to action recognition. Through a digital quantity dynamic correction technical scheme based on the 3D rocker sensor, real-time correction of a rocker signal center point is realized, signal deviation caused by drifting and external interference is eliminated, signal stability and processing precision are improved, and meanwhile, robustness and use reliability of a system are improved.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

The invention provides a block LMS (Least Mean Square)-based calibration type high-precision multi-stage PipelinedSAR ADC (Analog to Digital Converter). The block LMS-based calibration type high-precision multi-stage PipelinedSAR ADC comprises a first-stage ADC sub-circuit, a second-stage ADC sub-circuit and a third-stage ADC sub-circuit, wherein the first-stage ADC sub-circuit is used for sampling an input signal and The nth-stage ADC sub-circuit performs residual amplification and re-sampling on the voltage signal of the upper electrode plate of the capacitor after the last adjustment of the previous-stage sub-circuit is completed, and performs cyclic comparison adjustment for multiple times according to the sampled signal, so as to output a 9-bit comparison result digital code; and the dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain correct weights, and then performs normal ADC sampling quantization to obtain digital codes with relatively high linearity. According to the method, the first five DACs are split to generate corresponding capacitor selection bits, the multiple requirement for a residual amplifier is relaxed through inter-stage capacitance scaling, the correct weight is obtained by processing the calibration weight twice, and the linearity can be improved.