1161results about "Analogue/digital conversion calibration/testing" patented technology

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a multi-channel acquisition module, system and method based on trigger synchronization automatic calibration, and belongs to the field of electronic measurement, the acquisition module comprises a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit and an FPGA receiving and synchronous calibration circuit; the method has the advantages that the multi-channel synchronization precision is high, convenient channel expansion is supported, pairwise interconnection delay calibration can be carried out between modules in parallel, the system calibration time does not increase linearly along with the increase of the number of the channels, the interconnection relation is realized through annular connection, and a large fan-out cable is not needed.

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

The invention discloses a multipath signal conversion crosstalk-free optimization system and method, and relates to the technical field of data acquisition and signal processing, and the system comprises a detection module which is used for generating an initial calibration parameter based on a synchronization signal phase deviation detection result, and an adjustment module which is used for adjusting the frequency and phase of a sampling clock according to the initial calibration parameter, the calibration module is used for carrying out alignment calibration on multiple paths of data to obtain an alignment error value, and the optimization module is used for further optimizing a sampling clock based on the alignment error value to realize accurate calibration; compared with a traditional hardware phase-locked loop system, the multipath signal conversion crosstalk-free optimization system and method have higher adjustment flexibility and synchronization precision, are suitable for a high-frequency and high-precision data acquisition application environment, and improve overall sampling accuracy and data analysis reliability while maintaining system stability.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

An apparatus as discussed herein can be configured to include a first analog-to-digital converter operative to convert a first analog voltage into a first digital signal; a digital-to-analog converter operative to convert the first digital signal into a second analog voltage; a switched capacitor circuit coupled to the digital-to-analog converter, the switched capacitor circuit is operative to store a sample of the second analog voltage; and a second analog-to-digital converter operative to convert an analog error voltage into a second digital signal, the analog error voltage based on a difference between the sample of the second analog voltage received from the switched capacitor circuit and a sample of the first analog voltage.

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

The invention discloses a dual-channel analog-to-digital conversion chip synchronization control method and system, and relates to the technical field of analog-to-digital conversion, and the method comprises the following steps: a system initialization step: carrying out the initialization operation of a dual-channel analog-to-digital conversion chip, a synchronization signal generator, a control circuit and a data processing module; configuring a working mode, a sampling rate and a data output format of the dual-channel analog-to-digital conversion chip; configuring clock parameters of the synchronizing signal generator; setting a control algorithm and initialization parameters of the control circuit; the dual-channel analog-to-digital conversion chip is used for presetting processing parameters such as filtering and calibration of the data processing module, the dual-channel analog-to-digital conversion chip comprises two independent analog-to-digital conversion channels which are respectively used for processing two paths of analog signals, a high-precision synchronous control signal is generated through the synchronous signal generator, accurate synchronization of sampling moments of the two paths of analog signals is realized, and the sampling precision of the two paths of analog signals is improved. The synchronization precision of dual-channel analog-to-digital conversion is effectively improved, signal processing errors caused by asynchronous sampling are reduced, and the system performance is improved.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

The invention provides a linearity correction circuit and a linearity correction method for a successive approximation analog-to-digital converter, which are applied to the technical field of semiconductor integrated circuit design and are used for multiplexing part of capacitors in an analog-to-digital converter capacitor array to inject jitter noise so as to improve the linearity of an SAR ADC under small input amplitude and improve the linearity of the SAR ADC under small input amplitude in a sampling stage. An input signal is coupled to an upper pole plate of the DAC capacitor array, and meanwhile, a lower pole plate of the multiplexing capacitor unit is connected to a reference voltage controlled by a dither signal; after a phase is sampled and before the phase is converted, a lower pole plate of a multiplexing capacitor unit is switched to a fixed reference voltage, random jitter noise is injected at the moment, after the voltage of a top pole plate of a capacitor array is established stably, a comparator is enabled, successive approximation conversion is started, and the jitter noise is injected by multiplexing part of capacitors in the existing CDAC capacitor array, so that the random jitter noise is generated. The random jitter noise injection by using an extra capacitor array is avoided, the circuit design is simplified, the circuit cost and power consumption are reduced, and the linearity of the SAR ADC is improved.

The invention discloses an ambient light adaptive correction system based on feedback control, which comprises a photodiode, a TIA module, a TIA DC compensation module, an analog-to-digital conversion module, a feedback control module and a data register, and is characterized in that the photodiode is used for converting an optical signal into a light current, and the light current is transmitted to the analog-to-digital conversion module after being processed by the TIA module and the TIA DC compensation module; the analog-to-digital conversion module converts the optical current into a digital signal and transmits the digital signal to the feedback control module; the feedback control module is electrically connected with the TIA direct current compensation module and the data register; wherein the feedback control module is used for realizing an ambient light self-adaptive correction method based on feedback control, and the self-adaptive correction method feeds back and adjusts TIA bias current in real time according to light current, ensures the working consistency of the TIA, ensures that the current sampled by the ADC is within a certain range, and calibrates the proportion of the sampled current, so that the current measurement precision of the ADC is improved; and adaptive calibration under chip distance measurement is realized.

The invention relates to the technical field of radio frequency signal processing, and discloses a digital filtering repair method and system for signal distortion, and the method comprises the steps: obtaining a frequency domain amplitude-frequency response and a phase response; constructing a phase compensation amount by adopting piecewise polynomial fitting and a phase inversion mechanism; a complex number logarithm domain mapping mechanism is adopted to execute composite frequency response inversion; constructing a switchable hybrid digital filter with an amplitude path and a phase path coupled in parallel; multi-band adaptive scheduling is executed; and outputting the radio frequency baseband signal stream. The technical problems that in the prior art, frequency response nonlinear distortion in a broadband range cannot be dealt with by adopting a fixed template or a single-path filter, and particularly, a high-precision and low-delay dynamic compensation effect cannot be realized in a scene that multi-band coupling interference exists in a radio frequency ADC channel with the bandwidth exceeding 800MHz are solved. Due to the fact that the switchable hybrid digital filter is constructed, accurate modeling and flexible recovery of distortion characteristics in broadband signals are achieved.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

The invention provides a sampling compensation circuit, a voltage sampling device and radio frequency power supply equipment, and relates to the technical field of power electronics, the sampling compensation circuit is used for compensating a sampling voltage value obtained by a voltage sampling circuit, the voltage sampling circuit at least comprises a sampling diode, the sampling diode is used for rectifying a to-be-detected alternating current signal, and the to-be-detected alternating current signal is sent to the sampling compensation circuit. Therefore, a sampling voltage signal is obtained. The sampling compensation circuit comprises a voltage drop acquisition unit and a sampling compensation unit. The first input end and the second input end of the voltage drop obtaining unit are used for being connected with the first end and the second end of the sampling diode respectively, and the voltage drop obtaining unit is used for obtaining a voltage difference signal. The sampling compensation unit is used for acquiring a sampling voltage signal output by the second end of the sampling diode and a voltage difference signal output by the first output end of the voltage drop acquisition unit, and compensating the sampling voltage signal according to the voltage difference signal to obtain a corrected sampling signal. According to the invention, a more accurate sampling voltage value can be obtained.

A time-interleaved current-based digital-to-analog converter (current DAC) cell includes first input circuitry configured to receive a digital input signal, a first biasing voltage, a first clock, and a second clock. The first clock and the second clock having a phase offset from one another and having a common period. The current DAC also includes a first gate configured to, responsive to an ‘ON’ state of the first clock, pass the digital input signal to a second gate, the second gate being configured to, responsive to an ‘OFF’ state of the second clock, output a first DAC cell activation signal. The current DAC further includes first output circuitry configured to, responsive to the first DAC cell activation signal, output a first analog current signal based on (i) the digital input signal and (ii) the first biasing voltage.

An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A / D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A / D conversions.

The invention relates to the technical field of semiconductor integrated circuits, and discloses a bandwidth mismatch calibration system and method of a time-interleaved architecture ADC (Analog to Digital Converter). The system comprises N sub-ADCs, N bandwidth adjustment units and a controller. Firstly, a unified calibration signal is input into all sub-ADCs, and each sub-ADC samples the transition edge of the signal. The controller detects and determines a transition point error of each sub-ADC at the transition edge based on the sampling output of each sub-ADC. The controller calculates bandwidth adjustment code words for the corresponding sub-ADCs based on the difference between the error and a preset target value. The code word is used for driving the bandwidth adjusting unit to adjust the bandwidth of the corresponding sub-ADC, so that the bandwidths of all the sub-ADCs tend to be consistent through closed-loop feedback, and automatic and accurate calibration of bandwidth mismatch is realized.

The present disclosure provides a multi-channel signal sampling device and a calibration system, belonging to the technical field of signal processing; the multi-channel signal sampling device comprises a PXIe chassis and at least two acquisition cards arranged in the PXIe chassis; the multi-channel signal sampling device further comprises a synchronization program component, which is executed to determine the delay data between each channel of each acquisition card and the trigger channel according to the trigger channel currently located in the first target acquisition card and the pre-stored synchronization calibration basic data, and to synchronize each channel and the trigger channel according to the delay data; the synchronization calibration basic data comprises single-board calibration data and cross-board calibration data; the multi-channel signal sampling device can solve the problems of high synchronization calibration cost and design difficulty existing in the current PXIe sampling device.

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

The present disclosure relates to an integrated circuit for calibration of an offset voltage mismatch between comparators in an analog-to-digital converter and a method. The integrated circuit comprises a successive-approximation analog-to-digital converter comprising N+1 comparators, and N calibration circuits. The input end of any calibration circuit is connected to the output end of the successive-approximation analog-to-digital converter, and the output end of any calibration circuit is connected to the input end of a different comparator. The successive-approximation analog-to-digital converter is used for converting an input signal into a multi-bit digital code. Each calibration circuit is used for determining mismatch information on the basis of the multi-bit digital code, wherein the mismatch information is used for correcting an offset voltage of the comparator connected to the calibration circuit. According to embodiments of the present disclosure, calibration circuits are used to increase the conversion rate and improve the quantization precision of an analog-to-digital converter, and reduce hardware complexity and non-ideal effects.

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

Certain aspects of the present disclosure provide techniques and apparatus for digital-to-analog conversion. An example apparatus generally includes a digital-to-analog converter (DAC), an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC, and a controller coupled to the DAC and the IADC. The controller is configured to determine a direct current (DC) offset associated with the DAC using the IADC and control a mission-mode digital input signal of the DAC based on the DC offset.

An analog-to-digital converter including a voltage-to-delay circuit, a plurality of residue stages coupled in a sequence, and select logic. A first residue stage generates a bit output and a residue delay signal, a second residue stage generates a bit output and a residue delay signal responsive to the residue delay signal from the first residue stage, and a third residue stage generates a bit output and a residue delay signal responsive to the residue delay signal from the second residue stage. The third residue stage includes a plurality of trim circuits, the selection of which is controlled by the bit output of two or more preceding residue stages in the sequence.

An analog signal generation device according to the present invention includes a DA converter that adjusts a signal level of a digital signal according to a DAC correction amount and then converts the digital signal into an analog signal, a detector that detects the analog signal and outputs a detection signal, a storage unit that stores a characteristic equation for calculating the DAC correction amount, and a control unit, in which in a case where the differential voltage when the digital signal having a signal level of a predetermined value is input to the DA converter is larger than a threshold value, the control unit calculates a new DAC correction amount based on the differential voltage by using the characteristic equation, and in a case where the differential voltage does not fall within the threshold value, the control unit corrects the characteristic equation.

A novel CP signal detection circuit disclosed by the present application comprises a sampling circuit and a control circuit which are connected with a detection object, the sampling circuit comprises a rectification module, a voltage division module and a following module, the rectification module is connected with the detection object, the rectification module is connected with the voltage division module, and the following module is connected with the voltage division module. The following module is connected with the control circuit, the following module comprises an operational amplifier and a first clamping diode, an output pin of the first clamping diode is connected with an in-phase input pin of the operational amplifier, an inverted input pin of the operational amplifier is connected with an output pin of the operational amplifier, and an output pin of the operational amplifier is connected with the output pin of the first clamping diode. And an output pin of the operational amplifier is connected with the control circuit. The voltage dividing module is arranged in front of the following module, and the voltage state of the obtained CP signal is segmented, so that the control circuit can distinguish the work more accurately. And the following module is provided with a clamping diode at an input pin of an operational amplifier, so that the control circuit is prevented from being damaged.

An adaptive calibration detection method for an analog-to-digital converter chip comprises the following steps: acquiring an input analog signal of the analog-to-digital converter chip, and sampling the input analog signal to obtain a sampling signal; performing spectrum analysis on the sampling signal to obtain a spectrum characteristic parameter of the sampling signal; judging whether the analog-to-digital converter chip has a nonlinear error, an offset error or a gain error or not according to the frequency spectrum characteristic parameters; if an error exists, calculating a calibration parameter based on a preset calibration model in combination with the spectrum characteristic parameter; according to the calibration parameters, the conversion process of the analog-to-digital converter chip is adjusted in real time so as to compensate the errors, automatic detection and calibration of various errors of the analog-to-digital converter chip are achieved, the calibration precision and efficiency are improved, and meanwhile the performance of the high-speed channel signal integrity chip can be accurately evaluated.