3233results about "Analogue/digital conversion calibration/testing" patented technology

A signal processing system for reducing calibration-related distortions in a complete-channel signal generated by a multi-channel subsystem, such as an interleaved ADC, includes a channel separator for separating the distorted digital signal into its various sub-channels and a single-channel corrector for independently processing each sub-channel to reduce distortion products present therein. The system additionally includes a subchannel re-combiner for combining the plurality of sub-channels processed by the single-channel corrector and a multi-channel corrector for calibrating each of plurality of sub-channels relative to one another to yield an equalized, complete-channel output signal. The multi-channel corrector includes a bank of optimized filters, each filter being assigned to a corresponding sub-channel of the complete-channel signal. In one embodiment, one of the plurality of sub-channels is selected as an ideal reference signal and the filters assigned to the remaining sub-channels are optimized to yield outputs which match the ideal reference signal.

A calibratable analog-to-digital converter system with a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal. Calibration logic is responsive to the digital signals output by the N ADCs and is configured to calibrate each of the ADCs based on the digital signals output by each ADC.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.