97results about "Analogue/digital conversion calibration/testing" patented technology

This invention provides a semiconductor device that automatically corrects the conversion value of an analog-to-digital converter, a method for correcting the conversion value of an analog-to-digital converter, and a program for doing so. [Solution] The analog / digital converter 1 outputs a converted value DS obtained by converting the input signal IN from analog to digital. The non-volatile memory 11 stores multiple correction values. The correction circuit 21 selects a correction value from the multiple correction values ​​according to the situation, depending on the situation affecting the offset on the converted value DS of the analog / digital converter 1, and outputs an output value OUT with the offset on the converted value DS corrected based on the selected correction value.

The analog-to-digital converter system (10) includes a digital-to-analog converter (32) for generating a calibration voltage based on a digital input code, and an analog-to-digital converter (18) connected to the digital-to-analog converter (32) for receiving the calibration voltage from the digital-to-analog converter (32), receiving a sampled voltage, generating a digital output code based on the calibration voltage, and generating a digital output code based on the sampled voltage. The analog-to-digital converter system (10) may have a look-up table (20) connected to the analog-to-digital converter (18) for storing a first digital output code in association with the digital input code. A method for calibrating the analog-to-digital converter system (10) is also described.

The application discloses a calibration method for capacitor array mismatch. By adjusting the value of the adjustable reference voltage of the capacitor connected to at least one bit, the value of the adjustable reference voltage is locked when the actual output voltage is equal to the rated output voltage under the corresponding condition, and correct conversion voltage can be obtained even if there is error in the capacitor of some bits in the capacitor array, so that the capacitor array is calibrated.

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

The application discloses a negative voltage generating circuit for a SAR ADC, which comprises a first inverter, a first capacitor, a second capacitor, a discharging switch unit, a charging switch unit, a first resistor and a third capacitor; an external clock signal is input into the first inverter and the second capacitor respectively, the output end of the first inverter is connected with the first capacitor, the first capacitor is further connected with one end of the discharging switch unit and one input end of the charging switch unit respectively, the second capacitor is further connected with the other end of the discharging switch unit and the other input end of the charging switch unit respectively, the first resistor is connected with the output end of the discharging switch unit and the third capacitor, and one end of the third capacitor is an output end to output a negative voltage. The negative voltage generating circuit can directly generate a negative voltage to provide for the SAR ADC, can systematically offset the decision threshold of a comparator, can compensate for the inherent positive offset voltage, and can make the actual jump point of the comparator return to the ideal zero differential input position.

The application discloses a method and system suitable for segment delay measurement of an audio decoder, comprising the following steps: writing periodic waveform data with a preset size into a DAC unit in response to a first excitation signal, and carrying out digital-to-analog conversion on the periodic waveform data through the DAC unit; inputting an audio signal obtained through the digital-to-analog conversion into an ADC unit through an audio line, and carrying out analog-to-digital conversion on the audio signal through the ADC unit; transmitting data obtained through the analog-to-digital conversion to the DAC unit, so as to enter the next cycle of digital-to-analog conversion; determining at least two of a first time, a second time, a third time and a fourth time; and determining at least one of a first complete path delay, a DAC delay, a decoding software delay and an ADC delay according to the at least two of the first time, the second time, the third time and the fourth time. The application can measure the segment delay of audio decoding.

A reference buffer with wide output voltage and current range is provided. A reference buffer includes an error amplifier comprising a first input, a second input, and a first output, wherein the amplifier is configured to generate an output signal indicative of an error between an output reference signal and an internal reference signal. The reference buffer further includes a first voltage follower circuit configured to generate the output reference signal based, at least in part, on the output signal of the error amplifier, wherein the first voltage follower comprises a third input and a second output, and wherein the second output is coupled to the second input of the error amplifier.

The application discloses a linearization calibration circuit and method applied to a pipeline ADC without a sampling and holding structure, and the circuit comprises a signal generation module, a pipeline ADC quantization module and a linear calibration module. The signal generation module is used for generating a pseudo-random signal, and the pseudo-random signal is converted into a dithering signal and then input into the pipeline ADC quantization module. The dithering signal comprises a first dithering signal and a second dithering signal. The pipeline ADC quantization module is used for superimposing the first dithering signal and the second dithering signal on an input signal respectively after the first dithering signal and the second dithering signal are processed through different paths, generating a to-be-calibrated signal, and quantizing the to-be-calibrated signal to obtain an output digital code. The linear calibration module is used for calibrating the to-be-calibrated signal based on a preset weight coefficient, the output digital code and the pseudo-random signal, and obtaining a calibrated signal. The application does not affect the main function of the circuit during calibration, is suitable for the pipeline ADC without the sampling and holding structure, can be operated in the background, has low circuit complexity, and has important significance for improving the linearity of the ADC applied to various communication systems.

The application relates to an MCU built-in ADC error self-calibration method, and relates to electronic technology, and the application comprises the following steps: (a) connecting a VDD power supply to a reference voltage end of an ADC; (b) connecting an input channel of the ADC to an on-chip bandgap reference voltage, sampling the bandgap reference voltage by the ADC to obtain a reference measurement code value D; (c) calculating a VDD actual voltage VDD_actual; (d) calculating a calibration coefficient K and storing the same; (e) connecting an input channel of the ADC to a target analog signal for sampling to obtain an original code value D_raw, and calculating an accurate code value D_corrected of the calibrated target analog signal. By adopting the application, the measurement precision is obviously improved, and the cost and complexity are greatly reduced.

The application relates to a correction method and system of a ring oscillator structure TDC, and relates to the technical field of time-to-digital conversion.The application is used to solve the problem that the sampling circuit of the existing ring oscillator structure TDC may be wrong when sampling the output changing delay unit, leading to inaccurate measured time interval.The application can eliminate the error caused by sampling the delay unit near the signal transmission edge by finding the boundary of the ring oscillator unit state change, i.e. the position of the signal transmission, and correcting the sampled ring oscillator state through logical judgment.

The application discloses a programmable gain amplifier and a control method thereof. The programmable gain amplifier comprises a first differential amplifier circuit, a first set of gain resistors, a second set of gain resistors, a set of sampling capacitors, a first set of switches and a second differential amplifier circuit. The first set of switches is used for selectively coupling the first set of gain resistors between an inverting input voltage and an input of the first differential amplifier circuit, coupling the second set of gain resistors between a common-mode voltage source and the input of the first differential amplifier circuit, and coupling the set of sampling capacitors with respective outputs of the first differential amplifier circuit during a first stage of an offset calibration of the first differential amplifier circuit. Through storage of the sampling capacitors and negative feedback of the second differential amplifier circuit, an offset voltage on the first differential amplifier circuit is offset, so that the influence of the offset voltage on a front-stage amplifier circuit on detection accuracy can be effectively reduced.

The application provides a TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm, relates to the technical field of data transmission, and comprises the following steps: obtaining a first sequence obtained by performing digital-to-analog conversion and downsampling processing on a preset PRBS sequence and a second sequence obtained by performing alignment and downsampling processing on an expected sequence of the preset PRBS sequence; performing correlation operation on the first sequence and the second sequence to obtain a correlation operation result, and adjusting the second sequence to be aligned with the first sequence based on the correlation operation result; the correlation operation result comprises a correlation maximum value and a correlation minimum value for measuring the correlation degree; performing equalization processing on the first sequence by using an FFE algorithm to obtain an error sequence between the first sequence after equalization processing and the second sequence after alignment adjustment, performing bias error calibration and gain error calibration based on an expected value and a standard deviation of the error sequence; and performing time mismatch error calibration based on time errors of channels.

This invention relates to the field of integrated circuit technology, and in particular to an FPGA prototype verification system for a 16-channel clock-interleaved ADC, comprising a host computer and a verification board connected thereto; the verification board has an FPGA core board in the center and 16 ADC acquisition modules arranged compactly around it, the ADC acquisition modules being connected to the FPGA core board via a JTAG interface; the ADC acquisition module includes an ADC module and a clock generation module and a power supply module connected thereto; this invention innovatively introduces a hardware-level correction mechanism based on programmable phase-locked loop phase modulation, effectively reducing the complexity and logic resource overhead of subsequent digital domain signal processing.

This prevents deviations from the optimal operating conditions of the voltage comparator. [Solution] The A / D converter comprises a capacitive D / A converter 1Pa that generates a voltage corresponding to a positive-sequence signal VinP and a reference voltage Vr, a capacitive D / A converter 1Ma that generates a voltage corresponding to an inverse-sequence signal VinM and a reference voltage Vr, a voltage comparator 2 that performs a voltage comparison between the differential inputs of the signals output from the capacitive D / A converters 1Pa and 1Ma, a D / A converter 5 that applies voltage to the non-inverting input terminal and the inverting input terminal of the voltage comparator 2, a determination unit 4 that adjusts the output voltage of the D / A converter 5 according to the comparison result of the voltage comparator 2, and a successive comparison register 3 that outputs a digital value according to the comparison result of the voltage comparator 2. The determination unit 4 adjusts the output voltage of the D / A converter 5 according to the comparison result of the voltage comparator 2 so that the response speed of the voltage comparator 2 is as fast as possible.

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

The application relates to the technical field of mixed signal circuits, and provides a pipeline successive approximation type analog-to-digital converter and method for inter-stage gain error calibration. A background calibration scheme is designed by introducing a gain error detection circuit and a calibration circuit. For inter-stage gain error calibration of any two adjacent sub-SAR ADCs, the gain error detection circuit is used to judge the range of residual error, the inter-stage gain error is monitored, and finally the closed-loop gain of the residual error amplifier is calibrated according to the deviation result determined by the inter-stage gain error, so that the closed-loop gain gradually converges to the ideal gain. Compared with the prior art, the aforementioned background calibration scheme belongs to analog domain calibration and can track the change of the gain error with PVT. By directly correcting the actual analog gain in the circuit, the background real-time calibration of the inter-stage gain error is efficiently and accurately realized, and the precision and stability of the pipeline successive approximation type analog-to-digital converter are effectively improved.

According to various embodiments, an electronic device is described, comprising a device input for connecting an analog signal source, an analog-to-digital converter having an analog-to-digital converter input connected to the device input, an alternating current source configured to supply an alternating current to the analog-to-digital-converter input and a detection circuit configured to store a reference for an amplitude of a voltage signal at the analog-to-digital-converter input caused by the alternating current, receive an output of the analog-to-digital converter, determine the amplitude of the voltage signal at the analog-to-digital-converter input caused by the alternating current by filtering the output of the analog-to-digital converter and output an error signal if the reference for the amplitude differs from the determined amplitude by more than a predetermined threshold.

A test device of an analog-to-digital conversion (ADC) circuit is used to perform an ADC test on the ADC circuit to convert an analog ramp voltage into a digital output signal. The test device includes a controller, a memory, an ADC missing code checking unit and an analog ramp voltage generation circuit controller. The controller is used to generate a control signal. The memory is coupled to the controller and the ADC circuit, respectively, to receive and store the digital output signal according to the control signal. The ADC missing code checking unit is coupled to the controller and the memory, respectively, to check whether the digital output signal has at least one missing code value according to the control signal and to generate a checking result. The analog ramp voltage generation circuit controller is coupled to the controller and the ADC missing code checking unit, respectively, to generate a ramp voltage control signal and a ramp slope control signal according to the control signal and the checking result.

This invention provides a reference-free background calibration method for ultra-high-speed TIADCs based on minimum mean square (RMS) calibration. It employs a decimation-calibration-interpolation calibration mode. The original quantized data is decimated using a specific decimation rate to obtain multiple quantization code sets. A step-by-step grouping calibration algorithm is used based on the number of interleaved channels, selecting the first quantization code set for step-by-step calibration. Each step involves grouping the data and using a dual-channel synchronous detection method based on a binary search to search for the clock jitter value of each channel in the grouped quantized data. Other quantization code sets are then compensated using a first-order Taylor approximation in the digital domain based on the clock jitter value of the first quantization code set. Finally, the compensated multiple quantization code sets are re-interpolated to obtain the calibrated result of the original data. This invention eliminates the need for a reference channel, minimizing the RMS of the detected clock jitter value and thus improving compensation accuracy.

The AD conversion system (1) comprises: an AD converter (10) that converts an analog signal input from an input path (25) into a digital signal and outputs it to an output path (26); a first element section (11) electrically connected to the input path (25); and a second element section (12) electrically connected to the input path (25). The first element section (11) switches between a first operating state and a first stop state, and outputs a first reference voltage in the first stop state. The first operating state is a state in which a voltage corresponding to a detection object is output to the input path (25), and the first stop state is a state in which the output of the voltage corresponding to the detection object is stopped. The detection object is either a detection object voltage or a detection object current. The second element section (12) switches between a second operating state and a second stop state. The second operating state is a state in which a second reference voltage different from the first reference voltage is output to the input path (25), and the second stop state is a state in which the output of the second reference voltage is stopped.

An analog-to-digital converter (ADC) and a method for calibrating a comparator within the ADC are provided. The ADC includes a sampling capacitor array, the comparator, an offset calibration control switch and a control logic, where the offset calibration control switch is coupled between the sampling capacitor array and the comparator. In a sampling phase, the sampling capacitor array samples an input signal, the offset calibration control switch is turned off, input terminals of the comparator are pulled to a same level, and the control logic performs calibration of the comparator according to a comparison result generated by the comparator. In a conversion phase, the offset calibration control switch is turned on, and the control logic output an analog-to-digital conversion result of the input signal according to the comparison result.

To provide an electronic device capable of detecting abnormalities in electronic devices. [Solution] The electronic device 1 comprises an analog-to-digital converter ADC, a digital-to-analog converter DAC, a reference signal generation unit Vref, and a control unit that controls the analog-to-digital converter ADC and the digital-to-analog converter DAC. The control unit performs a first determination process, a second determination process, and an abnormality determination process. The first determination process determines whether the first output value VO1 indicated by the first digital output signal VDO1 is within a predetermined range with respect to a reference value VR. The second determination process determines whether the second output value VO2 is within a predetermined range with respect to a second input value VI2. The abnormality determination process determines whether there is an abnormality in at least one of the analog-to-digital converter, the digital-to-analog converter, and the reference signal generation unit, based on the determination result in the first determination process and the determination result in the second determination process.

The application provides a multi-path sampling clock calibration device, a multi-path interleaving sampling system and a calibration method. The device comprises a phase adjustment unit, a phase detection unit and a control unit. The phase adjustment unit comprises a plurality of adjustment branches. Each adjustment branch adjusts the phase of a received clock signal and outputs the clock signal to a corresponding clock input end of an external sampling circuit. Meanwhile, the clock input end of the external sampling circuit is configured in an impedance mismatch state to reflect part of the signal along the original path. The phase detection unit detects the phase difference of each reflected signal relative to a reference phase based on the reflected clock signals output by each branch. Finally, the control unit generates a control signal according to the phase difference to adjust the phase adjustment amount of each branch, so that the phase of the output sampling clock of each branch remains constant or consistent.

The application discloses a digital-to-analog converter and a current calibration device and method thereof, the current calibration method comprising: comparing the output current of a to-be-calibrated current source of the digital-to-analog converter with the output current of a reference current source and outputting an error signal; generating a calibration control code according to the error signal by using a successive approximation algorithm; and controlling a calibration current source to inject corresponding compensation current into the to-be-calibrated current source according to the calibration control code, wherein at least one redundant bit is included in the calibration bits of the calibration control code, and the value of the redundant bit is a positive integer less than N, wherein N is the number of calibration precision bits. The successive approximation algorithm with the redundant bit is adopted, even if a single misjudgment occurs during calibration, the previous error can be corrected in subsequent low-bit calibration, and the calibration stability and calibration precision are significantly improved. Further, the gradient alignment algorithm is adopted, so that the output current of the calibrated current source presents staggered distribution, and the linearity and the spurious-free dynamic range of the signal can be improved.

Optoelectronic device with at least two optoelectronic circuits (2, 4a, 4b) for transmitting an optical clock signal to an electronic component (40-47, 74a, 74b), a control device (78a, 78b) for controlling the propagation times of the optoelectronic circuits and at least two electronic components (40-47, 74a, 74b), each of the at least two optoelectronic circuits (2, 4a, 4b) with: - a clock generation device (25) for generating the optical clock signal, - a converter element (30-37, 73a, 73b) for converting the optical clock signal into an electrical clock signal supplied to the electronic component (40-47, 74a, 74b), and - an optical line (60, 72a, 72b) from the clock generation device (25) to the converter element (30-37, 73a, 73b), wherein the optoelectronic circuit (2, 4a, 4b) has an adjustable optical element (60, 72a, 72b) for setting a propagation delay between the clock generating device (25) and the electronic component (40-47, 74a, 74b), where the optical line (60, 72a, 72b) is the adjustable optical element (60, 72a, 72b), wherein the transit time is adjustable by changing an optical length of the optical line (60, 72a, 72b), wherein the optical line (60, 72a, 72b) has a plurality of heating elements (61, 79a, 79b) for heating the optical line (60, 72a, 72b), wherein the optical length of the optical line (60, 72a, 72b) is adjustable for setting the transit time by heating the optical line (60, 72a, 72b), and wherein the control device (78a, 78b) is configured to individually control the individual heating elements (61, 79a, 79b) to generate a temperature gradient in order to compensate for a temperature gradient (62) within the optoelectronic device by means of this temperature gradient generated as a counter-gradient.

Systems and methods for monitoring a plurality of operating conditions of a programmable device are disclosed. In some embodiments, the system can include a root monitor including circuitry configured to generate a reference voltage; a plurality of sensors and satellite monitors distributed across the programmable device; and an interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each satellite monitor can be proximate a respective one of the plurality of sensors and coupled to the respective one of the plurality of sensors via a local interconnect. The interconnect system can include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors and can include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors as data packets to the root monitor.

The application relates to a high-gain low-power-consumption comparator with output offset self-calibration, which comprises a sampling switch, a preamplifier, an output offset self-calibration unit and an output dynamic latch. The application adds the output offset self-calibration unit on the basis of a traditional comparator, and mainly comprises six switches (SW5, SW6, SW7, SW8, SW9 and SW10), two offset storage capacitors (C1 and C2) and two NMOS transistors (M9 and M10). The application can improve the gain of the comparator, effectively reduce the offset error of the comparator without obviously increasing the power consumption, ensure the conversion speed, save the chip area, and meet the design requirements of a high-precision low-power-consumption analog-to-digital converter.

The technical scheme of the present application provides a signal sampling circuit, a reference source correction method thereof and an electronic device, which comprises a detection reference source, a backup reference source, a working reference source, a switch module, an analog-digital conversion module and a data control module. The data control module outputs a first control signal group to the switch module, so that the signal output by the detection reference source and the signal output by the backup reference source are both output to the analog-digital conversion module, and are converted into a first digital detection signal and a second digital detection signal by the analog-digital conversion module. The data control module compares the first digital detection signal with a first reference signal and compares the second digital detection signal with a second reference signal; if the first absolute difference and / or the second absolute difference is greater than or equal to the corresponding set threshold, it indicates that the output drift of the working reference source exceeds the limited requirement, and therefore the data control module outputs a second control signal group to the switch module to automatically switch the backup reference source as the reference source of the analog-digital conversion module.