1161results about "Analogue/digital conversion calibration/testing" patented technology

A low power integrated circuit having analog to digital conversion circuitry capable of receiving a plurality of analog signals and converting them to a digital value. The digital value is then transmitted, upon request, over a single wire bus. The accuracy of the analog to digital conversion circuitry can be calibrated via trim codes stored in an onboard EPROM.

The invention relates to a method of preparing signals (X and Y) to be compared to establish predistortion at the input of an amplifier (12), the signals comprising a signal (X) before amplification and a signal (Y) after amplification by said amplifier. Preparation includes time aligning (22) the signal before amplification (X) with the signal after amplification (Y) before using them to establish said predistortion. The invention preferably operates in two stages, namely a stage of coarse time alignment, in which the signal before amplification (X) is subjected to a time delay comprising an integer number of first time units, and a stage of fine time alignment, in which a delay or advance value of a fraction of the first time unit is determined.

A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Various embodiments of the present invention provide systems and methods for mitigating latency in a data detector feedback loop. For example, a method for reducing latency in an error corrected data retrieval system is disclosed. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

An ADC is disclosed comprising at least one folder receiving an input voltage, generating a first output voltage and a second output voltage, and including a plurality of amplifiers and calibration logic for generating bias control signals according to the first output voltage and the second output voltage. Each of the amplifier receives one of a plurality of reference voltages and comprises a bias circuit for providing a bias current to the amplifier based on at least one of a plurality of bias control signals. During calibration, the calibration logic provides the bias control signals to control the bias circuit of each amplifier in the folder such that the first output voltage is substantially the same as the second output voltage.

In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Systems and methods for analog to digital conversion that may be implemented using a digital to analog converter (DAC) to provide negative feedback to cancel signals at the input of an analog to digital converter (ADC), and that may be used to extend the effective dynamic range of an ADC. The systems and methods may be implemented in multi-channel environments.

A method for initializing a counter within a corresponding set of A/D converters of N sets of A/D converters of a single-chip CMOS-type image sensor in order to minimize none uniformity across the N sets of A/D converters is provided. The single chip CMOS type image sensor includes an image sense array having N columns of output lines for outputting N analog signals respectively; and a signal process device for generating N sets of digital signal each of which corresponds to one of N analog signals respectively. The signal process device has N input lines and N sets of A/D converter each of which including a counter for generating one of the N sets of digital signal respectively. The method comprises the steps of applying a predetermined reference voltage at each of N input lines of the signal process device such that a compensation value corresponding to each set of A/D converter is obtained. The method further preloads the counter of each corresponding set of A/D converter with the compensation value corresponding to each set of A/D converter.

An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.

A system and method are provided for adaptively controlling timing in SAR ADC of a sampled analog signal within a conversion period. A state machine maintains a set of SAR states including a sampling state and a plurality of bit conversion states. A reference generator generates a quantization level reference for each of the bit conversion states within a parametric settling time thereof. A comparator compares the sampled analog signal with the quantization level reference over a parametric propagation time for determining a hit value for each hit conversion state. A clock generator adaptively defines signals for clocking the state machine and comparator for each SAR state, thereby adaptively delaying bit determination in each bit conversion state by an integration period not less than the settling time, while adaptively delaying quantization level reference generation for a next bit conversion state by a regeneration period not less than the propagation time.

The invention discloses a sequential approximation analog to digital converter with digital correction and a processing method thereof aiming at the defect of difficult composition manufacture of a coupling capacitor in the traditional sequential approximation analog to digital converter. The sequential approximation analog to digital converter comprises a main DAC (Digital Analogue Converter), acalibration DAC, a comparer, a control circuit and a storage. The sequential approximation analog to digital converter is characterized in that the main DAC comprises a high-K-bit CDAC (Capacitance Digital Analogue Converter) and a low-N-bit CDAC. Introduced system errors and capacitance matching errors are digitally corrected and eliminated, error voltages corresponding to capacitors in the high-K-bit CDAC are quantized and stored in the storage, and two-digit 0 are added behind the tail of the quantized residual error voltage digital code and participate in the calculation of the error voltages. When normal conversion is carried out, the error voltage digital codes are accumulated and then last two digits are discarded, the remain digital codes are used as the input of the calibration DAC, thus the accuracy of the analog to digital converter is improved.

The A/D converter device includes a comparing section and an abnormality judging section. The comparing section compares a voltage of its signal transfer line connected between its input multiplexer and its A/D converting section through its sample-hold section with a predetermined abnormality judging voltage. The abnormality judging section is configured to apply a reference voltage to the signal transfer line in synchronization with an A/D conversion cycle thereof on condition that its A/D converting operation thereof is not interrupted, and to determine presence of abnormality in the A/D converter device if an comparison result of the comparing section does not match an expected value corresponding to the reference voltage.

Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.

An analog input signal obtained from an analog sensor group 104A and first and second calibration voltages obtained by high-precision voltage-dividing resistors are successively selected by a multiplexer, digitally converted through an AD converter and then input to a microprocessor. The microprocessor calculates a collinear approximate coefficient based on the first and second calibration voltages in cooperation with a program memory, and corrects the digital conversion value to the analog input signal by using the approximate coefficient, thereby correcting a linear error of the conversion characteristic of the AD converter. In the calculation of the approximate coefficient, upper and lower limit check is executed on measurement values and calculation coefficients, and also plural calculation results are averaged to enhance the precision.

A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

A pipelined analog-to-digital converter (ADC) is calibrated to enable production of an n-bit digital output representing an n-2 bit binary word, where "n" is a selected large positive integer, for example without limitation on the order of ten (10). In an analog-to-digital converter (ADC) having a plurality stages, each stage includes a stage input connection, a stage output connection, and a capacitor circuit including first and second predetermined capacitors (C1 and C2) and a variable capacitance calibration capacitor (Ccal). The first and second capacitors and the variable capacitance calibration capacitor are connected to each other at a capacitor common node. An amplifier input connection is connected to a capacitor common node. A comparator input connection (CIC) is connected to a stage input connection. A track and hold circuit (THC) is coupled to an amplifier output connection, and a source follower circuit (SF) is connected to a stage output connection.

The invention discloses a self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter, comprising an M channel TIADC, a signal recombination, a digital reference signal memorizer, a simulated reference signal generator, a self-adaptive reconstruction filter bank, a clock generation circuit and a subtraction device. Signals after passages are reconstructed are used to correct each passage instead of single correction on each passage, thereby solving the problem that when an input signal bandwidth is larger than the Nyquist frequency of each passage ADC, the time error can not be corrected due to aliasing. Each self-adoptive reconstruction filter is divided into a plurality of sub-filters for concurrent working, thereby not improving the requirement of thetreatment speed for a self-adoptive correcting filter while realizing the effect of signal recombination and ensuring the practicability of the hardware of the structure of the invention. A digital reference signal is internally installed in the device and is taken as a target to carry out the self-adoptive correction, pre-measuring or calculating a passage mismatch error is not needed, and the source of the error is not needed to be discriminated so that various mismatch errors can be corrected.

The invention provides a successive approximation analog-digital converter and an analog-digital conversion method based on digital domain self-correcting. The successive approximation analog-digital converter comprises a CDAC, a comparator, an SAR control logic circuit, a correction control logic circuit, a storage, an adder and a clock circuit; a differential structure is adopted in the CDAC; capacitor arrays of the CDAC respectively form a high-M-level CDAC and a low-L-level CDAC; on the basis of a capacitor array reusing thought, mismatching errors of various capacitors in the high-M-level CDAC capacitor array are detected by reusing the low-L-level CDAC in a self-correcting stage; detected error values are quantized; error voltage is converted into an error code to output; the output error code is output into the storage; after mismatching error detection and quantization are completed, digital conversion of an input analog signal begins to perform; an original code is output, and operated with the error code at the corresponding bit called from the storage; therefore, the final output codeword after being corrected is obtained; and thus, the linearity of the SAR ADC is increased.

The invention discloses a multi-analog-to-digital converter (ADC) high-speed time alternating acquisition system with a data synchronous identification function. Phase relation between multiple ADC data synchronous clocks is measured by adding a test pulse forming module, a high-precision time interval measuring unit, a data feedback control module and a data sequence identification module, and the sequence of sampled data is fed back and controlled according to a measuring result, so real-time correct splicing of parallel time alternating sampling data sequences is realized, reliable guarantee is provided to the processing of sampled data at the rear end, the stable operation of the system is effectively ensured, and the technology lays a firm foundation for construction of a multi-ADC acquisition system with higher sampling rate.

System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.

A calibratable analog-to-digital converter system with a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal. Calibration logic is responsive to the digital signals output by the N ADCs and is configured to calibrate each of the ADCs based on the digital signals output by each ADC.

A system and method are provided for adaptive self-calibration to remove sample timing error in time-interleaved ADC of an analog signal. A plurality of ADC channels recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples. A timing skew detection unit is coupled to the ADC channels, which generates for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment. Each timing skew factor is generated based adaptively on the output samples for a selective combination of segments including at least one preceding and at least one succeeding sample segment. A plurality of timing control units respectively coupled to the ADC channels adjust time delays for the sampling clock within respective sample segments responsive to the timing skew factors, thereby substantially aligning the sample segments with the sampling clock.

The invention discloses a digital background calibration circuit used for a high-speed and high-precision pipelined analog-to-digital converter. The digital background calibration circuit comprises a pseudo random number generator, pipelined circuits with calibration functions and a digital background calibration engine. Based on the structure of the traditional pipelined analog-to-digital converter, a primary-stage pipelined circuit and a secondary-stage pipelined circuit are modified in the circuit disclosed in the invention to realize the injection of random signals and the digital background calibration engine is used to associate the random signals so as to realize the real-time extraction and compensation of error information, thereby avoiding the influence of irrational factors of the traditional pipelined analog-to-digital converter (such as capacitor mismatching, limitations of operational amplifier gains and the like) on the conversion precision of the analog-to-digital converter. The technology can lower the design difficulty of an analog circuit and ensure the performance of a system. At the same time, because of the simple algorithm and the low implementation complexity, the calibration circuit can be used to effectively reduce the area of the chip and lower the power consumption of the system, thereby being especially applicable to a high-speed system.

The invention provides a multi-channel time-interleaved analog-digital converter. The multi-channel time-interleaved analog-digital converter is characterized in that a clock generation circuit generates a work clock for the converter; an ADC channel set including M ADC channels is configured into a time-interleaved structure; the ADC channels operate in turns in a time division multiplexing under control of the clock generation circuit, a high-speed analog input signal is converted into M low-speed digital output signals, and M is an integer not smaller than 2; a channel mismatch detection circuit detects timing sequence mismatch errors of signals output by the M ADC channel, in real time, so that a timing sequence mismatch parameter of each ADC channel relative to a reference ADC channel is acquired; a signal compensation and reconstruction circuit compensates and reconstructs the digital output signals output by the ADC channel set according to the timing sequence mismatch errors that the channel mismatch detection circuit detects; a signal combiner circuit combines the M low-speed output signals subjected to channel compensation and generated by the signal compensation and reconstruction circuit, and finally a high-speed digital output signal is obtained.

The invention discloses a digital calibration method for a high-precision SAR ADC (successive approximation register analog to digital converter). The method comprises the following steps of (1) designing of a calibration DAC (digital to analog converter), digitalizing the error voltage of each capacitor in the high segment of a main DAC, and carrying out digital to analog conversion on the processed calibration codes; (2) designing of digital calibration time sequence, obtaining the calibration codes, maintaining sampling, and gradually converting. The method is applied to the high-precision SAR ADC, and a capacitor array of the high segment in the sectional main DAC is subjected to digital calibration, so the mismatch of the capacitors caused by parasitic capacitors and the process manufacturing error is reduced, the problem of unable realizing of precise double relationship due to the mismatch of the adjacent capacitors in the high segment is greatly corrected, and the precision of the SAR ADC is effectively improved.

A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.