685results about "Analogue/digital conversion calibration/testing" patented technology

The invention relates to the technical field of radio frequency signal processing, and discloses a digital filtering repair method and system for signal distortion, and the method comprises the steps: obtaining a frequency domain amplitude-frequency response and a phase response; constructing a phase compensation amount by adopting piecewise polynomial fitting and a phase inversion mechanism; a complex number logarithm domain mapping mechanism is adopted to execute composite frequency response inversion; constructing a switchable hybrid digital filter with an amplitude path and a phase path coupled in parallel; multi-band adaptive scheduling is executed; and outputting the radio frequency baseband signal stream. The technical problems that in the prior art, frequency response nonlinear distortion in a broadband range cannot be dealt with by adopting a fixed template or a single-path filter, and particularly, a high-precision and low-delay dynamic compensation effect cannot be realized in a scene that multi-band coupling interference exists in a radio frequency ADC channel with the bandwidth exceeding 800MHz are solved. Due to the fact that the switchable hybrid digital filter is constructed, accurate modeling and flexible recovery of distortion characteristics in broadband signals are achieved.

The invention provides a sampling compensation circuit, a voltage sampling device and radio frequency power supply equipment, and relates to the technical field of power electronics, the sampling compensation circuit is used for compensating a sampling voltage value obtained by a voltage sampling circuit, the voltage sampling circuit at least comprises a sampling diode, the sampling diode is used for rectifying a to-be-detected alternating current signal, and the to-be-detected alternating current signal is sent to the sampling compensation circuit. Therefore, a sampling voltage signal is obtained. The sampling compensation circuit comprises a voltage drop acquisition unit and a sampling compensation unit. The first input end and the second input end of the voltage drop obtaining unit are used for being connected with the first end and the second end of the sampling diode respectively, and the voltage drop obtaining unit is used for obtaining a voltage difference signal. The sampling compensation unit is used for acquiring a sampling voltage signal output by the second end of the sampling diode and a voltage difference signal output by the first output end of the voltage drop acquisition unit, and compensating the sampling voltage signal according to the voltage difference signal to obtain a corrected sampling signal. According to the invention, a more accurate sampling voltage value can be obtained.

The invention relates to the technical field of semiconductor integrated circuits, and discloses a bandwidth mismatch calibration system and method of a time-interleaved architecture ADC (Analog to Digital Converter). The system comprises N sub-ADCs, N bandwidth adjustment units and a controller. Firstly, a unified calibration signal is input into all sub-ADCs, and each sub-ADC samples the transition edge of the signal. The controller detects and determines a transition point error of each sub-ADC at the transition edge based on the sampling output of each sub-ADC. The controller calculates bandwidth adjustment code words for the corresponding sub-ADCs based on the difference between the error and a preset target value. The code word is used for driving the bandwidth adjusting unit to adjust the bandwidth of the corresponding sub-ADC, so that the bandwidths of all the sub-ADCs tend to be consistent through closed-loop feedback, and automatic and accurate calibration of bandwidth mismatch is realized.

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

Certain aspects of the present disclosure provide techniques and apparatus for digital-to-analog conversion. An example apparatus generally includes a digital-to-analog converter (DAC), an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC, and a controller coupled to the DAC and the IADC. The controller is configured to determine a direct current (DC) offset associated with the DAC using the IADC and control a mission-mode digital input signal of the DAC based on the DC offset.

The invention discloses a foreground calibration circuit for an input offset voltage of an SAR ADC comparator. The foreground calibration circuit comprises a power supply input circuit, an input geminate transistor circuit, a latch comparator, an SAR successive approximation register and a Res DAC resistance voltage division type digital-to-analog converter. The output end of the power input circuit is electrically connected with the power end of the input geminate transistor circuit; an analog input signal VIN and a reference voltage signal VREF are input into the input end of the input geminate transistor circuit, and the output end of the input geminate transistor circuit is electrically connected with two input ends of the latch comparator; the two output ends of the latch comparator are electrically connected with the input end of the SAR successive approximation register, and the output end of the SAR successive approximation register is electrically connected with the input end of the Res DAC resistance voltage division type digital-to-analog converter; the output end of the Res DAC resistance voltage division type digital-to-analog converter outputs a CALIP signal and a CALIN signal to a grid electrode of an adjusting tube in the input geminate transistor circuit, so that the adjusting tube generates compensation current to compensate the current difference of two input geminate transistors in the input geminate transistor circuit, and offset voltage is calibrated.

This invention provides a semiconductor device that automatically corrects the conversion value of an analog-to-digital converter, a method for correcting the conversion value of an analog-to-digital converter, and a program for doing so. [Solution] The analog / digital converter 1 outputs a converted value DS obtained by converting the input signal IN from analog to digital. The non-volatile memory 11 stores multiple correction values. The correction circuit 21 selects a correction value from the multiple correction values ​​according to the situation, depending on the situation affecting the offset on the converted value DS of the analog / digital converter 1, and outputs an output value OUT with the offset on the converted value DS corrected based on the selected correction value.

The invention relates to the field of high-speed serial interface chips, and discloses an error calibration method of an ultra-high-speed phase interpolator. The method comprises the steps of amplitude calibration, edge searching, reference clock delay calibration, multi-phase cyclic calibration, linear interpolation and the like, a reference clock rising edge zero crossing point is used as a high-precision time reference, delay control words of a selected discrete phase are adjusted one by one, a mapping lookup table covering a full-phase range is generated through linear interpolation, and the time delay control words of the selected discrete phase are adjusted one by one. And compensation of the nonlinear error of the phase interpolator is realized. According to the invention, high-precision linearity calibration can be completed before normal operation of the chip, the clock recovery precision is significantly improved, the nonlinear error is reduced from + / -1.5 LSB to + / -0.5 LSB, the error rate of the system is reduced, and the power consumption and the area overhead are low.

Disclosed is a two-stage successive approximation register analog to digital converter based on a difference and differential amplifier, including a first-stage sub-ADC, a difference and differential amplifier, and a second-stage sub-ADC connected in sequence. The first-stage sub-ADC and the second-stage sub-ADC each include capacitor arrays and comparators. The difference and differential amplifier includes a transconductance amplifier GM1, a transconductance amplifier GM2, a resistance load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistance load R, and the transconductance amplifier GM2 form a negative feedback loop. The disclosure adjusts the gain of the amplifiers through the proportional resistors R1 and R2, so that higher conversion accuracy can be achieved.

The invention discloses a DAC output error correction method based on digital compensation, and the method comprises the steps: collecting the amplitude deviation, phase deviation and time sequence jitter data of a DAC output signal through a quantum sensing DAC calibration analysis platform, and constructing a multi-dimensional error original data set; calling an operational amplifier imbalance dynamic coupling prediction model to analyze a coupling relationship, and extracting dynamic association features; separating harmonic components and screening error contribution factors based on a broadband DAC harmonic distortion correction model; calculating a gradient change rule and an extreme point position by adopting a differential nonlinear gradient correction model; and integrating the characteristics and the parameters to construct a digital compensation parameter matrix, and dynamically adjusting an output code value through real-time digital modulation to realize error correction. According to the method, dynamic association and distribution characteristics of multi-source errors are accurately captured through multi-model collaborative operation and full-process closed-loop processing, multi-dimensional error synchronous correction is achieved, and DAC output precision and working condition adaptability are improved.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and / or calibration based on signal measurements taken at the output stage of a device comprising the DAC.

The invention discloses a foreground and background calibration fused capacitor mismatch calibration method and system, and the method comprises the steps: carrying out foreground digital calibration after a chip is powered on, and comprises the steps: obtaining an error voltage; quantizing the obtained error voltage to generate a corresponding error code word; the weight of foreground calibration is obtained; the method comprises the following steps of: generating a pseudorandom sequence and injecting the pseudorandom sequence into an input signal of an ADC (Analog to Digital Converter) when an ADC (Analog to Digital Converter) enters normal work; carrying out weighted summation on the digital code word quantized and output by the ADC and eliminating the interference of the pseudo-random sequence from the digital code word; and carrying out correlation calculation on the weighted summation result after the interference of the pseudo-random sequence is eliminated and the pseudo-random sequence to obtain a calibration coefficient, and carrying out iterative calculation on the capacitance weight according to the calibration coefficient. The advantages of foreground calibration and background calibration are fully combined, so that a better calibration effect is achieved.

The analog-to-digital converter system (10) includes a digital-to-analog converter (32) for generating a calibration voltage based on a digital input code, and an analog-to-digital converter (18) connected to the digital-to-analog converter (32) for receiving the calibration voltage from the digital-to-analog converter (32), receiving a sampled voltage, generating a digital output code based on the calibration voltage, and generating a digital output code based on the sampled voltage. The analog-to-digital converter system (10) may have a look-up table (20) connected to the analog-to-digital converter (18) for storing a first digital output code in association with the digital input code. A method for calibrating the analog-to-digital converter system (10) is also described.

Systems and methods for providing multiple stable reference voltages are disclosed. In one aspect, a bandgap reference circuit generates a first reference voltage, which is calibrated with an adjustable resistor bank. Settings for this adjustable resistor bank may be stored in a memory and reused at multiple locations with theoretically identical resistor banks for other circuits requiring reference voltages. Recognizing that there may be voltage network variations induced by distances from bandgap reference circuit, process variations between resistor banks, or the like, each resistor bank may be separately calibrated, and settings stored in memory. By providing separate resistor banks for each location that needs a reference voltage, the need for duplicative and space intensive bandgap reference circuits is minimized. Further, by providing separate resistor banks, variations in the local voltage are minimized providing more stable and reliable operation of circuits in the die.

The present disclosure relates to a circuit and method for calibrating a digital-to-analog converter. A digital-to-analog converter (DAC) calibration system includes a DAC configured to convert a digital input to an analog input, a detector configured to measure analog outputs of the plurality of DAC unit cells and combine the analog outputs to generate a total analog output signal, and a calibration engine. The calibration engine is configured to calibrate the DAC.

The invention discloses a borrowing type successive approximation analog-to-digital converter adopting a back propagation neural network for calibration. The borrowing type successive approximation analog-to-digital converter comprises a system composed of a positive and negative capacitance digital-to-analog converter adopting a three-stage split bridge type capacitor array, a bootstrap sampling switch, an automatic return-to-zero comparator, an SAR logic control unit, an original-to-binary module and a BPNN calibration engine. Bootstrap sampling switches are respectively arranged at the tail ends of the positive and negative capacitance digital-to-analog converters, a comparator is connected with the output ends of the two, and the output is connected with an SAR logic control unit; the original-to-binary module converts the code generated by the SAR logic control unit into a binary code; and a BPNN calibration engine receives the code and performs calibration calculation by using a trained back propagation neural network model. By implementing the converter disclosed by the invention, hardware implementation can be simplified while high performance is ensured, so that the ADC realizes efficient and accurate signal conversion under a 180-nanometer BCD process, and power consumption and cost are reduced.

The present disclosure relates to a digital-to-analog conversion device and method with signal calibration mechanism. A digital-to-analog conversion device with signal calibration mechanism. A first conversion circuit generates a first analog signal to an echo path according to an input digital signal. A second conversion circuit generates a second analog signal to the echo path according to the input digital signal and a pseudo noise digital signal. An echo transmission circuit processes the signals of the echo path to generate an echo signal. First and second calibration circuits generate first and second calibration signals. A calibration parameter operation circuit operates according to a difference between the echo signal and the first and second calibration signals and related path information to generate first and second offset values. The first and second calibration circuits make the first and second response coefficients converge according to the echo signal, and update first and second code word offset tables according to the first and second offset values.

The present application provides an analog-to-digital converter including a sample-and-hold circuit configured to periodically sample and hold an analog input signal; a first level sub-analog-to-digital converter configured to convert the analog input signal into a first digital signal, convert the first digital signal into a first voltage signal, and perform differential processing between the analog input signal and the first voltage signal to obtain a second voltage signal; a first processing circuit configured to clock-synchronize and periodically delay the first digital signal to obtain a second digital signal; an inter-stage amplifier realized using an open-loop structure and configured to amplify and process the second voltage signal to obtain a third voltage signal; a second level sub-analog-to-digital converter configured to convert the third voltage signal into a third digital signal; a second processing circuit configured to clock-synchronize the third digital signal to obtain a fourth digital signal; and an adder configured to merge and add the second digital signal, which is a higher-order codeword, and the fourth digital signal, which is a lower-order codeword, to obtain a digital output signal, and a method for calibrating the inter-stage gain.

The invention discloses an error compensation method of an analog-to-digital converter, a digital device and a controller, and the method comprises the steps: obtaining a to-be-compensated digital quantity and two reference digital quantities, the to-be-compensated digital quantity is obtained through the conversion of an analog signal through the analog-to-digital converter, and the reference digital quantities are obtained through the conversion of a reference signal through the analog-to-digital converter; obtaining a linear error based on the plurality of sampling values of each reference digital quantity under the condition that the reference digital quantity is within a preset effective range; and compensating the digital quantity to be compensated according to the linear error to obtain a compensated digital quantity. According to the invention, the accuracy in the ADC analog-to-digital conversion process can be effectively improved.

The embodiment of the invention discloses a chip detection method and device, electronic equipment and a storage medium, and can solve the problem that the detection of a digital-analog chip is not accurate enough due to the fact that an existing chip possibly cannot reflect related functions in the digital-analog chip very accurately. Obtaining original simulation data of the to-be-tested chip; based on the original simulation data, a target test chip is run, the target test chip is a chip obtained after the programmable integrated circuit chip simulates the function of the current version of the chip to be tested, and the current version is a version after version iteration; in the running process of the target test chip, running indexes are collected, and the detection result of the to-be-tested chip is determined according to the running indexes.

A self-calibration digital-to-analog converter (DAC) and a calibration method for DAC are provided. The circuit includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a correction switching circuit. In normal operation mode, the resistor circuit receives the common voltage for conversion. In correction mode, the circuit performs self-correction in a sampling time and a comparison time. During the sampling time, the resistor circuit receives the reference voltage and first correction data, and the buffer amplifier input samples the voltage. During the comparison time, the resistor circuit receives the common connection voltage and second correction data, and the fine-tuning circuit adjusts the correction data until the buffer amplifier output voltage flips and records the correction value corresponding to the second correction data. With this self-correction mechanism, the circuit can output theoretically correct digital-to-analog conversion results under the reference voltage and common connection voltage.

The invention relates to a module (1) for sampling an analog signal (S) and to a method for detecting errors when sampling an analog signal (S). In the method, the completion of each sampling of the analog signal (S) is reported to a processor (5) of the module (1) by means of a report signal (M). The processor (5) respectively generates processor signals (P) at equally spaced module time points with respect to the module time. A reference duration, which is the time interval between the generation of the processor signal (P) and the next reception of the report signal (M) by the processor (5) after the generation of the processor signal (P), is measured once. For each subsequent processor signal (P), a signal difference duration is measured, which is the time interval between the generation of the processor signal (P) and the next reception of the report signal (M) by the processor (5) after the generation of the processor signal (P). When the deviation between the signal difference duration and the reference duration exceeds the tolerance duration, an error is deduced.

The invention relates to a successive approximation register analog-to-digital converter with comparator performance calibration. Systems and methods relate to devices including, but not limited to, SAR ADCs. The apparatus includes a first digital-to-analog conversion (DAC) circuit including a first capacitor. The digital-to-analog conversion (DAC) circuit is configured to adjust a first input voltage in response to a first control signal. The apparatus also includes a first comparator configured to receive an adjusted input voltage from the digital-to-analog conversion (DAC) circuit. The first control signal is provided in response to a target input voltage and a sensed input voltage and adjusts the first input voltage using the first capacitor.

This invention provides a reference voltage buffer circuit and calibration method for a high-precision analog-to-digital converter (ADC). The circuit includes a first operational amplifier whose inverting input is connected to a reference voltage, and whose output is fed back to the non-inverting input via a first driving transistor and a voltage divider circuit. A second operational amplifier's non-inverting input is connected to a first voltage divider node, its inverting input is connected to a second voltage divider node, and its output is connected to the gates of several third driving transistors and a second driving transistor. The drains of the third driving transistors are all connected to the first voltage divider node via switches. The width-to-length ratios of the second driving transistors and the several third driving transistors are linearly related. The switches are all input with logic control signals to control their states for linear calibration of the reference voltage. This invention uses binary encoding to control the switch states for linear calibration of the output reference voltage and significantly reduces the total resistance by designing a linear relationship between the resistors, thus reducing chip area and cost.

Various techniques are described for correcting distortion in an analog input signal after digitization in a receiver signal chain. The techniques include a system that stores concatenated distortion correction terms, allowing for efficient data handling and processing. The techniques further include a system that has a smaller number of replica memories compared to primary memories, which store operational data. The replica memories are updated with new data and may be swapped with primary memories to update them without interrupting system operations. The techniques further include a dither system that uses two memories to store and process the dithered signals, which are then combined to produce a noise-corrected digital output. The techniques further include a system to correct distortions in analog input signals processed through multiple parallel paths.

The application discloses a successive approximation type analog-digital conversion device based on a composite dielectric grid and a working method, and belongs to the technical field of semiconductor devices, analog-digital conversion and storage-computation integration. The device is divided into coupling units with different areas according to binary values, and then the control of each weight coupling unit is realized through binary weights. The device does not need large MIM capacitors and complex metal switch trees, thereby reducing area consumption. The on-off characteristics of a semiconductor are utilized, and whether the readout transistor is turned on or not is taken as a comparison result to realize the step-by-step comparison between a two-part interval and an input quantity, thereby avoiding the comparison circuit logic of a circuit stage, so that the power consumption of a quantization unit is significantly reduced. In addition, the device provided by the application has a simple structure, can be extended in a row or column direction in parallel according to actual conditions, and mismatch can be eliminated through code table compensation. The device can be used as an on-chip ADC front end and can also be embedded in a pixel / storage-computation unit as a local quantizer, and has strong versatility.

The application discloses a TI-ADC mismatch error calibration method based on a full connection neural network. First, a TI-ADC mismatch error model is established, error signal data is generated, and a neural network training data set is constructed by using the data; then, a full connection neural network is built, and the training data set is used for training the full connection neural network to obtain a trained neural network; subsequently, the trained neural network is tested by using the error model to generate a TI-ADC signal with mismatch error, the output of the trained neural network is subjected to fast Fourier transform to obtain a frequency spectrum and a performance index; according to the test result, the network training parameters are adjusted, including the training iteration number, the data batch processing size, the loss function type, the training optimizer, the learning rate and the like, and the neural network is trained again; the training is repeatedly performed until the test result reaches an expected target; the algorithm is novel, the process is simple, and the overall performance of the TI-ADC can be effectively improved.

The application discloses a DAC double-channel synchronous output automatic calibration method and system based on FPGA, relates to the technical field of multi-channel data synchronization, and comprises the following steps: calculating a clock delay calibration value according to a link delay value read from the register of a DAC chip, and configuring the register of the DAC chip according to the clock delay calibration value; calculating a data dynamic delay compensation value according to the phase difference value between the SYSREF phase measurement values read from two DAC chips; calculating a fixed delay compensation value corresponding to the two DAC chips according to the waveform phase difference time of two-channel test data; calculating a data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value; and performing delay processing on the data needed to be sent to the two DAC chips by using the data delay compensation value. The application can automatically complete the DAC synchronous output calibration of double channels, and does not need to compile FPGA programs when producing double-channel board cards, thereby improving the production efficiency.