Eureka-AI is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Eureka AI

1161results about "Analogue/digital conversion calibration/testing" patented technology

Sequential approximation analog to digital converter with digital correction and processing method thereof

The invention discloses a sequential approximation analog to digital converter with digital correction and a processing method thereof aiming at the defect of difficult composition manufacture of a coupling capacitor in the traditional sequential approximation analog to digital converter. The sequential approximation analog to digital converter comprises a main DAC (Digital Analogue Converter), acalibration DAC, a comparer, a control circuit and a storage. The sequential approximation analog to digital converter is characterized in that the main DAC comprises a high-K-bit CDAC (Capacitance Digital Analogue Converter) and a low-N-bit CDAC. Introduced system errors and capacitance matching errors are digitally corrected and eliminated, error voltages corresponding to capacitors in the high-K-bit CDAC are quantized and stored in the storage, and two-digit 0 are added behind the tail of the quantized residual error voltage digital code and participate in the calculation of the error voltages. When normal conversion is carried out, the error voltage digital codes are accumulated and then last two digits are discarded, the remain digital codes are used as the input of the calibration DAC, thus the accuracy of the analog to digital converter is improved.

Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter

InactiveCN101888247AAvoid problems that are difficult to convert to hardware circuitsThere is no problem of implementation deviationAnalogue-digital convertersAnalogue/digital conversion calibration/testingTime errorDigital down converter
The invention discloses a self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter, comprising an M channel TIADC, a signal recombination, a digital reference signal memorizer, a simulated reference signal generator, a self-adaptive reconstruction filter bank, a clock generation circuit and a subtraction device. Signals after passages are reconstructed are used to correct each passage instead of single correction on each passage, thereby solving the problem that when an input signal bandwidth is larger than the Nyquist frequency of each passage ADC, the time error can not be corrected due to aliasing. Each self-adoptive reconstruction filter is divided into a plurality of sub-filters for concurrent working, thereby not improving the requirement of thetreatment speed for a self-adoptive correcting filter while realizing the effect of signal recombination and ensuring the practicability of the hardware of the structure of the invention. A digital reference signal is internally installed in the device and is taken as a target to carry out the self-adoptive correction, pre-measuring or calculating a passage mismatch error is not needed, and the source of the error is not needed to be discriminated so that various mismatch errors can be corrected.

Digital background calibration circuit

The invention discloses a digital background calibration circuit used for a high-speed and high-precision pipelined analog-to-digital converter. The digital background calibration circuit comprises a pseudo random number generator, pipelined circuits with calibration functions and a digital background calibration engine. Based on the structure of the traditional pipelined analog-to-digital converter, a primary-stage pipelined circuit and a secondary-stage pipelined circuit are modified in the circuit disclosed in the invention to realize the injection of random signals and the digital background calibration engine is used to associate the random signals so as to realize the real-time extraction and compensation of error information, thereby avoiding the influence of irrational factors of the traditional pipelined analog-to-digital converter (such as capacitor mismatching, limitations of operational amplifier gains and the like) on the conversion precision of the analog-to-digital converter. The technology can lower the design difficulty of an analog circuit and ensure the performance of a system. At the same time, because of the simple algorithm and the low implementation complexity, the calibration circuit can be used to effectively reduce the area of the chip and lower the power consumption of the system, thereby being especially applicable to a high-speed system.
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products