3200results about "Analogue/digital conversion calibration/testing" patented technology

A low power integrated circuit having analog to digital conversion circuitry capable of receiving a plurality of analog signals and converting them to a digital value. The digital value is then transmitted, upon request, over a single wire bus. The accuracy of the analog to digital conversion circuitry can be calibrated via trim codes stored in an onboard EPROM.

The invention relates to a method of preparing signals (X and Y) to be compared to establish predistortion at the input of an amplifier (12), the signals comprising a signal (X) before amplification and a signal (Y) after amplification by said amplifier. Preparation includes time aligning (22) the signal before amplification (X) with the signal after amplification (Y) before using them to establish said predistortion. The invention preferably operates in two stages, namely a stage of coarse time alignment, in which the signal before amplification (X) is subjected to a time delay comprising an integer number of first time units, and a stage of fine time alignment, in which a delay or advance value of a fraction of the first time unit is determined.

A circuit and method measure the output voltage of a CMOS pixel in a manner that substantially reduces all columnar pattern noise due to mismatches in the signal processing circuits including the correlated double sampling amplifiers and A/D converters. The circuit includes a test switch, operatively connected between a reference voltage source and a correlated double sampling amplifier, for applying a test voltage from the reference voltage source when the state of the test switch is ON to the correlated double sampling amplifier. The reference voltage source produces a voltage corresponding to a full-scale voltage level to enable the determination of a gain error in the correlated double sampling amplifier and/or A/D converter; a voltage corresponding to ground to enable the determination of an offset error in the correlated double sampling amplifier and/or A/D converter; and a plurality of analog voltages ranging from analog ground to a full-scale voltage level to enable the determination of non-linearity errors in the A/D converter.

A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Embodiments of the present invention provide a method and apparatus for compressed sensing. The method generally comprises forming a first compressed sensing matrix utilizing a first set of time indices corresponding to a first sampling rate, forming a second compressed sensing matrix utilizing a plurality of frequencies and a second set of time indices corresponding to a second sampling rate, forming a combined compressed sensing matrix from the first compressed sensing matrix and the second compressed sensing matrix, and reconstructing at least a portion of the input signal utilizing the combined compressed sensing matrix. The first and second sampling rates are each less than the Nyquist sampling rate for the input signal.

Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and/or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.

Various embodiments of the present invention provide systems and methods for mitigating latency in a data detector feedback loop. For example, a method for reducing latency in an error corrected data retrieval system is disclosed. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

An ADC is disclosed comprising at least one folder receiving an input voltage, generating a first output voltage and a second output voltage, and including a plurality of amplifiers and calibration logic for generating bias control signals according to the first output voltage and the second output voltage. Each of the amplifier receives one of a plurality of reference voltages and comprises a bias circuit for providing a bias current to the amplifier based on at least one of a plurality of bias control signals. During calibration, the calibration logic provides the bias control signals to control the bias circuit of each amplifier in the folder such that the first output voltage is substantially the same as the second output voltage.

In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

A method of compensating for nonlinear distortions in a digital signal comprises receiving the digital signal, generating a nominal phase shifted signal based on the digital signal, generating a modeled distortion signal based on the digital signal and the nominal phase shifted signal, subtracting the modeled distortion signal from the digital signal, and generating a compensated signal. A compensating system comprises an input interface configured to receive a digital signal having nonlinear distortion, and a distortion model coupled to the interface, configured to generate a nominal phase shifted signal based on the digital signal, generate a modeled distortion signal based on the digital signal and the nominal phase shifted signal, subtract the modeled distortion signal from the digital signal, and generate a compensated signal.

Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Systems and methods for analog to digital conversion that may be implemented using a digital to analog converter (DAC) to provide negative feedback to cancel signals at the input of an analog to digital converter (ADC), and that may be used to extend the effective dynamic range of an ADC. The systems and methods may be implemented in multi-channel environments.

A digital direct conversion receiving apparatus, including: a phase conversion unit to down-convert a Radio Frequency (RF) signal into a plurality of sample signals, and generate a certain phase difference among the plurality of sample signals when the RF signal is down-converted; and a variable complex gain unit to remove an image component from the plurality of sample signals using the generated phase difference.

A method for initializing a counter within a corresponding set of A/D converters of N sets of A/D converters of a single-chip CMOS-type image sensor in order to minimize none uniformity across the N sets of A/D converters is provided. The single chip CMOS type image sensor includes an image sense array having N columns of output lines for outputting N analog signals respectively; and a signal process device for generating N sets of digital signal each of which corresponds to one of N analog signals respectively. The signal process device has N input lines and N sets of A/D converter each of which including a counter for generating one of the N sets of digital signal respectively. The method comprises the steps of applying a predetermined reference voltage at each of N input lines of the signal process device such that a compensation value corresponding to each set of A/D converter is obtained. The method further preloads the counter of each corresponding set of A/D converter with the compensation value corresponding to each set of A/D converter.