74 results about "Time interleaved" patented technology

The invention relates to the technical field of offshore data monitoring, and discloses an offshore data monitoring method based on a wireless communication system, and the method comprises the following steps: S1, data collection: obtaining offshore monitoring data of a target; s2, data preprocessing: performing format conversion, duplicate removal, time alignment and data interpolation processing on the data acquired by the data acquisition; s3, data fusion: matching and fusing the processed data based on a time interleaving algorithm and a spatial clustering algorithm; s4, performing target tracking, and performing target trajectory prediction by adopting a Kalman filtering method under the condition of target data missing; and S5, monitoring output, generating a fusion data set, and outputting dynamic information of the target. Through combination of deep learning target identification, LSTM network state prediction and an efficient wireless communication technology, more accurate marine target monitoring, stable real-time data transmission and efficient target state tracking are realized.

Methods, systems, and devices for wireless communications are described. A network entity may transmit DCIs to a UE to schedule instances of one or more MBS TBs, the multiple instances of the one or more TBs being time-interleaved. For example, the network entity may transmit a first set of DCIs scheduling a first set of instances of a first TB, and a second set of DCIs scheduling a second set of instances of a second TB, where at least one instance of the first set of instances may be interleaved with the second set of instances. In some cases, the first and second set of DCIs may include one DCI to schedule the respective set of instances, or one DCI per instance of the respective set of instances. Additionally, or alternatively, the network entity may indicate one or more parameters to the UE associated with MBS inter-TB time interleaving.

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

The embodiment of the invention discloses a chip calibration method and device, a storage medium and electronic equipment, relates to the technical field of communication, and aims to solve the problem of performance reduction caused by time interleaving errors of a chip of a time interleaving architecture in the prior art. According to the method, firstly, the error calculation of the whole link is carried out by directly collecting the digital result output by the ADC, then optimization iteration is carried out in the simulation domain according to the calculated time interleaving error, the numerical value of the corresponding sub-ADC channel register is adjusted, the register is updated in a register control code mode, and the time interleaving error of the whole link is calculated. The offset error, the gain error and the clock offset between the sub-ADC channels are corrected, and finally the chip is calibrated, so that the performance of the chip is improved.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

Methods, systems, and devices for wireless communications are described. A network entity may transmit DCIs to a UE to schedule instances of one or more MBS TBs, the multiple instances of the one or more TBs being time-interleaved. For example, the network entity may transmit a first set of DCIs scheduling a first set of instances of a first TB, and a second set of DCIs scheduling a second set of instances of a second TB, where at least one instance of the first set of instances may be interleaved with the second set of instances. In some cases, the first and second set of DCIs may include one DCI to schedule the respective set of instances, or one DCI per instance of the respective set of instances. Additionally, or alternatively, the network entity may indicate one or more parameters to the UE associated with MBS inter-TB time interleaving.

Methods, systems, and devices for wireless communications are described. A network entity may transmit DCIs to a UE to schedule instances of one or more MBS TBs, the multiple instances of the one or more TBs being time-interleaved. For example, the network entity may transmit a first set of DCIs scheduling a first set of instances of a first TB, and a second set of DCIs scheduling a second set of instances of a second TB, where at least one instance of the first set of instances may be interleaved with the second set of instances. In some cases, the first and second set of DCIs may include one DCI to schedule the respective set of instances, or one DCI per instance of the respective set of instances. Additionally, or alternatively, the network entity may indicate one or more parameters to the UE associated with MBS inter-TB time interleaving.

The invention discloses an interleaving sampling circuit, and particularly relates to the technical field of signal sampling. In the circuit, the input end of a first input buffer is used for accessing a signal to be sampled; the output end of the first input buffer is respectively connected to the input ends of the at least two sampling and holding amplifiers; the output end of each sampling and holding amplifier is connected with at least one analog-to-digital converter; the clock signals accessed by the at least two sampling and holding amplifiers are activated alternately; for any sampling and holding amplifier, when a clock signal of the sampling and holding amplifier is at a high level, only one of the analog-to-digital converters connected with the sampling and holding amplifier is in a working state, and the analog-to-digital converters in the working state are alternately switched along with the period of the clock signal of the sampling and holding amplifier. The interleaving sampling circuit can improve the performance of the time interleaving ADC.

A time-interleaved ADC mismatch correction method and time-interleaved ADC relating to the technical field of integrated circuits are disclosed. The time-interleaved ADC mismatch correction method and time-interleaved ADC solve problems with high-order filter modules and signal overflow or saturation risks. The applied technical scheme uses time-interleaved ADC output signal(s) and a fitted signal to calculate a set of filtering coefficients, and uses this set of filtering coefficients to correct the ADC output signal in real time. The applied technical scheme compensates for differences in the frequency response of each channel, rather than the frequency response itself, and the filter order is smaller, the implementation is simpler, and the circuit design complexity and device cost are greatly reduced. The technical solution has a wide range of adaptability, can correct and improve broadband interleaving performance, and avoids the signal overflow / saturation risk because the compensation range is small.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The invention relates to the technical field of digital information secure transmission, in particular to a data information secure transmission method and system. The method comprises the following steps of: performing differential quantization and coding on original measurement data of a power grid to obtain a parameter feature code vector; constructing a power grid disturbance response matrix according to the parameter feature code vector to obtain a disturbance response matrix; acquiring to-be-transmitted data; performing information channel modulation on the to-be-transmitted data according to the disturbance response matrix to obtain a modulation parameter sequence; performing time interleaving analysis according to the modulation parameter sequence to obtain a time interleaving data stream; obtaining power grid topology information; performing space-time fusion coding transmission according to the power grid topology information and the time-interleaved data stream to obtain a space-time interleaved code stream; and performing spatio-temporal de-interleaving processing on the spatio-temporal interleaving code stream to obtain a channel data block set. According to the invention, the security, reliability, concealment and high adaptability of data information transmission are improved through a digital information security transmission technology.

An ADC circuit comprises: an ADC for performing a conversion operation in a time-interleaved manner; and a control logic circuit connected to the ADC, where the control logic circuit is configured to: calculate a correlation value between the data at a first number of times using a first number of bits in each of the data output from the ADC; calibrating the sampling timing of at least some of the ADCs based on a first accumulated correlation value obtained by accumulating correlation values calculated at a first number of times; calculating a correlation value between the data at a second number of times by using a second number of bits in each data; and calibrating the sampling timing of at least some of the ADCs based on a second accumulated correlation value obtained by accumulating the correlation values calculated by the second number of times.

Write data bursts directed to two different channels (or ranks) may be time-interleaved and transmitted to a data buffer device. The data buffer device deinterleaves the write data bursts and transmits them to memory devices via two different memory channel data interfaces. When one of the channels is not being written to, the host may time-interleave write data for two write data bursts that are directed to the same channel. The write data burst for the first channel is transmitted to the memory devices via the first channel. The time-demultiplexed write data burst for the next write transaction directed to the first channel is stored by the data buffer device. At a later time, the data buffer device transmits stored write data burst to the memory devices via the first channel.

The present invention discloses a high-precision source measurement unit. On the basis of the prior art, the D / A conversion circuit is improved. A low-noise amplifier Amp and four resistors are used to add the outputs V1 and V2 of two DACs with a set proportionality coefficient of 2 N to increase the resolution of digital-to-analog conversion by N bit, greatly improving the resolution and sampling rate of the D / A conversion circuit, that is, using the DAC splicing technology to achieve high-bandwidth and high-precision signal output. At the same time, in the present invention, both the voltage A / D conversion circuit and the current A / D conversion circuit are time-interleaved analog-to-digital conversion devices, which improves the signal sampling rate and further improves the measurement accuracy and bandwidth.

A derivative measurement circuit is configured to sample the input voltage of an input line to determine the time-derivative of the input voltage. A plurality of time-interleaved analog-to-digital converters (ADCs) are configured to convert respective input-voltage samples that are sampled at different times. The ADCs do not convert the input-voltage samples having respective time-derivatives that are above a predetermined threshold magnitude or that are relatively high to limit sampling clock jitter and sampling clock skew.

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

An apparatus includes an analog-to-digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe type and one or more additional frames of at least one additional component carrier signal, the one or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration for at least one of the first or second component carrier signal based at least in part on an operating mode of the second component carrier signal and respective symbols of the first and second component carrier signals.

The invention discloses a time domain interleaving method, a de-interleaving method, an interleaver and a de-interleaver, and the time domain interleaving method comprises the following steps: carrying out expansion, code block segmentation and coding on a transmission block by using a redundancy version number n used for interleaving to obtain k coded code blocks, or carrying out code block segmentation and coding on the transmission block with the redundancy version number n used for interleaving to obtain k coded code blocks; obtaining k coded code blocks; performing rate matching related operation on the k coded code blocks, and writing the k coded code blocks into a circulating memory; according to the number of physical resources of the subframe, the size of a transmission block and the number of redundancy versions, determining a bit position corresponding to each redundancy version in the cyclic memory; and taking n subframes as a period, selecting a redundancy version for k code blocks in each subframe according to a preset selection method, and carrying out subsequent baseband processing and transmission on bits contained in the redundancy version. According to the method provided by the invention, the problem of concentrated information bit distribution in the existing time interleaving method for multiplexing HARQ storage can be effectively solved, the anti-interference capability of the system is remarkably improved, the bit error rate caused by channel fading is reduced, and the transmission quality and performance of the whole communication system are improved.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

Methods, systems, and devices for wireless communications are described. A network entity may transmit DCIs to a UE to schedule instances of one or more MBS TBs, the multiple instances of the one or more TBs being time-interleaved. For example, the network entity may transmit a first set of DCIs scheduling a first set of instances of a first TB, and a second set of DCIs scheduling a second set of instances of a second TB, where at least one instance of the first set of instances may be interleaved with the second set of instances. In some cases, the first and second set of DCIs may include one DCI to schedule the respective set of instances, or one DCI per instance of the respective set of instances. Additionally, or alternatively, the network entity may indicate one or more parameters to the UE associated with MBS inter-TB time interleaving.

The present invention inhibits interference of time-interleaved AD converters.　An AD conversion circuit (TD1) is provided with a plurality of time-interleaved AD converters (AD1 to AD4) and a plurality of sample-and-hold circuits (SH1 to SH4; SW1, SC1, GW1, . . . , SW4, SC4, and GW4) that sample and hold an analog input (AI) and a reference potential (VS) of each of the plurality of AD converters (AD1 to AD4).

The invention provides a digital calibration system and method for a time-interleaved analog-to-digital converter, and belongs to the technical field of digital circuits, and the system comprises an analog-to-digital converter module which is used for receiving an input calibration signal and obtaining a plurality of analog-to-digital converter data based on the calibration signal; the plurality of analog-to-digital converter data are voltage and current of the analog-to-digital converters, the power calculation module is used for obtaining power corresponding to the plurality of analog-to-digital converters based on the plurality of analog-to-digital converter data, the accumulator is used for obtaining average power of the plurality of analog-to-digital converters based on the power corresponding to the plurality of analog-to-digital converters, and the judgment module is used for judging the average power of the plurality of analog-to-digital converters. The analog-to-digital converter module is used for obtaining a judgment result based on the power corresponding to the analog-to-digital converters and the average power of the analog-to-digital converters, and the calibration module is used for carrying out dynamic calibration operation on the analog-to-digital converter module based on the judgment result. According to the invention, the technical problem of low digital calibration precision of the analog-to-digital converter in the prior art is solved.

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

Various schemes related to video coding parallelization techniques are described. An apparatus receives video data. The apparatus then calculates a plurality of figures of merit (FOMs), each FOM representing how much quality a particular coding tool can achieve when encoding the video data. The apparatus also determines coding tools that can be suitable for encoding the video data by comparing the FOMs. In determining the coding tools, the apparatus utilizes a time interleaving technique to process the video data in parallel. The video data can include an array of coding blocks, and the apparatus can receive the video data using a snake processing order to scan the array of coding blocks.

A method for preventing performance degradation of a blind calibration of an interleaving error of a plurality of time-interleaved analog-to-digital converters, the method comprising: Acquiring a block of data comprising output values generated by one of the plurality of time-interleaved analog-to-digital converters; Qualifying the data block by evaluating a variability measurement of a qualification histogram generated from the data block; in response to determining that the data block fails qualification, skipping an update of the interleaving error blind calibration; and in response to determining that the data block qualifies, using the data block to update the blind calibration of the interleaving error.

The present invention discloses a clock mismatch calibration method for a time-interleaved ADC, and relates to the technical field of clock calibration, including dividing a TI-ADC into M sub-ADCs, selecting a pair of sub-ADCs with an interval of M / 2 for clock mismatch calibration, wherein M is an even number; taking two calibrated sub-ADCs as a reference, selecting a sub-ADC located between the two sub-ADCs for clock mismatch calibration; fixing the three calibrated sub-ADCs, and adjusting the gain of the first sub-ADC in the digital domain; performing clock mismatch calibration on the selected two sub-ADCs again with the gains of the first two sub-ADCs and the first sub-ADC; repeating steps S1 to S4 until all ADCs are calibrated. The method of the present invention effectively solves the problem of large clock mismatch calibration error caused by the coupling effect between gain mismatch and clock deviation, and simultaneously realizes digital domain compensation of gain and high-precision estimation of clock deviation.

A correction device (100) for a multi-channel time-interleaved ADC system (300) is disclosed. The correction device (100) is configured to correct amplitude response mismatch errors of an ADC output sequence v using a first time-varying function B and further to correct phase response mismatch errors of the ADC output sequence using a second time-varying function C. Thus, due to the use of the first time-varying function B and the second time-varying function C, low complexity converter performance is improved.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, during a first multicast channel (MCH) scheduling period, an MCH scheduling information (MSI) medium access control control element (MAC-CE) associated with one or more time-interleaved multicast traffic channel (MTCH) transmissions. The UE may receive the one or more time-interleaved MTCH transmissions, spanning one or more MCH scheduling periods, including the first MCH scheduling period, based at least in part on the MSI MAC-CE. Numerous other aspects are described.

A system and method for digitizing signals from a plurality of channels in parallel, using a time interleaved and beam-forming receiver, such as a phased array, applying appropriate delays, and performing the digitization using analog-to-digital converters sized based on the reciprocal of the number of channels. The system includes a delay line applying a tunable delay to the received signals before the signals are digitized.

A time-interleaved analog-to-digital converter includes multiple coarse converter circuits, a control logic circuit, multiple first and second transfer circuits, a fine converter circuit, and an encoder circuit. The multiple coarse converter circuits sequentially sample input signals and perform multiple coarse conversions to generate multiple decision signals. The control logic circuit generates multiple coarse digital codes based on the decision signals. The multiple first and second transfer circuits transfer multiple first and second residual value signals, respectively. The fine converter circuits perform fine conversion based on the corresponding first and second residual value signals to generate fine digital codes. The sampling period for sampling the input signal and the coarse conversion period for performing coarse conversion are set based on the fine conversion period for performing fine conversion. The encoder circuit generates a digital output based on the corresponding coarse and fine digital codes.