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476 results about "Time interleaved" patented technology

Time interleaving is a technique that allows the use of multiple identical analog-to-digital converters [1] (ADCs) to process regular sample data series at a faster rate than the operating sample rate of each individual data converter.

Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter

InactiveCN101888247AAvoid problems that are difficult to convert to hardware circuitsThere is no problem of implementation deviationAnalogue-digital convertersAnalogue/digital conversion calibration/testingTime errorDigital down converter
The invention discloses a self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter, comprising an M channel TIADC, a signal recombination, a digital reference signal memorizer, a simulated reference signal generator, a self-adaptive reconstruction filter bank, a clock generation circuit and a subtraction device. Signals after passages are reconstructed are used to correct each passage instead of single correction on each passage, thereby solving the problem that when an input signal bandwidth is larger than the Nyquist frequency of each passage ADC, the time error can not be corrected due to aliasing. Each self-adoptive reconstruction filter is divided into a plurality of sub-filters for concurrent working, thereby not improving the requirement of thetreatment speed for a self-adoptive correcting filter while realizing the effect of signal recombination and ensuring the practicability of the hardware of the structure of the invention. A digital reference signal is internally installed in the device and is taken as a target to carry out the self-adoptive correction, pre-measuring or calculating a passage mismatch error is not needed, and the source of the error is not needed to be discriminated so that various mismatch errors can be corrected.
Owner:BEIJING UNIV OF TECH

High-speed high-accuracy recorder and sampling data automatic-correction and high-order matching method thereof

The invention discloses a high-speed high-accuracy recorder and a designing method thereof. The high-speed high-accuracy recorder comprises a signal conditioning module, four analogue-to-digital converter (ADC) modules, four first in first out (FIFO) modules, two synchronous dynamic random access memory (SDRAM) modules, a client-server architecture control module, a synchronous coherent clock module, a high-accuracy reference voltage source module and the like, wherein the client-server architecture control module consists of an advanced RISC machine (ARM) unit and a field programmable gate array (FPGA) unit; and the synchronous coherent clock module takes a clock chip as a core. The recorder finishes the operations of 'time-interleaved' sampling, encapsulation, caching, transmission, decapsulation combination, correction, storage, uploading and the like concurrently under the control of a concurrent time sequence logic, corrects sampling data based on an inter-ADC channel mismatchingautomatic-correction polynomial to reduce gain mismatching and offset/zero mismatching among ADC channels, reduces time mismatching among the ADC channels by using a synchronous coherent clock and a serpentine curve wire-length fine-adjustment technology, and solves the problems of associated global errors produced by data loss in the high-speed 'time-interleaved' sampling by using a high-order matching technology in which the encapsulation is performed by additional timestamp sequence numbers.
Owner:ZHEJIANG UNIV +1

Multi-channel time-interleaved analog-digital converter

ActiveCN104038226AControl workflowAccurately Calculate Timing Mismatch ErrorAnalogue/digital conversion calibration/testingDigital down converterTransverter
The invention provides a multi-channel time-interleaved analog-digital converter. The multi-channel time-interleaved analog-digital converter is characterized in that a clock generation circuit generates a work clock for the converter; an ADC channel set including M ADC channels is configured into a time-interleaved structure; the ADC channels operate in turns in a time division multiplexing under control of the clock generation circuit, a high-speed analog input signal is converted into M low-speed digital output signals, and M is an integer not smaller than 2; a channel mismatch detection circuit detects timing sequence mismatch errors of signals output by the M ADC channel, in real time, so that a timing sequence mismatch parameter of each ADC channel relative to a reference ADC channel is acquired; a signal compensation and reconstruction circuit compensates and reconstructs the digital output signals output by the ADC channel set according to the timing sequence mismatch errors that the channel mismatch detection circuit detects; a signal combiner circuit combines the M low-speed output signals subjected to channel compensation and generated by the signal compensation and reconstruction circuit, and finally a high-speed digital output signal is obtained.
Owner:HUAWEI TECH CO LTD
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