24 results about "Time interleaved" patented technology

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

Write data bursts directed to two different channels (or ranks) may be time-interleaved and transmitted to a data buffer device. The data buffer device deinterleaves the write data bursts and transmits them to memory devices via two different memory channel data interfaces. When one of the channels is not being written to, the host may time-interleave write data for two write data bursts that are directed to the same channel. The write data burst for the first channel is transmitted to the memory devices via the first channel. The time-demultiplexed write data burst for the next write transaction directed to the first channel is stored by the data buffer device. At a later time, the data buffer device transmits stored write data burst to the memory devices via the first channel.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The present invention inhibits interference of time-interleaved AD converters.　An AD conversion circuit (TD1) is provided with a plurality of time-interleaved AD converters (AD1 to AD4) and a plurality of sample-and-hold circuits (SH1 to SH4; SW1, SC1, GW1, . . . , SW4, SC4, and GW4) that sample and hold an analog input (AI) and a reference potential (VS) of each of the plurality of AD converters (AD1 to AD4).

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

Various schemes related to video coding parallelization techniques are described. An apparatus receives video data. The apparatus then calculates a plurality of figures of merit (FOMs), each FOM representing how much quality a particular coding tool can achieve when encoding the video data. The apparatus also determines coding tools that can be suitable for encoding the video data by comparing the FOMs. In determining the coding tools, the apparatus utilizes a time interleaving technique to process the video data in parallel. The video data can include an array of coding blocks, and the apparatus can receive the video data using a snake processing order to scan the array of coding blocks.

A correction device (100) for a multi-channel time-interleaved ADC system (300) is disclosed. The correction device (100) is configured to correct amplitude response mismatch errors of an ADC output sequence v using a first time-varying function B and further to correct phase response mismatch errors of the ADC output sequence using a second time-varying function C. Thus, due to the use of the first time-varying function B and the second time-varying function C, low complexity converter performance is improved.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, during a first multicast channel (MCH) scheduling period, an MCH scheduling information (MSI) medium access control control element (MAC-CE) associated with one or more time-interleaved multicast traffic channel (MTCH) transmissions. The UE may receive the one or more time-interleaved MTCH transmissions, spanning one or more MCH scheduling periods, including the first MCH scheduling period, based at least in part on the MSI MAC-CE. Numerous other aspects are described.

An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A / D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A / D conversions.

In some embodiments, there may be provided systems, methods, and articles of manufacture for timeinterleaved multiple output. In some example embodiments, there may be provided an apparatus including a plurality of antennas; an analog spreader coupled the plurality of antennas; a radio frequency chain coupled to the analog spreader, wherein the radio frequency chain down converts and performs an analog-to-digital conversion to generate a stream; and a digital despreader, wherein the digital despreader receives the stream output by the radio frequency chain and digitally inverts analog spreading caused by the analog spreader to generate one or more user streams. Related systems, methods, and articles of manufacture are also disclosed.

A analog-to-digital conversion circuit includes a plurality of time interleaved analog-digital converters (TI-ADCs), a timing calibrator configured to calculate calibration values of the plurality of TI-ADCs based on correlation values between target samples output from target TI-ADCs and adjacent samples of adjacent TI-ADCs in two respective cycles and output codes for calibrating time skews of the plurality of TI-ADCs based on the calibration values and a plurality of calibration parameters, and a clock phase adjuster configured to adjust phases of a plurality of clock signals based on the codes.

Methods, systems, and devices for conducting wireless communications are described. A network entity may send a DCI (Distributed Control Information Code) to the UE for scheduling instances of one or more MBS TBs, where multiple instances of the one or more TBs are time-interleaved. For example, the network entity may send a first set of DCIs for scheduling a first group of instances of a first TB and a second set of DCIs for scheduling a second group of instances of a second TB, wherein at least one instance in the first group of instances may be interleaved with the instances in the second group. In some cases, the first set of DCIs and the second set of DCIs may include a single DCI for scheduling the respective group of instances, or a DCI for each instance in the respective group of instances. Additionally or alternatively, the network entity may indicate to the UE one or more parameters associated with time interleaving between MBS TBs.

A receiver includes an analog front end configured to receive a data input / output signal and amplify the data input / output signal and generate a processing signal, a time interleaved analog-to-digital converter (TI ADC) configured to sample the processing signal and generate a plurality of digital data signals, a Mueller-Muller phase detector configured to receive the digital data signals and drive at least one of a plurality of calculators based on a transition between two digital data signals, a monitoring circuit configured to receive the digital data signals, receive a multi-level signal transmitted from a transmitter, and generate a monitoring output signal based on the digital data signals and the multi-level signal, and a control logic circuit configured to receive a monitoring output signal output and generate a plurality of calculator selection signals for driving the calculators based on the monitoring output signal.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

The utility model provides a high-speed signal acquisition device and an automatic test system in order to solve the problem of insufficient signal-to-noise ratio of signals in the prior art. The equipment comprises an analog front-end module, an analog-to-digital conversion module, a multi-stage storage module, an interface module, a clock synchronization module, a digital correction module and a distributed data processing module. The analog front-end module adopts three-stage processing of a signal conditioning circuit, a differential amplifier and an anti-aliasing filter, low-noise amplification and single-end-to-differential output are realized through the signal conditioning circuit, the bandwidth is accurately limited by combining the anti-aliasing filter, the signal-to-noise ratio of a signal is increased to more than 100dB, common-mode interference and aliasing distortion are effectively inhibited, and the signal-to-noise ratio of the signal is increased to more than 100dB. And the nanosecond baseline error is ensured. The analog-to-digital conversion module adopts a multi-ADC time interleaving architecture and is matched with a phase locking circuit to generate a synchronous clock with the phase difference of 180 degrees / n, so that the equivalent sampling rate is improved to n times of that of a single channel, and meanwhile, the time sequence offset between the channels is eliminated.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, during a first multicast channel (MCH) scheduling period, an MCH scheduling information (MSI) medium access control control element (MAC-CE) associated with one or more time-interleaved multicast traffic channel (MTCH) transmissions. The UE may receive the one or more time-interleaved MTCH transmissions, spanning one or more MCH scheduling periods, including the first MCH scheduling period, based at least in part on the MSI MAC-CE. Numerous other aspects are described.

The invention discloses a receiver, a phase detection apparatus and a phase detection method. The receiver includes: an analog front end configured to receive a data input / output signal, and amplify the data input / output signal, and generate a processed signal; a time interleaved analog-to-digital converter (TI ADC) configured to sample the processing signal and generate a plurality of digital data signals; a Mueller-Muller phase detector configured to receive the digital data signals, and to drive at least one of the plurality of calculators based on a transition between two digital data signals; a monitoring circuit configured to receive the digital data signal, receive the multi-level signal transmitted from the transmitter, and generate a monitoring output signal based on the digital data signal and the multi-level signal; and a control logic circuit configured to receive the output monitoring output signal and generate a plurality of calculator selection signals for driving the calculator based on the monitoring output signal.

The application relates to the technical field of marine data monitoring, and discloses a marine data monitoring method based on a wireless communication system, which comprises the following steps: S1, data acquisition, obtaining marine monitoring data of a target; S2, data preprocessing, performing format conversion, deduplication, time alignment and data interpolation processing on the data obtained in the data acquisition; S3, data fusion, based on a time interleaving algorithm and a space clustering algorithm, matching and fusing the processed data; S4, target tracking, under the condition of target data loss, adopting a Kalman filtering method to predict a target trajectory; and S5, monitoring output, generating a fusion data set and outputting dynamic information of the target. Through the combination of deep learning target identification, an LSTM network state prediction and efficient wireless communication technology, the application realizes more accurate marine target monitoring, stable real-time data transmission and efficient target state tracking.

Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.

The invention discloses a time-interleaving-based digital-to-analog converter with high sampling rate and high resolution, which comprises M identical N-channel data interfaces used for synchronizing sampling data in a synchronization mode and descrambling the sampling data in a working mode; the M encoders are used for performing hybrid encoding on acquired N-bit sampling data through x-bit thermometer encoding and y-bit binary encoding, and the data after hybrid encoding are used for driving the current switch array; the multiplexer is used for combining the data signals of the first rate in the M * (2x-1 + y) channels to generate the data signals of the M * first rate of the 2x-1 + y channels; the ECL buffer is used for reducing clock noise and re-synchronizing a sampled data signal; and the current switch array is used for outputting an analog sampling signal and realizing conversion from a digital signal to an analog signal. According to the digital-to-analog converter, the precision of the digital-to-analog converter is ensured, the power consumption is reduced, and the precision and the power consumption are balanced.

This invention discloses an analog-to-digital converter (ADC) based on time-interleaved noise and its application method. The ADC includes: a first-channel conversion circuit, a second-channel conversion circuit, a multiplexer, a shared dynamic amplifier, a first feedback error circuit, a second feedback error circuit, and a feedforward error circuit. This invention processes the signal to be converted using the dual-channel conversion circuits. The first-channel conversion circuit receives a common-mode level based on a first preset period, and the second-channel conversion circuit receives a common-mode level based on a second preset period, thereby achieving interleaved time conversion between the two channels. The shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit, and the feedforward error circuit enable dynamic power consumption across the entire ADC circuit, thus meeting different bandwidth and accuracy application requirements depending on the sampling frequency and oversampling rate.

The application belongs to the technical field of time-interleaved analog-to-digital converter, and relates to a sampling time deviation calibration method of a time-interleaved analog-to-digital converter. The application extracts the sampling time deviation information of the time-interleaved analog-to-digital converter by using the deviation direction information obtained by a Mueller-Muller type phase detector in a clock recovery circuit and combining the autocorrelation principle, and adjusts the sampling time of each analog-to-digital converter through calibration logic. Because the deviation direction information obtained by the Mueller-Muller type phase detector in the clock recovery circuit is multiplexed, the hardware overhead of the circuit is greatly reduced, and the area and power consumption of the circuit are reduced.