56 results about "Time interleaved" patented technology

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

The invention discloses an interleaving sampling circuit, and particularly relates to the technical field of signal sampling. In the circuit, the input end of a first input buffer is used for accessing a signal to be sampled; the output end of the first input buffer is respectively connected to the input ends of the at least two sampling and holding amplifiers; the output end of each sampling and holding amplifier is connected with at least one analog-to-digital converter; the clock signals accessed by the at least two sampling and holding amplifiers are activated alternately; for any sampling and holding amplifier, when a clock signal of the sampling and holding amplifier is at a high level, only one of the analog-to-digital converters connected with the sampling and holding amplifier is in a working state, and the analog-to-digital converters in the working state are alternately switched along with the period of the clock signal of the sampling and holding amplifier. The interleaving sampling circuit can improve the performance of the time interleaving ADC.

A time-interleaved ADC mismatch correction method and time-interleaved ADC relating to the technical field of integrated circuits are disclosed. The time-interleaved ADC mismatch correction method and time-interleaved ADC solve problems with high-order filter modules and signal overflow or saturation risks. The applied technical scheme uses time-interleaved ADC output signal(s) and a fitted signal to calculate a set of filtering coefficients, and uses this set of filtering coefficients to correct the ADC output signal in real time. The applied technical scheme compensates for differences in the frequency response of each channel, rather than the frequency response itself, and the filter order is smaller, the implementation is simpler, and the circuit design complexity and device cost are greatly reduced. The technical solution has a wide range of adaptability, can correct and improve broadband interleaving performance, and avoids the signal overflow / saturation risk because the compensation range is small.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The invention relates to the technical field of digital information secure transmission, in particular to a data information secure transmission method and system. The method comprises the following steps of: performing differential quantization and coding on original measurement data of a power grid to obtain a parameter feature code vector; constructing a power grid disturbance response matrix according to the parameter feature code vector to obtain a disturbance response matrix; acquiring to-be-transmitted data; performing information channel modulation on the to-be-transmitted data according to the disturbance response matrix to obtain a modulation parameter sequence; performing time interleaving analysis according to the modulation parameter sequence to obtain a time interleaving data stream; obtaining power grid topology information; performing space-time fusion coding transmission according to the power grid topology information and the time-interleaved data stream to obtain a space-time interleaved code stream; and performing spatio-temporal de-interleaving processing on the spatio-temporal interleaving code stream to obtain a channel data block set. According to the invention, the security, reliability, concealment and high adaptability of data information transmission are improved through a digital information security transmission technology.

An ADC circuit comprises: an ADC for performing a conversion operation in a time-interleaved manner; and a control logic circuit connected to the ADC, where the control logic circuit is configured to: calculate a correlation value between the data at a first number of times using a first number of bits in each of the data output from the ADC; calibrating the sampling timing of at least some of the ADCs based on a first accumulated correlation value obtained by accumulating correlation values calculated at a first number of times; calculating a correlation value between the data at a second number of times by using a second number of bits in each data; and calibrating the sampling timing of at least some of the ADCs based on a second accumulated correlation value obtained by accumulating the correlation values calculated by the second number of times.

Write data bursts directed to two different channels (or ranks) may be time-interleaved and transmitted to a data buffer device. The data buffer device deinterleaves the write data bursts and transmits them to memory devices via two different memory channel data interfaces. When one of the channels is not being written to, the host may time-interleave write data for two write data bursts that are directed to the same channel. The write data burst for the first channel is transmitted to the memory devices via the first channel. The time-demultiplexed write data burst for the next write transaction directed to the first channel is stored by the data buffer device. At a later time, the data buffer device transmits stored write data burst to the memory devices via the first channel.

A derivative measurement circuit is configured to sample the input voltage of an input line to determine the time-derivative of the input voltage. A plurality of time-interleaved analog-to-digital converters (ADCs) are configured to convert respective input-voltage samples that are sampled at different times. The ADCs do not convert the input-voltage samples having respective time-derivatives that are above a predetermined threshold magnitude or that are relatively high to limit sampling clock jitter and sampling clock skew.

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

An apparatus includes an analog-to-digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe type and one or more additional frames of at least one additional component carrier signal, the one or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration for at least one of the first or second component carrier signal based at least in part on an operating mode of the second component carrier signal and respective symbols of the first and second component carrier signals.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The present invention inhibits interference of time-interleaved AD converters.　An AD conversion circuit (TD1) is provided with a plurality of time-interleaved AD converters (AD1 to AD4) and a plurality of sample-and-hold circuits (SH1 to SH4; SW1, SC1, GW1, . . . , SW4, SC4, and GW4) that sample and hold an analog input (AI) and a reference potential (VS) of each of the plurality of AD converters (AD1 to AD4).

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

Various schemes related to video coding parallelization techniques are described. An apparatus receives video data. The apparatus then calculates a plurality of figures of merit (FOMs), each FOM representing how much quality a particular coding tool can achieve when encoding the video data. The apparatus also determines coding tools that can be suitable for encoding the video data by comparing the FOMs. In determining the coding tools, the apparatus utilizes a time interleaving technique to process the video data in parallel. The video data can include an array of coding blocks, and the apparatus can receive the video data using a snake processing order to scan the array of coding blocks.

A method for preventing performance degradation of a blind calibration of an interleaving error of a plurality of time-interleaved analog-to-digital converters, the method comprising: Acquiring a block of data comprising output values generated by one of the plurality of time-interleaved analog-to-digital converters; Qualifying the data block by evaluating a variability measurement of a qualification histogram generated from the data block; in response to determining that the data block fails qualification, skipping an update of the interleaving error blind calibration; and in response to determining that the data block qualifies, using the data block to update the blind calibration of the interleaving error.

A correction device (100) for a multi-channel time-interleaved ADC system (300) is disclosed. The correction device (100) is configured to correct amplitude response mismatch errors of an ADC output sequence v using a first time-varying function B and further to correct phase response mismatch errors of the ADC output sequence using a second time-varying function C. Thus, due to the use of the first time-varying function B and the second time-varying function C, low complexity converter performance is improved.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, during a first multicast channel (MCH) scheduling period, an MCH scheduling information (MSI) medium access control control element (MAC-CE) associated with one or more time-interleaved multicast traffic channel (MTCH) transmissions. The UE may receive the one or more time-interleaved MTCH transmissions, spanning one or more MCH scheduling periods, including the first MCH scheduling period, based at least in part on the MSI MAC-CE. Numerous other aspects are described.

A system and method for digitizing signals from a plurality of channels in parallel, using a time interleaved and beam-forming receiver, such as a phased array, applying appropriate delays, and performing the digitization using analog-to-digital converters sized based on the reciprocal of the number of channels. The system includes a delay line applying a tunable delay to the received signals before the signals are digitized.

A time-interleaved analog-to-digital converter includes multiple coarse converter circuits, a control logic circuit, multiple first and second transfer circuits, a fine converter circuit, and an encoder circuit. The multiple coarse converter circuits sequentially sample input signals and perform multiple coarse conversions to generate multiple decision signals. The control logic circuit generates multiple coarse digital codes based on the decision signals. The multiple first and second transfer circuits transfer multiple first and second residual value signals, respectively. The fine converter circuits perform fine conversion based on the corresponding first and second residual value signals to generate fine digital codes. The sampling period for sampling the input signal and the coarse conversion period for performing coarse conversion are set based on the fine conversion period for performing fine conversion. The encoder circuit generates a digital output based on the corresponding coarse and fine digital codes.

The invention relates to the technical field of high-speed digital-to-analog conversion, and discloses a pulse width error calibration method of an ultra-high-speed digital-to-analog converter. According to the method, in a time interleaving architecture of a multi-sub DAC, high-precision compensation of a pulse width error is realized through target sampling, time-sharing point sampling, correlation analysis and a least mean square (LMS) adaptive algorithm. The method innovatively introduces a'advanced counting point 'strategy, periodically predicts a sampling position by using a test signal, avoids large-scale register storage, and realizes data acquisition with low hardware overhead. An ideal value and a channel reflection effect are eliminated through difference of adjacent sampling points, a pulse width error control word is accurately updated in combination with a bandwidth compensation factor, and the pulse width error control word only acts on a corresponding sub-DAC. The scheme reduces the pulse width error from about 1ps to about 50fs in Matlab simulation, has the advantages of high precision, low power consumption, strong stability and small area occupation, and is suitable for high-speed serial interface chips and coherent / incoherent optical chips.

An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A / D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A / D conversions.

In some embodiments, there may be provided systems, methods, and articles of manufacture for timeinterleaved multiple output. In some example embodiments, there may be provided an apparatus including a plurality of antennas; an analog spreader coupled the plurality of antennas; a radio frequency chain coupled to the analog spreader, wherein the radio frequency chain down converts and performs an analog-to-digital conversion to generate a stream; and a digital despreader, wherein the digital despreader receives the stream output by the radio frequency chain and digitally inverts analog spreading caused by the analog spreader to generate one or more user streams. Related systems, methods, and articles of manufacture are also disclosed.

A analog-to-digital conversion circuit includes a plurality of time interleaved analog-digital converters (TI-ADCs), a timing calibrator configured to calculate calibration values of the plurality of TI-ADCs based on correlation values between target samples output from target TI-ADCs and adjacent samples of adjacent TI-ADCs in two respective cycles and output codes for calibrating time skews of the plurality of TI-ADCs based on the calibration values and a plurality of calibration parameters, and a clock phase adjuster configured to adjust phases of a plurality of clock signals based on the codes.

Methods, systems, and devices for conducting wireless communications are described. A network entity may send a DCI (Distributed Control Information Code) to the UE for scheduling instances of one or more MBS TBs, where multiple instances of the one or more TBs are time-interleaved. For example, the network entity may send a first set of DCIs for scheduling a first group of instances of a first TB and a second set of DCIs for scheduling a second group of instances of a second TB, wherein at least one instance in the first group of instances may be interleaved with the instances in the second group. In some cases, the first set of DCIs and the second set of DCIs may include a single DCI for scheduling the respective group of instances, or a DCI for each instance in the respective group of instances. Additionally or alternatively, the network entity may indicate to the UE one or more parameters associated with time interleaving between MBS TBs.

The invention discloses a time domain interleaving method, a de-interleaving method, an interleaver and a de-interleaver, and the time domain interleaving method comprises the steps: carrying out the extension, code block segmentation and coding of a transmission block through the redundancy version number n used for interleaving, obtaining k coded code blocks, and writing the coded code blocks into a circulation memory; dividing redundancy versions and marking redundancy version numbers based on the bit length of each redundancy version of the coded code block in the cyclic memory; each subframe selects redundancy versions with the same redundancy version number in k code blocks, and the k redundancy versions are arranged according to a preset arrangement method and / or offset according to a preset offset method; according to the method provided by the invention, the problem that the existing time interleaving method for multiplexing HARQ storage amplifies selective fading of a frequency domain can be effectively solved, the anti-interference capability of a system is remarkably improved, the bit error rate of a code block caused by channel fading is reduced, and the performance of the system is improved. And the transmission quality and performance of the whole communication system are improved.

The application discloses a high-frequency signal single event transient detection method based on time interleaving, which comprises the following steps: under the condition of no irradiation, time interleaving high-speed collection is performed on the output of a to-be-detected circuit to obtain a sample value D(t), and an ideal denoising value I(t) and a noise value Z(t) at a corresponding moment are calculated; irradiation test is performed on the to-be-detected circuit, and time interleaving high-speed collection is performed on the high-frequency signal of the output of the to-be-detected circuit to obtain a sample value D'(t); according to the sample value D'(t) and the noise value Z(t) at the corresponding moment, an actual denoising value V(t) at the corresponding moment is calculated; according to the comparison result of V(t) and the ideal denoising value I(t) at the corresponding moment, the amplitude and the pulse width of the single event transient at the corresponding moment are determined; until the irradiation test is finished, a single event transient error characteristic distribution diagram of the to-be-detected circuit under heavy ions is obtained. The application effectively improves the pulse width precision and the amplitude precision of the single event transient signal in the board-level test, and improves the accuracy of the test.

The invention relates to an autonomous synchronization architecture for large scale time interleaved analog-to-digital converters. An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC including: a clock divider configured to generate a third clock signal based on the second clock signal; a token generator configured to generate a first token signal; a first phase detector configured to generate first and second outputs based on the first and third clock signals; and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC group and to perform a background calibration to align the third clock signal with the first clock signal.

A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

A time-interleaved analog-to-digital converter includes a plurality of sampling circuits, a plurality of analog-to-digital converter circuits, an output circuit, and a calibration circuit. The plurality of sampling circuits are configured to sequentially sample an input signal to generate a plurality of first signals, in which a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal in a plurality of control signals. The plurality of analog-to-digital converter circuits are configured to generate a plurality of first digital codes according to the plurality of first signals. The output circuit is configured to output a second digital code according to the plurality of first digital codes. The calibration circuit is configured to generate the plurality of control signals and adjust the plurality of control signals according to the second digital code.