70results about How to "Reduce frequency offset" patented technology

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

The invention discloses a frequency offset compensation method, which comprises the following steps that: a base station performs frequency offset estimation on received uplink signals to obtain a frequency offset estimation result, and pre frequency offset compensation is performed on downlink signals according to the frequency offset estimation result; a terminal detects the frequency of the received downlink signals after the frequency offset compensation, the emission frequency of the uplink signals is determined according to the detected frequency of the downlink signals, and the uplink signals are emitted in the determined frequency; and a terminal side performs the pre frequency offset compensation by the same method. The invention also discloses a frequency offset compensation device, which comprises a frequency offset estimation module, a pre frequency offset compensation module and a frequency detection and frequency modulation module. The method and the device can effectively reduce the frequency offset of uplinks and downlinks, perform the frequency offset compensation of the uplinks and the downlinks, and not only reduce the relative frequency offset between the base station and the terminal, but also reduce frequency jump variable when the terminal switches between the base stations, so that both the base station and the terminal can correctly correct the receivedsignals to ensure communication quality.

The invention provides a virtual synchronous generator virtual inertia and virtual damping coefficient adaptive control method, which relates to the technical field of smart grid and intelligent algorithms. Firstly, the inverter based on the virtual synchronous generator is modeled, and the correlation between the output frequency of the inverter and the virtual inertia J and the virtual damping coefficient D is obtained. Then the fitness function of the adaptive control method of virtual inertia J and virtual damping coefficient D based on the improved particle swarm optimization algorithm isdetermined. Finally, the improved particle swarm optimization algorithm is applied to the active power. In the frequency control part, the real-time adaptive control of virtual inertia J and virtualdamping coefficient D is realized in order to minimize the frequency deviation and stabilize the system. The invention provides a virtual synchronous generator virtual inertia and virtual damping coefficient real-time adaptive control method, which fully utilizes the characteristics of the virtual inertia and introduces the virtual damping coefficient, so that the inverter is more stable and the frequency offset is smaller.

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

A method (500) and system for compensation of frequency offset between a first transceiver (102) and a second transceiver (104) in wireless communication are disclosed. The compensation of the frequency offset between two or more transceivers (102, 104) is achieved using frequency synchronization bursts. These bursts contain information about the frequency offset. The frequency synchronization bursts are transmitted by the first transceiver at a range of frequencies above and below its carrier frequency (502). A second transceiver that receives at least one of these bursts (504) determines the frequency offset (504), and adjusts its frequency to match the frequency of the first transceiver (508). Thereafter, the second transceiver may enter a low power sleep mode (510) in order to reduce its power consumption. The second transceiver returns to active mode (512) just before the start of the transmission of the data packets (514).

This invention discloses a method for estimating frequency deviation in OFDM system, which first of all carries out deltafcoarse estimation based on the received front and back two sequences of the received down-line synchronous OFDM symbol, then caries out deltafcoarse adjustment to two arrays of pilot symbols and again carries out deltaffine estimation based on the two arrays of pilot symbols and finally carries out total frequency deviation estimation based on them.

The system comprises a RF receiving subsystem, an A / D converter, a digital baseband signal process subsystem, a digital down-conversion subsystem, a clock subsystem, a MCU subsystem and a frequency automatically-controlling subsystem. The output end of the RF receiving subsystem is sequentially connected to the A / D converter, digital down-conversion subsystem and the output end of the digital baseband signal process subsystem.

A method and system for communication of information in OFDM format are disclosed. The method employs multi-symbol encapsulation (MSE), wherein multiple OFDM symbols are grouped together in cyclic frames having a single cyclic guard portion, for example a cyclic prefix, with multiple OFDM symbols sandwiched between each two consecutive cyclic guard portions. All OFDM symbols of one frame are equalized together at the receiver in a frequency domain using a single DFT / IDFT operation sequence. Embodiments of the MSE OFDM system are disclosed enabling high bandwidth efficiency, high tolerance to carrier frequency offset and low peak-to-average power ratio.

Provided is a battery pack including a battery cell; a ferrite layer at a side surface of the battery cell; a film antenna at a side surface of the ferrite layer; and a reinforcement layer between the battery cell and the ferrite layer.

The invention provides a method and equipment for presetting downlink frequency offset. The method comprises the following steps: determining the uplink frequency offset receiving each uplink signal when the uplink signal transmitted on a public channel by each terminal of a coverage area is received; determining downlink frequency offset when an antenna of a base station transmits a downlink signal on the public channel to each terminal, according to the uplink frequency offset; and compensating the downlink frequency when the antenna of the base station transmits the downlink signal on the public channel according to the downlink frequency offset. According to the method and the equipment, the frequency offset when the downlink signal transmitted on the public channel reaches the terminal.

A PLL circuit arrangement includes a first frequency divider connected to a reference frequency source, a second frequency divider connected to the output of an oscillator controlled by the output of a loop filter, a phase / frequency detector that detects phase / frequency differences between the two divider outputs, a charge pump between the detector and the loop filter, a controller providing a changeable divider ratio to the first and / or second frequency divider, and a regulating signal generator that changes the output voltage of the loop filter applied to the oscillator in a controlled manner in response to a change of the divider ratio. The signal generator preferably has inputs connected to outputs of the controller and the frequency dividers, and an output connected to the charge pump and / or the loop filter to accelerate the recharging thereof in response to a change of the divider ratio.

The acoustic wave device comprises a substrate, a composite layer and an electrode layer which are sequentially stacked from bottom to top, the composite layer is provided with a closed groove in a preset shape, the composite layer comprises a temperature compensation layer and a piezoelectric layer which are stacked from bottom to top, and the electrode layer is located on the upper surface of the composite layer in the groove. Visibly, the composite layer is provided with a groove; the electrode layer is positioned on the upper surface of the composite layer in the groove; when sound waves are propagated along the transverse direction, the sound wave is reflected back by the edge of the piezoelectric layer positioned on the outer side of the groove; the energy of the sound wave is limited below the electrode layer, and transverse energy leakage is reduced; when sound waves are propagated in the longitudinal direction, due to the fact that the propagation speed of the sound waves of the substrate is higher than that of the composite layer, the sound waves are almost propagated only in the composite layer and cannot leak into the substrate, longitudinal energy leakage is restrained, the Q value is increased, and frequency deviation caused by temperature changes can be reduced due to the existence of the temperature compensation layer. The invention further provides a filteringdevice with the advantages.

A phase lock control system is presented for controlling a voltage controlled oscillator. The system includes a voltage controlled oscillator that produces a frequency signal exhibiting an output frequency that varies dependent upon the value of a control voltage applied thereto. A frequency deviation determining system employs a counter intermittently triggered ON for a fixed time by successive timing pulses received from a reference source and a comparator that determines any frequency deviation of the output frequency relative to a preset frequency. An error filter monitors the comparator for any frequency deviation for a plurality of samples of the frequency deviation determinations. A controller varies the control voltage to vary the output frequency in a direction to eliminate any frequency deviation.

A coherent or a noncoherent transmission mode is automatically selected for a transmission on the basis of an estimated Doppler frequency shift due to a motion of a mobile terminal. A coherent mode is selected if a pilot signal overhead is not excessive to uniquely characterize a Doppler frequency shift, as at lower carrier frequency times relative velocity products. A noncoherent mode is selected if a pilot signal overhead would be excessive to uniquely characterize a Doppler frequency shift at higher carrier frequency times relative velocity products. Both the coherent and noncoherent modes have respective advantages for their respective carrier frequency time relative velocity regimes.

Provided is a navigation signal transmitter capable of ensuring reduction in frequency deviation of a terrestrially transmitted navigation signal at low cost. The navigation signal transmitter is operable to receive a transmission wave, generate a synchronization pulse in synchronization with a predetermined data frame, generate an internal clock fundamental oscillation by a reference signal synchronizing section (550) using the synchronization pulse as a reference signal, generate an IMES signal based on the internal clock fundamental oscillation, and transmit the IMES signal. The reference signal synchronizing section (550) comprises a counter circuit (551), a comparator (553), a low-pass control filter (554), a D / A converter (555) and a voltage controlled oscillator (556). The reference signal synchronizing section (550) is configured to, when a magnitude relationship between the number of clock pulses generated in the voltage controlled oscillator (556) using the synchronization pulse as the reference signal and a reference value falls within a predetermined value and continues a predetermined number of times in one direction, adjust a level of control voltage of the voltage controlled oscillator (556).

The invention discloses a method and a system for transmitting upstream signals of a passive optical access network user, belongs to the technical field of fiber optical communication, and solves the problem about upstream signal conflicting of the user so as to improve transmission rate. The method includes: respectively modulating user information on N orthogonal waveform generators, converting into composite output optical signals via a laser; converting the received composite output optical signals into composite electrical signals, and separating N paths of same sub composite electrical signals to recover N paths of different user information. In the system, a signal transmitting terminal comprises N different orthogonal waveform generating circuits, an electric combiner and the laser, a signal receiving terminal comprises a photoelectric detector, an electric branching unit, N relative circuits, N judging regenerative circuits and the N orthogonal waveform generators. Requirements for frequency offset and phase noise are low, dependence on electronic chips is reduced, access capability of user-side data is greatly improved, and the structure and the protocol of a passive optical access network are simplified.

A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

A PLL circuit arrangement includes a first frequency divider connected to a reference frequency source, a second frequency divider connected to the output of an oscillator controlled by the output of a loop filter, a phase / frequency detector that detects phase / frequency differences between the two divider outputs, a charge pump between the detector and the loop filter, a controller providing a changeable divider ratio to the first and / or second frequency divider, and a regulating signal generator that changes the output voltage of the loop filter applied to the oscillator in a controlled manner in response to a change of the divider ratio. The signal generator preferably has inputs connected to outputs of the controller and the frequency dividers, and an output connected to the charge pump and / or the loop filter to accelerate the recharging thereof in response to a change of the divider ratio.

A piezoelectric quartz plate having reduced frequency deviation as a function of temperature, wherein the quartz plate is cut at an angle described by:Tf=⁢3.9+6.5⁢⁢cos2⁢⁢θ+⁢12⁡[c66⁢Tc66⁢sin2⁢θ+c44⁢Tc44⁢cos2⁢θ+Tc14⁢c14⁢sin⁢⁢2⁢⁢θc66⁢sin2⁢θ+c44⁢cos2⁢θ+c14⁢sin⁢⁢2⁢⁢θ]+⁢[a′·(sin⁡(ω·θ+ϕ′)+sin⁡(ω·θ+ϕ′)2)]+δwhere quartz plate thickness is chosen in accordance with a desired frequency. This useful behavior can be manipulated such that a quartz plate is designed to counteract frequency shifts over temperature excursion of other electrical components found in typical oscillator circuits. The choice of angles of cut having larger margins of error means that quartz oscillators can be more easily reproduced on a large scale and at a lower cost than has traditionally been the case.

The invention provides a method and device for estimating frequency deviation compensation. The method comprises: acquiring a maximum correlative value in K correlation processing results of a received signal; acquiring correlative results of same sub frame positions in the K correlation processing results according to the position, in a corresponding sub frame, of the correlation processing result corresponding to the maximum correlative value; merging the acquired K correlative results in order to form a correlation result sequence; performing interpolation on the correlation result sequence to acquire a maximum value point in a correlation function curve; and acquiring a frequency deviation compensation estimating result according to the maximum value point in the correlation function curve. The scheme of the invention may shorten cell search time.

A receiver is tuned to a transmission frequency of a data signal after the receiver has already locked onto a frequency carrying the data signal. A frequency offset between a locked frequency of a tuner on the receiver and the actual transmission frequency is determined by a comparator. If the frequency offset is greater than a threshold value, then the tuner is stepped to another frequency and the frequency offset is determined again. The direction of the tuning step can be determined by comparing multiple frequency offsets. An average value of multiple frequency offset measurements may also be used to determine if the tuner should retune to another frequency by comparison with the threshold value.

The invention discloses a multi-bias voltage-controlled oscillator with a radiation-resistant function. The multi-bias voltage-controlled oscillator comprises a plurality of bias circuits and a plurality of time delay units; each bias circuit is correspondingly connected with a time delay unit; the time delay units are in ring connection to form an annular oscillator; and each bias circuit receives an input control voltage, generates a bias voltage and then provides the bias voltage for the corresponding time delay unit. The multi-bias voltage-controlled oscillator has the advantages of beingsimple in structure, low in cost, resistant to radiation, low in soft error rate and the like.

The invention provides a system for adjusting frequency offset of communication signals, which comprises a signal reception unit, a synchronization unit, a frequency offset estimation unit, a frequency offset configuration unit, a synchronous down-sampling unit, a frequency offset compensation unit and a signal selection unit. The signal reception unit is used for receiving digital sampling signals; the synchronization unit is used for carrying out timing synchronization on the received digital sampling signals; the frequency offset estimation unit is used for estimating frequency offset of the digital sampling singles after timing synchronization; the frequency offset configuration unit is used for configuring frequency offset values for compensating frequency offset of multiple branches according to estimation values of the frequency offset; the synchronous down-sampling unit is used for carrying out synchronous down-sampling on the digital sampling signals after the timing synchronization to obtain sampling baseband signals; the frequency offset compensation unit is used for compensating the frequency offset of the multiple branches according to the frequency offset values and the baseband signals of synchronous down-sampling; and the signal selection unit is used for selecting an optimal signal from the signals after frequency offset compensation. A method for adjusting the frequency offset of the communication signals, provided by the utility model, can effectively reduce frequency offset influence of the system, and improve receiver performance and communication quality of the system.

An apparatus for demodulating a modulated signal comprises an analog to digital converter (2, 12) for converting an analog modulated input signal to a digital signal. The analog to digital converter is arranged to sample the input signal at a predetermined sampling rate. A digital down converter (4, 14) then receives the digital signal at the sampling rate. The digital down converter has an associated digital intermediate frequency and reduces the frequency of the digital signal to one quarter of the sampling rate. A low pass filter (6, 16) filters selected frequencies from the digital signal. A frequency offset stage (8, 18) applies a modification to the frequency of the filtered signal to reduce frequency offset therein, and a differential demodulator (10, 20) demodulates the signal after modifying the frequency to reduce the frequency offset. There is also disclosed a method for demodulating a signal.

A phase lock control system is presented for controlling a voltage controlled oscillator. The system includes a voltage controlled oscillator that produces a frequency signal exhibiting an output frequency that varies dependent upon the value of a control voltage applied thereto. A frequency deviation determining system employs a counter intermittently triggered ON for a fixed time by successive timing pulses received from a reference source and a comparator that determines any frequency deviation of the output frequency relative to a preset frequency. An error filter monitors the comparator for any frequency deviation for a plurality of samples of the frequency deviation determinations. A controller varies the control voltage to vary the output frequency in a direction to eliminate any frequency deviation.

A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal. Correspondingly, the invention also provides a frequency control circuit which include capabilities of reducing more noise as well as tracking larger frequency offset for a data signal.

A modulator (100) comprises a polar generation stage (120) arranged for generating an amplitude component and a phase component of a modulation signal, a differentiator stage (150) arranged for generating a differentiated phase component by differentiating the phase component; and an event detection stage (170) arranged for detecting a high bandwidth event by detecting at least one of the amplitude component and the differentiated phase component meeting an event criterion. An inversion stage (130) is arranged for generating a modified amplitude component by inverting the amplitude component in response to detecting the high bandwidth event. A phase offset stage (150) is arranged for generating a modified differentiated phase component by, in response to detecting the high bandwidth event, adding to the differentiated phase component a phase offset having a magnitude of 180 degrees and a sign opposite to a sign of the differentiated phase component. An amplitude modulation stage (300) is arranged for employing the modified amplitude component to modulate the amplitude of a carrier signal, and a phase modulation stage (200) is arranged for employing the modified differentiated phase component to modulate the frequency of the carrier signal.