248 results about "Voltage-controlled oscillator" patented technology

The invention relates to the technical field of radio frequency integrated circuits, and discloses a low-noise voltage-controlled oscillator circuit which comprises a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration and a source electrode following low-noise bias circuit with digital calibration, the cross-coupled amplifier array is composed of a plurality of units, and the source electrode of the cross-coupled amplifier array suppresses low-frequency noise through a resistance-capacitance feedback network and receives a digital amplitude calibration signal so as to dynamically adjust the number of working units and stabilize the output amplitude; the amplitude self-calibration loop consists of digital logic and a peak detector; the switched capacitor unit array is provided with stable direct-current bias; and a wide linear variable capacitor array driven by the stepped bias voltage. Through deep fusion of digital and analog technologies, the phase noise is remarkably reduced, the linear tuning range is widened, the amplitude stability is ensured, the power consumption is reduced, and the method is particularly suitable for a high-performance radio frequency communication chip of the Internet of Things.

The invention discloses a voltage-controlled oscillator and a sub-sampling phase-locked loop, and relates to the technical field of phase-locked loops. The voltage-controlled oscillator comprises two negative resistance transistors and a three-layer coil structure; the three layers of coil structures are respectively a drain coil, a grid coil and a source coil from outside to inside; the gate coil and the drain coil are both of an octagonal structure, and the source coil is of a splayed structure; the drain coil, the source coil and the grid coil are all provided with center taps, the center tap of the source coil is connected with a power voltage module, the center tap of the drain coil is grounded, and the connection point of the center tap of the source coil and the power voltage module and the connection point of the center tap of the drain coil and the ground are located on the same side of the drain coil. And the two negative resistance transistors are positioned on the other side of the drain coil. According to the invention, automatic alignment of second harmonics in a wide frequency range is realized. And meanwhile, an extra chip area is not increased.

The invention discloses a Colpitts voltage-controlled oscillator based on harmonic tuning, which comprises a differential driving module and a differential resonant cavity, and is characterized in that the differential driving module outputs a differential current signal and is used for providing a differential resonant current for the differential resonant cavity; the differential resonant cavity is used for converting an input differential current signal into a differential voltage signal, and the differential resonant cavity inputs the differential voltage signal into the differential driving module and provides a differential driving voltage for the differential driving module; wherein the differential resonant cavity has two differential-mode impedance peaks and one common-mode impedance peak, and the working frequency of the differential-mode impedance peak working at a high frequency band is increased to about two times based on a coupling effect among own inductors and a synergistic effect of frequency tuning and impedance matching; and meanwhile, the frequency corresponding to the common-mode impedance peak is one to three times of the frequency corresponding to the differential-mode impedance peak, so that the phase noise of the oscillator can be better suppressed, and more excellent comprehensive performance is realized under the condition of realizing higher working frequency.

The utility model discloses a Ka wave band frequency source based on a phase-locked loop structure, which comprises a master controller, a crystal oscillator module, a phase-locked loop module and a frequency doubling processing module, and the phase-locked loop module is respectively connected with the master controller, the crystal oscillator module and the frequency doubling processing module. The phase-locked loop module comprises a power supply module, a phase-locked loop main chip, a loop filter module and a locking state indication module, and the phase-locked loop main chip is respectively connected with the power supply module, the loop filter module, the locking state indication module and the main controller; the frequency doubling processing module comprises a low-pass filter, a high-pass filter, a fixed frequency attenuator, a power amplifier, a frequency doubling chip and a band-pass filter which are connected in sequence, and the input end of the low-pass filter is connected with the output end of the voltage-controlled oscillator. The frequency output by the phase-locked loop module is input to the frequency multiplication processing module, and the frequency multiplication processing module carries out harmonic suppression, attenuation, amplification and frequency multiplication processing on the input frequency, so that the output frequency has the advantages of low phase noise, wide frequency band and high stability.

This invention discloses a pilot-type carrier phase recovery circuit and a reverse antenna array system, belonging to the field of 5G millimeter-wave communication. The pilot-type carrier phase recovery circuit includes a digital phase detector, a quadrature mixer, a quadrature voltage-controlled oscillator, a low-pass filter, a high-pass filter, a polyphase filter, a loop filter, a first intermediate frequency amplifier, a second intermediate frequency amplifier, a first shaping circuit, and a second shaping circuit. Applied to a reverse antenna array system, this invention performs carrier phase recovery on the data signal and pilot signal output from the receiver, separating the data signal without spatial phase information and the spatial phase information used for reverse transmission. This invention enables high-order modulation full-duplex communication and real-time tracking of moving targets, featuring high integration, small area, high communication speed, and strong anti-interference capability.

The invention provides a PLL loop bandwidth adjusting circuit, a control method and a circuit board. The PLL loop bandwidth adjusting circuit comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage-controlled oscillator. The input end of the phase frequency detector is connected with a reference signal; the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter; the second output end of the phase frequency detector is connected with the second input end of the adjustable voltage-controlled oscillator through the phase-locked loop proportional path module; the phase-locked source has the beneficial effects of high flexibility and low power consumption, and is suitable for the technical field of phase-locked sources.

The application discloses a double feedback branch current compensation type charge pump circuit, which comprises a core circuit, a double feedback branch and a bias circuit connected in sequence, wherein the input node of the double feedback branch is connected with the core circuit for detecting the potential change of the output voltage, the first output node of the first feedback branch in the double feedback branch is connected with the gate of the bias circuit, the second output node of the second feedback branch is connected with the bias circuit, and the up and down charging and discharging currents are carried out phased current compensation through the bias circuit according to the degree of the output voltage deviating from the center potential. The application solves the mismatching problem of the up and down charging and discharging currents when the output voltage deviates from the center potential through the double feedback branch, can convert the phase error output by the frequency discriminator into the difference between the charging and discharging currents, charges and discharges the loop filter to generate the control voltage of the voltage controlled oscillator, thereby realizing the lower charging and discharging current mismatching in the wider control voltage range, the smaller ripple on the output voltage, and the optimization of the jitter performance of the output clock of the phase-locked loop.

This invention discloses a reconfigurable injection-locked local oscillator system, comprising a voltage-controlled oscillator (VCO), an injection-locked frequency multiplier (ILL), and an injection-locked amplifier (ILA). The first output terminal of the VCO is connected to the first input terminal of the ILL, the second output terminal of the VCO is connected to the second input terminal of the ILL, the first output terminal of the ILL is connected to the first input terminal of the ILL, and the second output terminal of the ILL is connected to the second input terminal of the ILL. The VCO generates a low-frequency fundamental wave, the ILL multiplier performs frequency multiplication on the low-frequency fundamental wave to generate a second or third harmonic wave, and the ILL amplifies the power of the second or third harmonic wave, thereby improving the accuracy of the output millimeter-wave frequency.

The invention relates to a W-band low-noise voltage-controlled oscillator based on a transformer resonant cavity and harmonic extraction. The W-band low-noise voltage-controlled oscillator comprises a dual-core in-phase coupled oscillator core, a two-bit switched capacitor bank, a linear variable capacitor bank and an output buffer, the dual-core in-phase coupled oscillator core comprises a transformer resonant cavity and a harmonic extraction network, a fundamental wave oscillation signal is generated in the transformer resonant cavity and is coupled and output to the output buffer, and a high-power second harmonic oscillation signal is generated in the harmonic extraction network and is output as a target oscillation signal; the two-bit switched capacitor bank adopts an HBT switch with excellent high-frequency performance, the tuning range of the oscillator is divided into four sub-bands, and the tuning gain is reduced; the capacitance value of the linearized variable capacitor bank is linearly changed along with the tuning voltage height, and a conversion mechanism of flicker noise is inhibited; and the output buffer realizes load isolation and buffering of the fundamental wave oscillation signal. The voltage-controlled oscillator has low tuning gain and high output power in the W wave band, and excellent phase noise is achieved.

The invention discloses a voltage-controlled oscillator circuit, comprising: a current control circuit module configured to receive an input voltage and generate a control current responsive to the input voltage; the ring oscillator circuit module is connected with the current control circuit module and comprises a multi-stage inverter and a current adjusting unit which are connected in series to form a ring; the current adjusting unit is respectively connected to the current control circuit module and each stage of the multi-stage phase inverter, and is configured to synchronously and symmetrically adjust the pull-up current and the pull-down current of each stage of phase inverter in the multi-stage phase inverter in response to the control current; and the output driving circuit module is connected with an output node of the ring oscillator circuit module so as to shape and drive the oscillation signal generated by the ring oscillator circuit module and output a clock signal with a duty ratio of 50%. The circuit structure is simplified, the chip area is saved, the oscillator is allowed to directly work at the target frequency instead of double frequency, and the overall power consumption is reduced.

The invention provides a phase-locked loop rapid locking circuit structure and a control method thereof, the circuit structure comprises a voltage-controlled oscillator, a frequency divider, a phase discriminator and a rapid locking loop filter, and the rapid locking loop filter comprises a capacitive digital-to-analog conversion module. According to the invention, the capacitive digital-to-analog converter module is adopted, and the control voltage of the voltage-controlled oscillator can be rapidly and accurately set based on the charge sharing principle, so that rapid locking is realized; moreover, the structure multiplexes the capacitor in the loop filter, and does not need an extra area. The method has the advantages of high precision, low power consumption and low cost, and has extremely high application value and potential.

The invention relates to a device and method for evaluating the influence of a power supply noise group on phase noise of a phase-locked loop, and relates to the technical field of phase-locked loops, and the device comprises a sine phase discriminator which detects the phase difference between an external reference signal and a feedback signal of a voltage-controlled oscillator; the input end of the loop filter is connected with the output end of the sine phase discriminator; the input end of the voltage-controlled oscillator is connected with the output end of the loop filter; establishing a phase-locked loop simulation model composed of a sine phase discriminator, a loop filter and a voltage-controlled oscillator; selecting a linear voltage-stabilized power supply series, and calculating a phase noise matrix with power supply noise corresponding to each model; different types of linear voltage-stabilized power supplies are respectively used for supplying power, and actually measured phase noise data corresponding to each type are tested and recorded; power supply noise group distribution is fitted by adopting a power law function, and optimal linear voltage-stabilized power supply model selection under the phase-locked loop architecture is determined. The method has the beneficial effects that the accuracy of predicting the phase noise is improved, the optimal solution is realized, and the model most suitable for the phase-locked loop architecture in the LDO series is selected.

The present disclosure provides a voltage-controlled oscillator structure for a communication circuit. The structure includes a cross-coupling circuit and a transmission line module. The cross-coupling circuit has a first transistor, a first capacitor, a second transistor, and a second capacitor. The transmission line module has a first transmission line unit and a second transmission line unit. A transmission line effect of the cross-coupling circuit is eliminated through the transmission line module, so as to reduce phase noise of a voltage-controlled oscillator, thereby further achieving a purpose of increasing a communication frequency range.

Techniques and apparatus for oscillating signal generation using a multi-mode voltage-controlled oscillator (VCO) circuit with transformer-based coupling. An example VCO circuit generally includes a first pair of transistors associated with a first active negative transconductance circuit; a second pair of transistors associated with a second active negative transconductance circuit; a transformer comprising a primary winding and a secondary winding, the primary winding being coupled to the second pair of transistors; a first set of switches coupled between gates of the first pair of transistors and the secondary winding of the transformer; and a second set of switches coupled between the gates of the first pair of transistors and a first voltage node.

The utility model provides a linear frequency modulation transmit-receive assembly with a silence function, which relates to the technical field of signal processing, and comprises a transmitting link, a receiving link and an auxiliary signal processing module, a voltage-controlled oscillator circuit of the transmitting link generates a microwave signal, and finally an isolator circuit transmits the signal. Signal processing and controllable silence of a transmitting path are ensured; and the receiving link carries out front-end processing on the received signal and carries out frequency mixing on the received signal and the local oscillator signal distributed by the directional coupler circuit to generate a beat signal, and the beat signal is further amplified by the intermediate frequency amplifier and then output. According to the utility model, silent signals are received through the enabling ends of the first power conversion chip A1 and the second power conversion chip A2, and power supply of the coupler circuit and the attenuator circuit of the transmitting link is directly cut off, so that compared with a traditional signal path cut-off mode, signal leakage or residual radiation can be thoroughly avoided, and the transmission efficiency is improved. The transmitting terminal is ensured to completely stop working in a silent state, and the requirement of a high-concealment scene is met.

This invention relates to the field of phase-locked loop (PLL) technology, specifically to a method for achieving low jitter over a wide locking range by optimizing the PLL structure. The method includes: outputting a first error signal through a phase detector, obtaining the characteristics of the first error signal, and constructing a first error signal function; obtaining a first adaptive loop bandwidth; constructing a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs in multiple frequency bands; during PLL locking, selecting a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; and calculating the root mean square (RMS) of the first error signal based on further analysis of the first error signal characteristics, and combining the initial feedback gain and the initial error signal RMS to obtain a first feedback gain adjustment value. This invention achieves low jitter over a wide locking range through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

The half-bridge LLC circuit comprises an LC filter circuit, an MOS tube bridge arm, a capacitor bridge arm, a resonant inductor Lr, a transformer, a diode D1, a diode D2, a diode D3, a diode D4, a filter capacitor Co, a resistor RL, a compensator, an amplitude limiter, a voltage-controlled oscillator, a PWM controller, an isolation driver, a comparator and a PI controller. According to the invention, the problems of loss, electromagnetic interference and the like caused by improvement of the switching frequency of the existing hard switching circuits such as forward and half-bridge circuits in the space navigation secondary power supply system are solved.

The invention belongs to the field of integrated circuit design, particularly relates to a fractional frequency divider circuit based on a digital time converter, and aims to solve the performance bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse swallowing multi-modulus frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse swallowing multimode frequency divider receives an output signal of the voltage-controlled oscillator, and outputs a signal D1 and a time sequence control signal after frequency division processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing signal, and outputs a delayed clock signal to counteract a quantization error. The femtosecond-level time delay circuit adopts an optimized circuit architecture design, has the characteristics of simple structure and low power consumption, realizes femtosecond-level time delay precision and high linearity, effectively inhibits phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the frequency spectrum purity and the system suitability of a clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of wireless communication, radar and the like are met.

The invention relates to the field of integrated circuits, and discloses a low-phase noise signal source circuit and radar equipment, and the low-phase noise signal source circuit comprises a four-core F23 type voltage-controlled oscillator which is used for generating a fundamental frequency, a second harmonic and a third harmonic; the harmonic self-mixer is connected with the quad-core F23 type voltage-controlled oscillator, and is used for mixing the fundamental frequency and the third harmonic into a quadruplicated frequency signal and outputting the quadruplicated frequency signal, and mixing the fundamental frequency and the fundamental frequency into a secondary frequency multiplication signal and outputting the secondary frequency multiplication signal; and the amplifier is connected with the harmonic self-mixer and is used for amplifying the quadruplicated frequency signal and outputting the amplified quadruplicated frequency signal. The signal source circuit can generate quadruplicated frequency signals.

Embodiments herein disclose an inductor-capacitor voltage controlled oscillator (LC-VCO) circuit. The LC-VCO circuit includes: an LC tank circuit including a center tap inductor connected in parallel with a capacitor bank without a varactor, where the LC tank circuit resonates to generate an oscillation voltage; and a control circuit connected to a varistor capacitance circuit, where the varistor capacitance circuit includes a varistor based on a voltage controlled transistor in series with at least one capacitor, the varistor capacitance circuit is connected in parallel with the LC tank circuit and connected to a negative transconductance circuit. The control circuit includes an error amplifier and a conversion circuit, and is configured to generate an output control voltage based on an input phase-locked loop (PLL) control voltage that controls a capacitance value of the varistor capacitance circuit through the variable resistor.

Provided is a clock generating apparatus including a voltage control oscillator that outputs a clock corresponding to a control voltage which is input, a control voltage generator that generates the control voltage corresponding to a difference between a frequency of the clock and a target frequency, a starting voltage generator that generates a starting voltage which is supplied to the voltage control oscillator during a start period of the voltage control oscillator, and a starting circuit that sets the control voltage to the starting voltage during the start period after a start-up of the voltage control oscillator.

The invention discloses a voltage-controlled oscillator, which belongs to the technical field of electronic circuits and comprises a source follower circuit, a pull-down circuit, a pull-up circuit and a plurality of delay circuits. The source follower circuit generates a regulating voltage according to a control voltage and an enable signal. When the regulating voltage conducts a first path in the pull-down circuit, the pull-down circuit pulls down the level of a first node to the ground so as to generate a pull-down signal through the first node. When the regulating voltage conducts a second path in the pull-up circuit, the pull-up circuit transmits the regulating voltage to a second node so as to generate a pull-up signal through the second node. The plurality of delay circuits are configured as a ring oscillator and are started according to the pull-down signal and the pull-up signal so as to generate an output oscillation signal according to the control voltage.

The present application relates to the field of integrated circuit design, in particular to a clock source with temperature process voltage compensation. The present application improves the existing temperature process compensation module, so that the temperature process compensation module can compensate the voltage variation of temperature and process at the same time; a selection module is added between the temperature process compensation module and the voltage controlled oscillator, the four variation voltages output by the temperature process compensation module are compared, the largest variation voltage under the current temperature condition is selected as the compensation voltage Vctrl and output to the voltage controlled oscillator; at this time, the control voltage obtained is a curve fitted by straight lines with different slopes, which can be applied to the case of large frequency and large temperature variation, the fitting is very good, and the output frequency error is very small.

An apparatus, comprising: a first upper voltage rail; a lower voltage rail; a set of voltage controlled oscillator (VCO) active cores, wherein one or more of the set of VCO active cores is selectively coupled to the first upper voltage rail based on a control signal, wherein the set of the VCO active cores are coupled to the lower voltage rail or the one or more of the set of VCO active cores is selectively coupled to the lower voltage rail based on the control signal; and a tank circuit coupled to the set of VCO active cores.

In a start-up sequence of a phase-locked loop, the voltage-controlled oscillator is controlled by a first voltage to operate in a linear regime and a first count of a register of a frequency divider is read. Then, the voltage-controlled oscillator is controlled by a second voltage having an offset from the first voltage and a second count of the register is read. A slope of the linear regime is then determined from a difference between the first and second counts and an offset of the first and second voltages. A determination is made of a third voltage needed to reach a target frequency of the output signal as a function of the slope and a deviation between a current value of the register count and a target value corresponding to the target frequency. The voltage-controlled oscillator is then controlled with the third voltage.

The invention belongs to the technical field of radio frequency integrated circuits, and discloses a switch-free three-coupling dual-core four-mode voltage-controlled oscillator which comprises a first voltage-controlled oscillator unit, a second voltage-controlled oscillator unit, a third voltage-controlled oscillator unit, a fourth voltage-controlled oscillator unit, a first three-coupling inductance network, a second three-coupling inductance network and a four-mode switch switching network. The first three-coupling inductor network and the second three-coupling inductor network are the same in structure and each comprise a first inductor group, a second inductor group and a third inductor group. The four-mode switch switching network is respectively connected with the positive end and the negative end of the first voltage-controlled oscillator unit, the positive end and the negative end of the second voltage-controlled oscillator unit, the positive end and the negative end of the third voltage-controlled oscillator unit and the positive end and the negative end of the fourth voltage-controlled oscillator unit. And the switching of four working modes is realized. The method is suitable for obtaining voltage-controlled oscillators with different working modes, and has the characteristics of high linearity, low phase noise and wide tuning range.

A method of operation for a dual mode Phase-Locked Loop (PLL) for phase coherent application includes selecting one of a non-coherent mode and a coherent mode. The non-coherent mode includes controlling a Voltage Controlled Oscillator (VCO) with a first error voltage determined by a first Low Pass Filter (LPF), the first LPF configured to filter a first output of a phase detector, the phase detector configured to determine a phase difference between a reference frequency and a feedback signal derived from a VCO frequency generated by the VCO. The coherent mode includes controlling the VCO with the first error voltage and a second error voltage determined by a second LPF of a Proportional and Integral Controller (PIC) configured to filter the first output of the phase detector and by a time variant proportional gain configured to modify a second output of the second LPF.

A phase-locked loop and a method for generating an output clock with reduced jitter. The phase-locked loop with reduced jitter comprises a phase detector for comparing a phase of a reference clock with a phase of a feedback clock to generate a plurality of up and down control signals; a voltage-controlled oscillator for generating an oscillation signal according to the plurality of up and down control signals; an output divider for dividing the oscillation signal to generate the output clock; a non-integer feedback divider for dividing the oscillation signal according to a modulated sequence to generate a modulated clock; a divider in series with the non-integer feedback divider and for dividing the modulated clock by a fixed modulus to generate a divided clock; wherein a frequency of the modulated clock is an integer multiple of a frequency of the divided clock, and one of the modulated clock and the divided clock is used as the feedback clock.

This invention relates to the field of high-speed signal transmission technology, specifically to a differential multi-band voltage-domain cross-voltage-domain voltage-controlled oscillator (VCO) for suppressing power supply noise. It includes a frequency and phase detector, a charge pump, a low-pass filter, a VCO_BIAS module, and a voltage-controlled oscillator unit. The charge pump and low-pass filter generate a differential control voltage; the VCO_BIAS module receives the differential control voltage and converts it into a differential current; the voltage-controlled oscillator unit receives the differential current; the VCO_BIAS module integrates a bias structure to suppress power supply noise, reducing the sensitivity of the tail current transistor of the voltage-controlled oscillator unit to power supply noise due to channel length modulation effects, and improving the jitter of the phase-locked loop (PLL) output frequency. In this invention, by constructing a differential structure, a cross-voltage-domain design, and tunable bias and load, a wide frequency range output under low-voltage power supply is achieved, and clock jitter caused by power supply noise is effectively suppressed.