43results about "Angle modulation" patented technology

A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.

A 4 frequency-shift keying (4FSK) transceiver is provided. The 4FSK transceiver includes both a 4FSK transmitter and a 4FSK receiver. The 4FSK transmitter includes a voltage-controlled oscillator (VCO) and two data links coupled to the VCO for delivering two parallel streams of input data bits to the VCO. For each pair of parallel input data bits received from the two data links, the VCO outputs a modulated signal having one of four operating frequencies via 4FSK modulation. Separately, the 4FSK receiver includes a power divider, for dividing the multi-frequency modulated signal into two paths of two binary bit streams, and a pair of low-noise amplifiers (LNAs) separately coupled to the two paths and configured as a pair of band-pass filters for filtering two different subsets of the four operating frequencies from the two binary bit streams into two filtered binary bit streams.

A demodulator (114) comprising the following: a recipient; and a DCR circuit (200) wherein the DCR circuit (200) alternates between the following: a detection mode wherein the DCR circuit (200) operates with a circular gain block (204) having a first circular gain and a first accumulation value to identify a plurality of harmonic interference frequencies, including an interference frequency at 2480 MHz that coincides with a center frequency of a Bluetooth Low Energy radio, resulting from a 16 MHz clock frequency oscillator; and a tracking mode, wherein the DCR circuit (200) operates with the circular gain block (204) which has a second circular gain and a second accumulation value, wherein: the second loop gain is smaller than the first loop gain; wherein each of the first and second loop gains is restricted to powers of 2 and is implemented as bit shifts over a system of registers, where the second accumulation value is defined by multiplying the first accumulation value by the first loop gain and dividing by the second loop gain; a time control for switching between the acquisition mode and tracking mode is programmable; and The DCR circuit (200) re-identifies the interference frequencies each time the receiver is switched from an off state to an on state.

Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

A clock gating system and device are provided. According to one general aspect, a device may include: a latch circuit configured to transmit a clock signal as an output signal based in part on a state or at least one enable signal. The latch circuit may include: an input stage controlled by a clock signal and one or more enable signals. The latch circuit may include: an output stage configured to generate an output signal. The input stage and the output stage may share a common transistor controlled by the clock signal.

The invention relates to an FMCW-based level measuring device (1) that can operate in two clearly distinct frequency bands: For this purpose, the level measuring device (1) comprises two high-frequency units (11, 12) each with a frequency-controllable oscillator (111, 112) in order to transmit radar signals (S) in the frequency bands according to the FMCW principle. HF1,2 ) to generate or, after reflection from the surface of the contents, to receive. An antenna arrangement (13) serves to transmit and receive the radar signals (S HF1, 2) towards the filling material (L) and for reception after reflection at the filling material surface, wherein a control / evaluation unit (14) is used based on the received signal (R) HF1,2The level measuring device (1) can determine the fill level (L) using the first or second frequency band. According to the invention, the level measuring device (1) is characterized by a common clock unit (15). This unit serves to form a phase-locked loop with both the first oscillator (111) and the second oscillator (121) in order to generate the corresponding radar signals (S) according to the FMCW principle. HF1,2 , R HF1,2 ) of both frequency bands. This eliminates the need for a complete phase-locked loop for each frequency band. As a result, the number of required components is reduced.

The interface between clock domains in an integrated circuit (IC) depends on the synchronization of the phase-locked loops (PLLs) that generate the clocks in the different domains and how each PLL responds to the jitter of a shared reference clock. The well-controlled, identical bandwidth (and loop dynamics) of these PLLs ensures that the reference jitter contribution is identical or even negligible. As a key component determining digital PLL bandwidth, the digitally controlled oscillator (DCO) can vary in gain due to process, temperature, and power supply IR drop between chips or modules. A calibration circuit provides gain correction factors to achieve the DCO's nominal gain and the desired / target PLL loop bandwidth. In some examples, the calibration circuit for each PLL determines the gain correction factor that results in a common jitter response for the PLLs and stores the gain correction factor in the calibration circuit.

The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond 4G communication systems such as Long Term Evolution (LTE). Specifically, the embodiment of the invention provides a method executed by a first node in a wireless communication system and the first node, the method provides a new signal generation scheme, the method comprises the following steps: acquiring configuration information, the configuration information comprising information related to a data modulation mode; a first angle related to data modulation is determined based on the configuration information, and a baseband signal is generated based on the first angle.

The invention discloses a core circuit for realizing accurate modulation and demodulation based on differential signal coupling design, and the core circuit comprises a differential signal coupling module which is used for converting an input signal into a differential positive signal and a differential negative signal, and outputting the differential positive signal and the differential negative signal; the signal acquisition module is used for receiving the differential positive signal and the differential negative signal and outputting an acquisition signal; the self-adaptive filtering module is used for receiving the acquisition signal and outputting a filtering control signal; the fuzzy logic control module is used for receiving the acquisition signal and outputting a mode control signal; the threshold value control module is used for outputting a protection trigger signal based on the abnormal threshold value; and the modulation-demodulation module is used for adjusting working parameters based on the filtering control signal and the mode control signal. Therefore, the signal imbalance can be accurately compensated by combining the differential signal with the self-adaptive filtering module, modulation and demodulation can be dynamically optimized through the fuzzy logic control module, and the modulation and demodulation accuracy is remarkably improved.

The oscillator includes a reference current generating circuit, a voltage modulator circuit, and an oscillating circuit. The reference current generating circuit is arranged to generate a reference current. The voltage modulator circuit is arranged to receive a feedback voltage, and perform a voltage modulation operation according to a first reference voltage and the feedback voltage, to generate a modulated voltage. The oscillating circuit is coupled to the reference current generating circuit and the voltage modulator circuit, and arranged to generate an oscillation signal with an oscillation frequency according to the reference current and the modulated voltage.

Embodiments of the present disclosure relate to the field of phase-locked loops technology, and disclose a phase-locked loop, a radar system and a method for randomizing initial phases of FMCW signals. The phase-locked loop includes a phase-locked loop circuit (100) and a stochastic control signal generator (200). In response to a respective clock signal of the plurality of clock signals indicating a respective target moment of one or more target moments, the stochastic control signal generator (200) inputs a stochastic control signal to the phase-locked loop circuit (100), so that the accumulated value of the plurality of fractional frequency division values of the phase-locked loop circuit (100) is converted into a random value, and that a plurality of initial phase differences respectively corresponding to the plurality of chirp signals output by the phase-locked loop circuit (100) form a non-arithmetic sequence. A plurality of pieces of velocity information resulting from the spurious signals are distributed over different velocity dimensions. In this way, a strength of the spurious signals on individual velocity dimension can be decreased, and the two false targets having fixed velocities can be prevented from occurring, thereby improving the detection accuracy of the radar system. Moreover, the plurality of chirp signals can have random phases, thereby improving the anti-interference ability of the radar system.

A system and method for accurately determining the distance between two network devices using channel sounding is disclosed. Each network device guarantees a fixed phase relationship between the transmit and receive circuits. In one embodiment, this is accomplished by incorporating a frequency divider within a phase locked loop. The frequency divider can have a reset such that the frequency divider can be initialized to a predetermined state. Furthermore, by utilizing a frequency divider with a reset configured within the phase locked loop, the clock of the transmit and receive circuits that the quadrature signal generator outputs are guaranteed to have a constant phase relationship.

A 4 frequency-shift keying (4FSK) transceiver is provided. The 4FSK transceiver includes both a 4FSK transmitter and a 4FSK receiver. The 4FSK transmitter includes a voltage-controlled oscillator (VCO) and two data links coupled to the VCO for delivering two parallel streams of input data bits to the VCO. For each pair of parallel input data bits received from the two data links, the VCO outputs a modulated signal having one of four operating frequencies via 4FSK modulation. Separately, the 4FSK receiver includes a power divider, for dividing the multi-frequency modulated signal into two paths of two binary bit streams, and a pair of low-noise amplifiers (LNAs) separately coupled to the two paths and configured as a pair of band-pass filters for filtering two different subsets of the four operating frequencies from the two binary bit streams into two filtered binary bit streams.

To provide a frequency modulation device and frequency modulation method, capable of reducing noise generated in the frequency modulation device and noise contained in a demodulation signal due to non-linearity of a voltage-controlled oscillator, and capable of suppressing increase of unwanted harmonic wave signals at demodulation.SOLUTION: A frequency modulation device according to the invention further includes: a pulse count detector (111) for demodulating a frequency modulated signal (51) and outputting a pulse density modulated signal (52); and a one-bit counter (303) for re-converting the pulse density modulated signal (52) to a frequency modulated signal (58), a feedback circuit (115) takes the pulse density modulated signal (52) as a demodulation signal (53).SELECTED DRAWING: Figure 5

A method of controlling a frequency-modulated oscillator 110 of a phase-locked loop circuit 100 is described, wherein the oscillator 110 comprises a bank of capacitors 413. The method comprises the steps of (i) switching a capacitor 414 of the bank of capacitors 413 to change an output frequency 1050 of an output signal 112 of the oscillator 110 from a first frequency 1051 to a second frequency 1052, (ii) determining a frequency information associated with the capacitor 414 and based on at least one of the first frequency 1051 and the second frequency 1052; and (iii) writing the frequency information to a look-up table 224, 225, 226 stored in a control unit 120 of the oscillator 110. A corresponding frequency-modulated oscillator 110 and phase-locked loop circuit 100 are also described.

Methods, systems, and devices for wireless communication are described. In some systems, a second network entity (e.g., a transmitting device) may transmit first signaling to a second network entity (e.g., a receiving device) to indicate one or more frequency domain residual sideband (FDRSB) parameters associated with the second network entity. The FDRSB parameters may be associated with an imbalance between an in-phase component and a quadrature phase component of the first signaling. The second network entity may generate and transmit second signaling that is configured to have the one or more FDRSB characteristics. The first network entity may determine whether the second network entity is a source of the second signaling based on the one or more FDRSB characteristics of the second signaling and the one or more FDRSB parameters indicated by the first signaling.

Interfaces between clock domains of an integrated circuit (IC) depend on synchronization of phase-locked loops (PLLs) that generate clocks in the different domains and on how each PLL responds to jitter in a shared reference clock. The well-controlled same bandwidth (and loop dynamic) for those PLLs renders the same and, therefore, ignorable reference jitter contribution. As a key component that determines a digital PLL bandwidth, digitally controlled oscillator (DCO) may have its gain vary with process, temperature, and supply IR drop from chip to chip or even module to module. A calibration circuit provides a gain correction factor to achieve a nominal gain in DCO as well as a desired / target PLL loop bandwidth. In some examples, the calibration circuit in each PLL determines a gain correction factor that causes the PLLs to have a common jitter response and stores the gain correction factors in the calibration circuits.

An electronic device is provided. The electronic device includes a substrate and a plurality of modulation units. The plurality of modulation units are disposed on the substrate. Each of the modulation units includes a first electronic element and a second electronic element, a first signal line, a second signal line, and a third signal line. The first signal line provides a first voltage to the first electronic element. The second signal line provides a second voltage to the second electronic element. The third signal line provides a third voltage to the first electronic element and / or the second electronic element. The first voltage is different from the second voltage, and the third voltage is different from the first voltage and / or the second voltage. The electronic device of the embodiments of the present disclosure has modulation units capable of modulating the phase, bandwidth, intensity, or polarization state of electromagnetic waves.

To provide a frequency delta-sigma modulation signal output circuit capable of generating a frequency delta-sigma modulation signal with reduced noise components.SOLUTION: A frequency delta-sigma modulation signal output circuit includes: a phase modulation circuit that generates a phase modulation signal by generating n delay signals by delaying a signal under measurement, where n is any integer greater than or equal to 2, and randomly selecting one of the n delay signals in synchronization with the signal under measurement; and a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase modulation signal.SELECTED DRAWING: Figure 1

To provide a modulation device and a modulation method capable of generating a wideband FM signal by suppressing frequency variation with a low cost electric component.SOLUTION: According to the present invention, a modulation device includes a multiplication PLL for generating a multiplication FM signal by multiplying N times a center frequency fck / L of an original FM signal generated on the basis of a system clock being a frequency fck and a frequency band W, an LO generation heterodyne PLL for controlling a VCO such that a difference frequency between a local frequency-divided signal of a frequency fLO / M generated from a local signal of a frequency fLO outputted by the VCO and a clock frequency-divided signal of a frequency fck / K approaches a frequency fxo of a reference signal, and a mixer for lowering the multiplication FM signal only by the frequency fLO to output it as a wideband FM signal.SELECTED DRAWING: Figure 1

A pulse width modulation system includes a plurality of module building blocks One control board is a master control board and others are slave control boards. Each slave control board determines a fictive master board timer based upon timer information received via a communication bus, and synchronizes the timer rate of a slave board timer to a timer rate of the master control board, or of an external timer rate. The timer information includes interlacing angle information defining an interlacing point for each of the control boards receiving the timer information. The interlacing angles are determined in relation to each other such that variation of a predetermined operation parameter, related to loads connected to pulse width modulated phase outputs of function modules, is minimized. At least two control boards, for which the interlacing angles are determined, are arranged to control function modules at different module building blocks.

A device for transmitting data includes a transmitter for generating a frequency-modulated output signal. The transmitter includes a phase-locked loop for adjusting an output frequency of the output signal to a carrier frequency, and a coupling circuit for coupling a data stream into the phase-locked loop. The output signal modulated in frequency by the coupled-in data stream has an output frequency variable over time, and the coupling circuit includes a compensation unit, which couples a compensation signal into the phase-locked loop. The compensation signal compensates at least approximately for an adjustment of the output frequency to the carrier frequency carried out by the phase-locked loop.

The invention discloses a pulse modulation system and method based on a neural network, and the method comprises the steps: firstly processing an input symbol bit stream through a pulse position modulation module, extracting a position-related symbol bit through an MLP, converting the position-related symbol bit into a normalized current value, and transmitting the normalized current value into a pulse neural network; controlling the occurrence time of a pulse time domain and outputting a pulse position vector by utilizing a membrane potential accumulation characteristic and a time-varying discharge threshold value of linear decline in a symbol period; extracting phase correlation symbol bits through a pulse phase modulation module, distributing the phase correlation symbol bits to positive and negative parallel channels, adjusting the phase based on a pulse position vector, and generating a pulse vector with position and phase characteristics; and finally, expanding the discrete vector into a continuous time domain pulse signal by a transposed convolutional layer. According to the invention, the limitation of hardware adaptability and expansibility of a traditional pulse modulation system is overcome, and an efficient and flexible scheme compatible with various pulse modulation variants is provided for the field of Internet of Things and wireless communication.

A wireless communication device includes a receiver circuit, a phase shift control circuit, and a digital phase-locked loop (DPLL) circuit. The receiver circuit includes a down-converter circuit that is used to apply down-conversion to an input signal according to a local oscillator (LO) signal. The phase shift control circuit is used to generate a phase shift signal. The DPLL circuit is used to generate the LO signal locked to an initial frequency under a frequency-lock state. In response to the phase shift signal, the DPLL circuit is further used to make the LO signal have a different frequency without leaving the frequency-lock state.

Frequency signal generator (100), comprising: a phase-controlled loop (110) configured to generate and provide a frequency signal (112); a frequency control unit (120) connected to the phase-locked loop and configured to generate a frequency control signal (122), wherein the phase-locked loop (110) is configured to change a frequency of the frequency signal (112) based on the frequency control signal (122); and a fault detection unit (130) configured to receive the frequency control signal (122), detect a fault in the frequency control signal, and provide a fault signal, wherein the fault signal includes information about a detected fault; the fault detection unit (130) includes a comparison unit configured to compare the frequency control signal (122) or comparison information derived from the frequency control signal with a reference comparison signal or reference comparison information; and the fault detection unit (130) includes a hash value generator configured to generate the comparison information by determining characteristic hash values ​​based on the frequency control signal (122).

The oscillator includes a reference current generating circuit, a voltage modulator circuit, and an oscillating circuit. The reference current generating circuit is arranged to generate a reference current. The voltage modulator circuit is arranged to receive a feedback voltage, and perform a voltage modulation operation according to a first reference voltage and the feedback voltage, to generate a modulated voltage. The oscillating circuit is coupled to the reference current generating circuit and the voltage modulator circuit, and arranged to generate an oscillation signal with an oscillation frequency according to the reference current and the modulated voltage.

Disclosed are a phase modulation surface unit, a phase modulation surface structure, and a terminal device. The phase modulation surface unit includes at least two phase-shifting layers which are stacked, where the phase-shifting layers each include: a first substrate; a second substrate; the first phase-shifting surface layer including at least one first electrode pattern extending in a first direction; the second phase-shifting surface layer including at least one second electrode pattern extending in a second direction and has one-to-one correspondence to the first electrode pattern, and the orthographic projection of the second electrode pattern on the first substrate intersecting with that of the corresponding first electrode pattern on the first substrate; and an tunable dielectric layer between the first phase-shifting surface layer and the second phase-shifting surface layer.

An electronic device, including a substrate and multiple modulation units, is provided. The modulation units are disposed on the substrate. Each modulation unit includes a first electronic element, a second electronic element, a first signal line, a second signal line, and a third signal line. The first signal line provides a first voltage to the first electronic element. The second signal line provides a second voltage to the second electronic element. The third signal line provides a third voltage to the first electronic element and / or the second electronic element. The first voltage is different from the second voltage, and the third voltage is different from the first voltage and / or the second voltage.

The invention discloses a broadband microwave vector signal source system and an implementation method thereof, relates to the technical field of microwave signals, and is characterized in that a digital technology and an analog technology are combined, a digital modulation signal is generated by utilizing an FPGA (Field Programmable Gate Array), and a fixed quadrature modulation analog output signal is generated through a DAC (Digital-to-Analog Converter) (containing a quadrature modulator); according to the broadband microwave vector signal source system, the frequency of the broadband microwave vector signal source system is reduced, the frequency of the broadband microwave vector signal source system is reduced, the frequency of the broadband microwave vector signal source system is increased, the frequency of the broadband microwave vector signal source system is increased, the frequency of the broadband microwave vector signal source system is increased, and the consistency of indexes is well guaranteed.

The invention discloses a modulation-demodulation circuit applied to impedance method human respiration detection, relates to the technical field of integrated circuits, and particularly relates to a modulation-demodulation circuit applied to impedance method human respiration detection, which comprises a phase inverter I 1, a phase inverter I 2, a single-pole double-throw switch SPDT1, a single-pole double-throw switch SPDT2 and a single-pole double-throw switch SPDT3, the single-pole double-throw switch SPDT1, the single-pole double-throw switch SPDT2 and the single-pole double-throw switch SPDT3 are connected with an RE switch SPMODCLK, an RE switch MODVEN, an RE switch SPMODP and an RE switch SPMODN; the device further comprises a chopping demodulation circuit, a control signal generation circuit and a modulation-demodulation circuit. According to the modulation-demodulation circuit applied to impedance method human body respiration detection, the novel impedance method respiration detection modulation-demodulation circuit is simple in structure and low in power consumption, the problems of circuit complexity, power consumption, envelope detection'threshold effect 'and the like of a traditional modulation-demodulation circuit are solved, and the respiration detection effect with high accuracy is achieved.