237 results about "Time-to-digital converter" patented technology

The invention relates to the technical field of high-speed digital interfaces, and discloses a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, and the system comprises a main node which generates and dynamically distributes clock signals, and constructs a dynamic clock tree structure; the slave equipment is used for realizing cascade error elimination through a distributed compensation mechanism; the dynamic phase compensation engine adopts a hybrid phase detection framework and is combined with a digital-to-time converter (TDC) and an analog phase-locked loop (PLL); and the environment parameter compensation module is used for collecting temperature, voltage and operation time in real time, and calculating phase compensation quantity through a formula that delta phi = alpha * (T-T0) + beta * (V-V0) + gamma * delta t. On the aspect of synchronization precision, the phase error of a single device can be smaller than or equal to + / -200ps, the strict scene requirement is effectively met, the environment adaptability is high, the defects of traditional fixed compensation can be overcome, cascade error accumulation can be efficiently restrained through distributed compensation of slave devices, and on the aspect of real-time performance, an online calibration module can conduct real-time calibration without interrupting services.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention discloses a single-photon non-vision-field target tracking system based on an unmanned aerial vehicle platform, which belongs to the field of non-vision-field imaging and is characterized in that a laser is connected with a scanning galvanometer assembly through a first nanosecond optical path switch and an optical fiber circulator to form an emission optical path for emitting laser pulses to relay reflecting surfaces corresponding to four predetermined positioning points; the scanning galvanometer assembly is connected with the photon detector through the collimating optical fiber, the optical fiber circulator and the second nanosecond optical path switch to form a receiving optical path capable of receiving echo photons; the main control module is electrically connected with the laser, the first nanosecond light path switch, the second nanosecond light path switch, the scanning galvanometer assembly, the photon detector, the time-to-digital converter and the high-frequency inertial measurement unit respectively, and can control each component to perform laser ranging, double-window gating, single-photon detection, inertial measurement unit sampling and timing according to a unified time sequence; and the three-dimensional coordinates of the current non-vision target are calculated by using the distance measurement data through an ellipsoid intersection solution method, so that non-vision target tracking is realized.

According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

An interface circuit according to the present invention comprises: a source clock reception circuit that receives a source clock; and a plurality of reception lanes that each receive reception data. Each of the plurality of reception lanes includes: a data line that transmits the reception data; a sampling clock line that transmits a sampling clock generated on the basis of the source clock; a sampler circuit that samples the reception data on the basis of the sampling clock; and an eye-monitoring circuit that includes a TDC circuit and is provided in parallel with the sampler circuit with respect to the data line and the sampling clock line. On the basis of a reference clock generated on the basis of the source clock, the TDC circuit monitors a TDC input signal generated on the basis of the reception data or the sampling clock and generates characteristic information of the reference clock and the reception data.

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention relates to a two-step time-to-digital converter and a method thereof, a phase-locked loop and an analog-to-digital converter. The method comprises the following steps of: performing N1-stage delay on a reference signal rs in sequence, and performing coarse quantization on the delayed signal of each stage relative to a feedback signal fb; when the two signals are different, after the time t1 is delayed, the first arriving signal is selected as a time starting signal Start and the fb is delayed for the time t1 and then serves as a time stopping signal Stop in the delayed period, and when the two signals are the same, the rs is selected as Start after the time t2 is delayed, and the fb is selected as Stop after the time t2 is delayed; performing fine quantization formation on the Start and the Stop; and decoding the code into n1-bit high-bit binary codes and decoding the code into n2-bit low-bit binary codes. The technical problem that the area and power consumption of an existing two-step TDC are increased due to the fact that the number of logic gates of a selector is greatly increased along with the increase of coarse quantization bits is solved.

The invention discloses a multichannel clock buffer test system and method, and relates to the technical field of semiconductor testing, and the method comprises the steps: calibrating the delay of an optical clock signal of each time-to-digital converter node to a preset precision threshold value; a standard clock signal is injected into the clock buffer input channel, and the clock buffer is driven to enter a working state; triggering a time-to-digital converter array by using the calibrated optical clock signal, collecting timestamp data of each output channel of a clock buffer, and generating an original time data set; inputting the original time data set into a double-mixing processor, and outputting a multi-channel skew parameter and a three-dimensional cloud picture; the multi-channel skew parameter is converted to a life indicator value for each output channel of the clock buffer based on the multi-channel skew parameter invoking a material model. According to the invention, the original time data set is subjected to two times of frequency mixing processing through the double frequency mixing processors, and phase detection and spectrum analysis are combined, so that high-precision extraction of the time deviation value of each output channel of the clock buffer is realized.

A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

An optical sensor includes an integrated circuit including an array of time-to-digital converters and a first array of interconnects connected to the array of time-to-digital converters. A plurality of single photon avalanche photodiode circuits includes a second interconnect. Each of the plurality of single photon avalanche photodiode circuits corresponds to a single pixel. The plurality of single photon avalanche photodiode circuits are individually arranged on the integrated circuit with the second interconnect of the plurality of single photon avalanche photodiode circuits connected to a corresponding one of the first interconnects of the integrated circuit.

A method for measuring a time-of-flight interval in a depth sensing system includes generating a coarse time count using a global clock signal shared across a plurality of pixels and external to the sensor array, wherein the coarse time count provides the most significant bits of the time-of-flight interval free of inter-pixel process variation; generating an intermediate time count within a pixel using a local ring oscillator based on completed oscillation cycles during a measurement interval; generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides the least significant bits; and deriving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

The application relates to a delay calibration circuit for a time-to-digital converter. The delay calibration circuit comprises a frequency discriminator, a charge pump, a filtering capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is used for receiving a starting signal and outputting a feedback signal after time delay; the frequency discriminator is used for receiving the starting signal and the feedback signal, converting a phase difference between the starting signal and the feedback signal into a voltage pulse signal, and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with a corresponding pulse width to the filtering capacitor under the control of the voltage pulse signal; the filtering capacitor is used for converting the current signal into a time delay control voltage, and applying the time delay control voltage to an input end of the bias voltage generating unit; the bias voltage generating unit is used for generating a bias voltage under the action of the time delay control voltage, and controlling a delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit is convenient to realize and high in precision.

There is provided an apparatus for processing timestamps generated by two or more time-to-digital converters (TDCs) that comprises: at least two TDCs, a reference clock, a counter and a stream generator that output a timestamp data stream (TD #1), a first input signal that is periodic or quasi periodic, a second input signal, an electronic circuit or computer program that takes said timestamp data stream as an input and generates a new timestamp data stream (TD #2). Said electronic circuit or computer program performs refining and rescaling calculations thereby providing means to enhance the accuracy of a plurality of timestamps and to express a plurality of timestamps in a different time reference frame.

The invention relates to an image sensing device and an operation method thereof. Disclosed is an image sensing apparatus capable of detecting a distance to a target object according to a time of flight (TOF) method. The image sensing apparatus includes: a pixel configured to generate a pulse signal based on photons reflected from a target object, the pixel including a light receiving element whose sensitivity is controlled according to a quenching control voltage; a time-to-digital converter (TDC) configured to count a number of photons to output a photon count value; and a controller configured to adjust a level of the quenching control voltage based on the photon count value.

Embodiments of a clock synchronization unit of an all-digital phase-locked loop (ADPLL), a successive approximation register (SAR) time-to-digital converter (TDC) of the ADPLL, and a clock synchronization method in the ADPLL are disclosed. In one embodiment, the clock synchronization unit of the ADPLL includes a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation instead. Other embodiments are also described.

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

An analog to digital converter (ADC) circuit including: a voltage-controlled delay circuit (VCDC) configured to: sample a received analog signal based on an input clock signal to generate analog signal samples; generate an output signal representative of the input clock signal shifted in the time domain with a delay based on the analog signal samples; and a time to digital converter (TDC) coupled to the voltage-controlled delay circuit and configured to generate a digital output signal based on the output signal.

This invention discloses a time-to-digital converter and its time margin extraction circuit, comprising multiple time margin extraction units; a first OR gate, with multiple input terminals receiving first output signals from the multiple time margin extraction units respectively, and an output terminal providing a second start signal; a second OR gate, with multiple input terminals receiving second output signals from the multiple time margin extraction units respectively, and an output terminal providing a second stop signal; each time margin extraction unit includes a first flip-flop, with its input terminal connected to a first input signal and a set terminal of a first pseudo-flip-flop, and its set terminal connected to the first stop signal and the input terminal of a second pseudo-flip-flop; a second flip-flop, providing a first output signal based on the output signal of the first flip-flop and the first input signal; and a third flip-flop, providing a second output signal based on the output signal of the first flip-flop and the second input signal, thereby improving the measurement accuracy of the time-to-digital converter and its continuous measurement capability.

The circuit includes a time-to-digital converter (TDC) (102) to generate an output signal that is a function of the time difference between a first input clock to the TDC (102) and a second input clock to the TDC (102). A first delay line (502) adds a time delay to a third clock to generate the first input clock. A pseudo-random binary sequence generator (504) generates a pseudo-random binary bit sequence (PRBS) to vary the amount of time delay added to the third clock by the first delay line.

A droop detector includes a phase generator generating a pulse responsive to a clock signal; an edge detector generating a first signal in response to the pulse; and a time-to-digital converter that includes N time-to-digital converter units. The time-to-digital converter generates an N-bit value representative of the timing difference between the edge of the pulse and the first signal. A capacitance associated with a subset of the time-to-digital converter units is adjusted during a calibration time to cause the difference between the arrival times of the data and clock at the jth time-to-digital converter unit to be greater than the difference between arrival times of the data and clock at the (j+1)th time-to-digital convert unit. The data terminal of the flip-flop of each time-to-digital converter unit is responsive to the first pulse, and the clock terminal of the flip-flop of each time-to-digital converter unit is responsive to the first signal.

Embodiments of the present invention relate to a ToF system. In one embodiment, a method includes: resetting respective count values ​​of a plurality of analog counters to initial count values, each analog counter in the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; receiving a plurality of digital addresses from a time-to-digital converter (TDC) after resetting the respective count values; during an integration period, for each received digital address, selecting an analog counter based on the received digital address and changing the respective count value of the selected one analog counter by a discrete amount toward a second count value, wherein each analog counter has a final count value at the end of the integration period; and after the integration period, determining a corresponding final bin count for each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

The invention relates to the field of laser radars, and particularly discloses a high-speed small target detection system based on photon detection and a use method, and the system comprises a laser emission module, an optical module, a detection module and a control module. And the laser emission module is coaxially fixed with the detection module and is connected with the optical module and the control module. The laser transmitting module is used for receiving a synchronizing signal and transmitting pulsed light; the optical module is responsible for collimated emission of laser beams and collection of target echo signals; the detection module realizes accurate time marking of each photon event based on a single photon array detector and a time-to-digital converter; the control module is responsible for system synchronization control, timestamp data processing, space-time photon correlation analysis and real-time estimation and prediction of target three-dimensional motion parameters. The technical scheme provided by the invention has the advantages of high sensitivity, high time resolution, high refresh rate and strong anti-interference capability, and is suitable for real-time detection and trajectory reconstruction of high-speed small targets.

The invention discloses an all-digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, and the phase-locked loop comprises a time-to-digital converter which is implemented based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; the digital loop filter is realized based on high-level integration and is used for outputting a frequency control word according to the phase error signal; the numerical control oscillator is realized based on the IP core and is used for outputting a digital sine wave signal according to the frequency control word; and the feedback frequency divider is realized based on high-level integration and is used for outputting a feedback clock signal according to the digital sine wave signal. According to the all-digital phase-locked loop, the modules in the all-digital phase-locked loop are strategically divided, high-level synthesis and register transfer level design are strategically combined, the all-digital phase-locked loop which is high in performance and efficiency and can be stably locked is achieved, and the all-digital phase-locked loop can be widely applied to the technical field of digital circuit design.

An electronic device may include a receiver coupled to an antenna over a transmission line. The receiver may include a set of sample and hold circuits coupled in parallel between the transmission line and at least one pulse modulator. The pulse modulator(s) may be coupled between the sample and hold circuits and at least one time-to-digital converter (TDC). Each sample and hold circuit may be clocked using a different respective phase of a clock signal. During signal reception, the antenna may receive a radio-frequency signal. The sample and hold circuits may convert the radio-frequency signal into analog signals using the different phases of the clock signal. The pulse modulator(s) may convert voltages of the analog signals into pulse widths in at least one analog pulse width modulation (PWM) signal. The TDC(s) may convert the analog PWM signal(s) into digital codes.

An embodiment of the present disclosure provides a time-to-digital converter and a control method. The time-to-digital converter includes: at least one time-to-digital conversion unit, the time-to-digital conversion unit including a delay locking module and a signal acquisition module, the delay locking module and the signal acquisition module including a common delay link, the time-to-digital converter having a delay locking mode and a time-to-digital conversion mode; in the delay locking mode, the delay locking module locks the basic delay time of the delay link; in the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link based on the basic delay time of the delay link to determine a signal time difference.

A device comprises a quantum random number generator, and further comprises following device parts: a first SPAD diode, a second SPAD diode, an optical fiber which optically couples the first SPAD diode and the second SPAD diode to one another, an amplifier and / or filter, an analog-to-digital converter, a comparator, a time-to-digital converter, and an entropy extraction device converting output values of the time-to-digital converter into first and second values and generates random bits therefrom.

The invention provides a laser radar ranging method and system using a single photon avalanche diode. A laser radar range finding method using a single photon avalanche diode comprises the following steps: generating and emitting a laser pulse sequence, the laser pulse sequence comprising a plurality of pulses, the plurality of pulses having a plurality of time intervals, each time interval being an integral multiple of the resolution of a time-to-digital converter, the sum of all the time intervals is a preset fixed value, so that the duration of a single measurement period is fixed; receiving an echo signal reflected by a target by using a single photon avalanche diode detector, and quantizing the echo signal into a receiving vector by using a time-to-digital converter; and performing cross-correlation operation on the receiving vector and a transmitting vector corresponding to the laser pulse sequence, and calculating a target distance according to a peak value position of a cross-correlation operation result. According to the invention, hardware cost is reduced, and high-efficiency ranging with a stable frame rate is realized at the same time.

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.