28 results about "Time-to-digital converter" patented technology

An optical sensor includes an integrated circuit including an array of time-to-digital converters and a first array of interconnects connected to the array of time-to-digital converters. A plurality of single photon avalanche photodiode circuits includes a second interconnect. Each of the plurality of single photon avalanche photodiode circuits corresponds to a single pixel. The plurality of single photon avalanche photodiode circuits are individually arranged on the integrated circuit with the second interconnect of the plurality of single photon avalanche photodiode circuits connected to a corresponding one of the first interconnects of the integrated circuit.

This invention discloses a time-to-digital converter and its time margin extraction circuit, comprising multiple time margin extraction units; a first OR gate, with multiple input terminals receiving first output signals from the multiple time margin extraction units respectively, and an output terminal providing a second start signal; a second OR gate, with multiple input terminals receiving second output signals from the multiple time margin extraction units respectively, and an output terminal providing a second stop signal; each time margin extraction unit includes a first flip-flop, with its input terminal connected to a first input signal and a set terminal of a first pseudo-flip-flop, and its set terminal connected to the first stop signal and the input terminal of a second pseudo-flip-flop; a second flip-flop, providing a first output signal based on the output signal of the first flip-flop and the first input signal; and a third flip-flop, providing a second output signal based on the output signal of the first flip-flop and the second input signal, thereby improving the measurement accuracy of the time-to-digital converter and its continuous measurement capability.

A phase-locked loop (PLL) circuit, an operating method thereof, and a sub-range control circuit are provided. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sigma-delta modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal according to an input frequency signal and a feedback signal. The processing circuit limits a voltage level corresponding to the charging current signal within a certain voltage range according to a prediction signal to generate a digital output. The loop filter is coupled to the TDC to perform a low-pass filtering operation according to the digital output. The DCO generates a DCO frequency signal according to an output of the loop filter. The feedback circuit generates the feedback signal according to the DCO frequency signal. The sigma-delta modulator (SDM) generates a phase signal representing accumulated phase shift information to the prediction circuit according to information of the feedback circuit and fractional frequency information. The prediction circuit generates the prediction signal according to the phase signal.

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

This application provides a phase-locked loop (PLL), a control method, and a frequency source. It includes a controller, a time-to-digital converter (TD-to-digital converter), an arithmetic logic unit (ALU), a digitally controlled oscillator (DCO), and a frequency divider. The DCO outputs a linearly swept frequency signal based on a frequency control signal from the ALU. The frequency divider generates a divided frequency signal based on the output frequency of the DCO. The TD-to-digital converter outputs the phase difference between the divided frequency signal and a reference signal. The ALU outputs a frequency control signal based on the phase difference and a control code to adjust the output frequency of the DCO. The controller acquires the output signal of the TD-to-digital converter after a step point in the division ratio, and adjusts the control code until the output signal of the TD-to-digital converter after the step point is zero when the output signal is not zero. This method improves the linearity of the sawtooth waveform generated by the PLL at the step point.

A sensor arrangement for high-resolution imaging using a common connection between a single-photon avalanche diode (SPAD) and a time-to-digital converter (TDC), comprising: a) a two-dimensional array of SPADs arranged in rows and columns, each SPAD being connected to a quench circuit (QU) that generates a digital pulse for each SPAD event; b) a row connection and a column connection, each QU of the SPAD array being connected to the row and column connections; c) a plurality of TDC channels, each assigned to either a specific row or a specific column of the SPAD array, the TDC channels being driven by a common clock generator and having N stages, and the TDC channels being configured to measure the time interval between the occurrence of a SPAD event and the clock signal;d) Synchronization means to ensure synchronous operation of the TDC channels assigned to the rows and columns of the SPAD array; e) A measuring device for acquiring the measurement results from the TDC channels assigned to the rows and columns of the SPAD array; f) Comparison means for comparing the measurement results from the row and column TDC channels to identify the SPAD source associated with a particular SPAD event; and g) Sorting means for matching the identified SPAD event to the corresponding histogram of the source SPAD.

This invention belongs to the technical field of time-to-digital converters (TD-SCDs), specifically disclosing a circuit and method for extracting the quantization margin of a time-to-digital converter. This invention adds an XOR gate and a transmission gate unit to the existing time-to-digital converter to extract the time margin, and outputs it through a dynamic OR gate. The circuit provided by this invention can extract the time margin that the time-to-digital converter cannot quantize, accurately measure the quantization error, and thus allow for further measurement of the time margin, improving the overall measurement accuracy of the time-to-digital converter. The circuit and method provided by this invention can not only extract the time margin that the time-to-digital converter cannot quantize, but also accurately determine the position of the trigger signal in the delay chain.

This invention provides a lidar ranging method and system using a single-photon avalanche diode (SPAD). The lidar ranging method using a SPAD includes the following steps: generating and transmitting a laser pulse sequence, the laser pulse sequence containing *n* pulses, with *n* time intervals between the *n* pulses, wherein each time interval is an integer multiple of the resolution of the time-to-digital converter (TD-SCDMA), and the sum of all time intervals is a preset constant value to fix the duration of a single measurement cycle; receiving the echo signal reflected from the target using a SPAD detector, and quantizing the echo signal into a received vector using the TD-SCDMA; performing a cross-correlation operation between the received vector and the corresponding transmitted vector of the laser pulse sequence, and calculating the target distance based on the peak position of the cross-correlation result. This invention achieves high-efficiency ranging with a stable frame rate while reducing hardware costs.

Aspects of the disclosure include a spatially distributed depth sensor array for vehicle sensing. An exemplary spatially distributed depth sensor array includes a 1 by N array of unit cells. Each unit cell includes a receive pixel having at least one single photon avalanche photodiode (SPAD) vertically stacked over at least one time-to-digital converter (TDC), a transmit pixel having at least one vertical cavity surface emitting laser (VCSEL), and a backplane. The receive pixel and the transmit pixel are integrated onto a surface of the backplane to define a respective unit cell. The backplane is configured to receive time-of-flight (TOF) signals from the at least one SPAD responsive to detection of a photon emitted from the at least one VCSEL.

Embodiments of a sampling system and a method for sampling are disclosed. In an embodiment, a sampling system includes a sampler array that includes sampling cells, a timing controller connected to the sampler array to form a closed loop and configured to correct a timing mismatch in the sampler array, and a time to digital converter (TDC) configured to perform indexing of the sampling cells in the sampler array.

This invention provides a fully digital phase-locked loop (PLL) and its locking method, comprising: dividing the output frequency of a numerically controlled oscillator (CNC) into N frequency bands through pre-calibration, and obtaining the input control word range corresponding to each frequency band, where N is a natural number greater than 1; setting the input control word of the CNC oscillator according to the locking frequency; inputting a reference signal and a feedback signal to a time-to-digital converter (TD-SCDC); and switching the loop state of the fully digital PLL from open-loop to closed-loop when the value of the phase digital signal output by the TD-SCDC meets a preset condition. By setting the input control word of the CNC oscillator according to the locking frequency, the phase of the feedback signal output by the CNC oscillator is made close to the phase of the reference signal, thereby making the value of the phase digital signal output by the TD-SCDC close to 0, thus enabling the loop state of the fully digital PLL to be quickly switched to closed-loop, solving the problem of how to shorten the locking time of the fully digital PLL.

Aspects of the present disclosure include spatially distributed depth sensor arrays for vehicle sensing. An example spatially distributed depth sensor array includes a 1 x N array of unit cells. Each unit cell includes a receiving pixel having at least one single photon avalanche photodiode (SPAD) vertically stacked above at least one time-to-digital converter (TDC), a transmitting pixel having at least one vertical cavity surface emitting laser (VCSEL), and a backplane. The receiving pixel and the transmitting pixel are integrated onto a surface of the backplane to define a respective unit cell. The backplane is configured to receive a time-of-flight (TOF) signal from the at least one SPAD in response to detecting a photon emitted from the at least one VCSEL.

The application discloses a design method of a time-to-digital converter based on a negative feedback time error amplifier, and relates to the field of semiconductor integrated circuit chip design. Specifically, the application is characterized in that: a traditional time-to-digital converter with a single delay chain is analyzed, the relative error of two delays is taken as the conversion precision, a high-precision time-to-digital converter with a Vernier delay chain is designed, coarse adjustment is realized, a time-to-digital converter with a multi-stage phase interpolation technology is used to improve the precision, fine adjustment is realized, the coarse adjustment and the fine adjustment are combined, a time error amplifier is inserted, a high-precision time-to-digital converter based on a time error amplifier is obtained, and the output signal of an SR latch is fed back to the input, and a plurality of time-to-digital converters based on the time error amplifier are cascaded. According to the method that the output signal of the SR latch is fed back to the input, the overall linearity of the time error amplifier is improved, and the design freedom of the time-to-digital converter can be greatly improved by using the time error amplifier based on the negative feedback.

A CMOS integrated chip (1) comprising a time-to-digital converter (TDC) circuit (2) for light detection and ranging (lidar) applications, the chip comprising a start channel (10) comprising an input (11) for a start signal (ST) and at least one stop channel (20, 30) comprising an input (21, 31) for a stop signal (SP). It further comprises a TDC element (40) for each of the start and stop channels (10, 20, 30), wherein the TDC element (40) is configured to store a respective count when triggered by the start signal (ST) or the stop signal (SP), respectively. It further comprises a computing unit (50) coupled to each TDC element (40) and configured to determine a time difference (AT) associated with the start signal (ST) and the stop signal (SP) based on said counts, and an instruction-driven communication interface (60) comprising at least two bidirectional data pins (63, 64). Furthermore, a time-of-flight measurement system and a method of operating a CMOS integrated chip (1) are provided.

The application discloses a decimal error estimation circuit applied to a full-digital phase-locked loop, comprising a time-to-digital converter and an encoding circuit, a period average module, a period normalization module, a first multiplier and a complement circuit; wherein the time-to-digital converter and the encoding circuit, the period average module, the period normalization module, the first multiplier and the complement circuit are sequentially connected. The application realizes the calculation of the decimal phase error in the full-digital phase-locked loop through the time-to-digital converter and the encoding circuit, the period average module, the period normalization module, the first multiplier and the complement circuit. The main advantages of the application are that the circuit structure is simple, the portability is strong, the design is flexible and the cost is low.

Embodiments of the present application relate to the field of quantum ranging positioning, and in particular to an automatic tracking ranging positioning system based on quantum entangled signals. A specific embodiment of the system comprises: a quantum entangled light source outputs an entangled photon pair as a reference light beam and a signal light beam; the reference light beam is transmitted into a time-to-digital converter; the signal light beam is transmitted into a first input-output port of a fiber-optic circulator; the signal light beam is transmitted into a beam transceiver; the signal light beam is transmitted to an angle reflector at a target point to be measured, and the reflected signal light beam is transmitted into the fiber-optic circulator; the reflected signal light beam is transmitted into a second photon detector; the reflected signal light beam is transmitted into a time-to-digital converter; the arrival time sequences of reference photons and signal photons corresponding to the reference light beam and the reflected signal light beam, respectively, are detected; and based on the arrival time sequences of the reference photons and the signal photons, target point coordinate information of the target point to be measured is determined. This embodiment can realize the functions of automatic tracking and rapid ranging positioning of a moving target.

Device (01) for examining body tissue (02) by acoustic spectroscopy, comprising an ultrasound transmitter (03) for emitting an ultrasound transmission signal (35, 36, 37, 38, 39, 40, 41), an ultrasound receiver (04) for receiving a reflected and / or transmitted ultrasound reception signal after passing through the body tissue (02) to be examined, wherein the transmitter (03) is capable of emitting multiple ultrasound transmission signals (35, 36, 37, 38, 39, 40, 41) of different frequencies f1 to f n , where n is greater than 1, and the receiving device (04) is designed to receive corresponding ultrasound receiving signals of different frequencies, characterized by that the device (01) comprises a first processing unit (10), a second processing unit (11), a signal switch (09), a storage unit (17) and an evaluation unit (25), wherein the first processing unit (10), which includes a time-to-digital converter, can determine frequency-dependent transit time values ​​(16) of the associated ultrasound signal from each transmit and receive signal pair, wherein the second processing unit (11) can determine frequency-dependent attenuation values ​​(20) of the associated ultrasound signal from each transmit and receive signal pair, wherein the signal switch (09) is arranged between the ultrasound receiving unit (04) on the one hand and the two processing units (10, 11) on the other, and wherein the received ultrasound receiving signal can be routed to both processing units (10, 11) in parallel by means of the signal switch (09). where in the storage device (17) for each of the frequencies f1 to f n the transmission time values ​​(16) and attenuation values ​​(20) determined for the various transmit and receive signals can be stored at least temporarily as a result data set (21), and wherein a qualified value for describing the examined body tissue (02) can be derived from the result data set (21) in the evaluation device (25).

An optoelectronic device (10) is configured as a self-mixing interferometer and comprises a laser (11), a driver (20) with an output coupled to the laser (11), a signal input (21), a comparator (22) with an input (23) coupled to the signal input (21), a time-to-digital converter (25) with an input (26) coupled to an output (24) of the comparator (22), and a signal evaluation circuit (30) with an input (31) coupled to an output (27) of the time-to-digital converter (25) and with an output (32). The signal evaluation circuit (30) is configured to provide an output signal (SOUT) at the output (32). Moreover, a method for generating an output signal (SOUT) is provided.

The present disclosure provides a digital phase-locked loop, DPLL, including a time-to-digital converter, TDC, configured to generate a digital phase signal indicative of a phase difference between a reference signal and a feedback signal; a digitally controlled oscillator, DCO, configured to generate an output signal based on a control signal, wherein the output signal of the DCO is fed back as the feedback signal to the TDC; and a digital loop filter, DLF, configured to process the digital phase signal to generate the control signal for the DCO, wherein the DLF includes a noise cancellation path, or digital noise cancellation block, configured to generate a noise cancellation signal for suppressing DCO phase noise based on the digital phase signal.

The application provides a time measurement method based on FPGA and an FPGA time-to-digital converter. The method comprises the following steps: inputting a pulse signal into each carry chain to obtain a thermometer code; obtaining an upper half edge timing code and a lower half edge timing code according to the thermometer code; detecting a level jump of a first local tap group and a second local tap group to generate an up edge trigger flag and a down edge trigger flag; taking an up edge original fine time value and a down edge original fine time value obtained according to a fine counting value coding rule as an address to address a modified lookup table of the carry chain, and obtaining an up edge fine time value and a down edge fine time value; performing an average operation on each carry chain to obtain the up edge fine time value and the down edge fine time value; and splicing the up edge coarse counting value and the up edge fine time value to obtain an up edge time stamp, and splicing the down edge coarse counting value and the down edge fine time value to obtain a down edge time stamp. The application can realize double edge detection and improve time measurement precision.

A time to digital converter including multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different transition delays of each buffer. The buffers may be configured to be compatible with a standard cell layout. The buffers may be configured as standard cell logic gate with modified connections. The buffers may be calibrated by selecting a fastest delay value that does not cause overflow in response to a calibration pulse.

The application discloses a kind of parallel MicroLED optical interconnection's synchronous control method and system, applied to parallel MicroLED optical interconnection's synchronous control system, system includes sending end and receiving end, method includes: sending end original transmission data is issued to each MicroLED drive unit, by each MicroLED drive unit according to synchronous reference clock and delay calibration parameter control corresponding MicroLED emits light at predetermined time;Receiving end receives the parallel optical signal of each transmission channel, reads the actual arrival time stamp of the parallel optical signal of each transmission channel recorded by time-to-digital converter, and determines data alignment reference channel according to the actual arrival time stamp corresponding to each transmission channel respectively;Receiving end carries out delay compensation to other transmission channels according to the time offset between other transmission channels and data alignment reference channel, so that after each transmission channel is aligned in time dimension, the electrical signal data of its own transmission channel is output, and original transmission data is obtained.

The application belongs to the technical field of ship management monitoring and management, and particularly relates to a non-invasive calibration system for ship pipeline pressure instrument based on ultrasonic measurement. The system comprises a control module, a transmission driving module, an ultrasonic wave transmission module, an ultrasonic wave timing module and an ultrasonic wave receiving module. The control module comprises an STM32 main control chip. The transmission driving module is composed of an NPN triode, a current limiting resistor and a coupling capacitor. The ultrasonic wave transmission module comprises a timer chip and a timer power supply circuit. The ultrasonic wave timing module comprises a TDC time-to-digital converter, a high-precision digital timing chip and a peripheral circuit. The ultrasonic wave receiving module comprises an ultrasonic wave transducer, an impedance matching and signal coupling circuit, a multi-stage amplification circuit, a band-pass filter circuit and a peak detection and comparison circuit. The application is mainly used for completing non-invasive pipeline liquid pressure instrument field calibration and avoiding the application limitation of traditional pressure instrument calibration and detection scheme in the corresponding scene.

This application provides a lock detection circuit and an offset correction phase-locked loop, relating to the field of integrated circuit technology. It includes a phase sequence determination module for receiving up and dn signals from a frequency and phase detector, and outputting a leading signal and a lagging signal. The frequency and phase detector compares the frequency and phase of a reference clock with a feedback clock, and outputs up and dn signals based on the comparison result. The leading signal is the phase-leading signal between the up and dn signals, and the lagging signal is the phase-lagging signal between the up and dn signals. A time-to-digital converter, connected to the phase sequence determination module, receives the leading and lagging signals, quantizes the phase difference between them, and outputs the corresponding digital codeword. A comparator module, connected to the time-to-digital converter, compares the digital codeword with a preset reference value and outputs a lock indication signal. The solution provided in this application has the advantage of enabling phase detection in high-speed scenarios.

An electronic device includes a logic controller, a time digital converter, and a clock adjustment circuit. The logic controller receives a clock signal and generates a first signal and a second signal according to the clock signal. The first signal leads the second signal by a first time difference. The time digital converter includes a plurality of delay circuits, receives the first signal and the second signal, and enables the second signal to catch up with the first signal in a second time difference through the delay circuits. The clock adjustment circuit adjusts the frequency of the clock signal according to the sum of the first time difference and the second time difference respectively calculated in the previous and subsequent periods of the clock signal.

This application relates to a code density calibration method and system based on dark counting. The method includes: setting a SPAD in Geiger mode under no-light conditions; generating a Poisson-distributed dark counting pulse unrelated to the TDC clock using thermal perturbation; using this pulse as a trigger signal to acquire and convert raw code during non-measurement periods / independent channels; recording the frequency of each unit using a counter array; calculating the total number of samples and the system period; calculating the calibration results of each unit, as well as differential and integral nonlinear indices; calculating the correction time value based on the indices; storing the calibration time in on-chip storage using the raw code as an index; constructing a calibration lookup table; during actual detection, using the raw code to address and look up the table, reading the calibration time and combining it with the coarse count to synthesize a high-precision result. This method can improve the measurement accuracy, stability, and environmental adaptability of a high-precision time-to-digital converter.

A time to digital conversion circuit includes a pulse signal generator configured to generate a pulse signal in response to activation of a transition detection signal, a latch circuit configured to latch a multiphase clock signal in response to a trailing edge of the pulse signal, an upper time to digital converter (TDC) configured to latch, in response to activation of a timing signal, a code whose value changes at the same period as a period of the multiphase clock signal, and a synchronization circuit. The latch circuit forms a lower TDC. The synchronization circuit supplies a signal synchronized by receiving the transition detection signal at a timing decided in accordance with a signal generated by the lower TDC as the timing signal to the upper TDC.

This invention discloses an electronic device for correcting time-dependent drift in a clock signal within a chip. The device includes a logic controller, a time-to-digital converter, and a clock adjustment circuit. The logic controller receives the clock signal and generates a first signal and a second signal based on the clock signal. The first signal leads the second signal by a first time difference. The time-to-digital converter includes multiple delay circuits that receive the first and second signals and use these delay circuits to allow the second signal to catch up with the first signal over a second time difference. The clock adjustment circuit adjusts the frequency of the clock signal based on the sum of the first and second time differences calculated for the preceding and following periods of the clock signal.