Time-to-digital converter chip

Abstract

A CMOS integrated chip (1) comprising a time-to-digital converter, TDC, circuit (2) for light detection and ranging, lidar, applications, comprises a start channel (10) comprising an input (11) for a start signal (ST), and at least one stop channel (20, 30) comprising an input (21, 31) for a stop signal (SP). It further comprises a TDC element (40) for each of the start and stop channels (10, 20, 30), wherein the TDC element (40) is configured to store respective counts when triggered by the start signal (ST) or the stop signal (SP), respectively. It further comprises a calculation unit (50) coupled to each TDC element (40) and configured to determine a time difference (ΔT) associated with the start signal (ST) and the stop signal 8SP) based on the counts, and an instruction driven communication interface (60) comprising at least two bidirectional data pins (63, 64). Further, a time-of-flight measurement system and a method of operating the CMOS integrated chip (1) is provided.

Description

[0001] Description

[0002] Time-to-digital converter chip

[0003] The present application relates to a CMOS integrated chip comprising a time-to-digital converter circuit , a time-of- flight measurement system, and a method of operating a CMOS integrated chip comprising a time-to-digital converter circuit .

[0004] A time-to-digital converter, TDC, is a device used to measure a time interval and convert it into digital output . It allows measurements of very short times at high resolution . A TDC may be used for light detection and ranging, lidar, for example , to measure the time an emitted light signal like a laser pulse needs to travel to a reflecting obj ect and back to the camera . Lidar applications may be used in time-of- f light , ToF, cameras .

[0005] However, there are requirements for lidar TDC including high measuring rates , high time resolution, fast readout , minimal pulse width and low noise . Moreover, fabrication costs should be low . Conventional TDC chips may miss at least some features that are exclusively suited for lidar measurements to ful fill the above-mentioned requirements .

[0006] At least one obj ect of particular embodiments is to provide an improved time-to-digital converter chip .

[0007] This obj ect is achieved with the subj ect-matter of the independent claims . Embodiments and developments derive from the dependent claims . According to at least one embodiment , a CMOS integrated chip comprising a time-to-digital converter, TDC, circuit for light detection and ranging, lidar, applications is provided . The CMOS integrated chip may be called chip in the following . That the chip is CMOS integrated can mean that circuits on the chip are formed by CMOS ( Complementary Metal-Oxide- Semiconductor ) fabrication steps . Apart from the TDC circuit the chip may comprise further circuits or components . The TDC circuit may be especially suited for lidar applications but can be used for other applications as well .

[0008] According to at least one embodiment , the chip comprises a start channel comprising an input for a start signal . The start signal can be an electrical signal . For example , the start signal is provided by an external microcontroller . It is also possible that the start signal is generated internally . The start signal may be configured to indicate the beginning of a measurement cycle . The input of the start channel may comprise one or more pins of the chip . For example , the input is reali zed as low-voltage di f ferential signaling, LVDS , interface comprising two pins for a positive and a negative start signal . The start channel may comprise further components , for example an edge detector .

[0009] According to at least one embodiment , the chip comprises at least one stop channel comprising an input for a stop signal . The chip may comprise a plurality of stop channels , in particular two stop channels . The stop signal can be an electrical signal . For example , the stop signal is provided as detection signal by a receiver or detector that sense a laser pulse . The stop signal may be configured to indicate the detection of the laser pulse . More than one stop signals may be provided to the input of the at least one stop channel during one measurement cycle . The input of the stop channel may comprise one or more pins of the chip . For example , the input is reali zed as low-voltage di f ferential signaling, LVDS , interface comprising two pins for a positive and negative stop signal . The stop channel may comprise further components , for example an edge detector .

[0010] According to at least one embodiment , the chip comprises a TDC element for each of the start and stop channels , wherein the TDC element is configured to store respective counts when triggered by the start signal or the stop signal , respectively . This can mean that the chip comprises a plurality of TDC elements . In particular, the chip may comprise one or more TDC elements for the start channel , one or more TDC elements for each stop channel and / or one or more TDC elements for a clock channel . The TDC element may be implemented as sample-and-hold registers , for example as flip- flop . Each TDC element may be coupled to a ring oscillator, in particular to a common ring oscillator . The counts to be stored by the TDC element may correspond to a respective state of the ring oscillator when the start signal or, respectively, the stop signal is provided . For example , the counts correspond to time units that are defined by the ring oscillator . As such, the time at which a respective signal is provided can be converted into a digital signal . Each stop signal may correspond to one laser pulse detection . Such detection or measurement signal may be called hit event in the following . Each TDC element may be configured to store more than one hit event . For example , the hit event is stored in a respective hit buf fer .

[0011] According to at least one embodiment , the chip comprises a calculation unit coupled to each TDC element and configured to determine a time di f ference associated with the start signal and the stop signal based on the counts . As each signal is associated with a respective time at which the signal is provided to the chip, a time di f ference between the start and a respective stop signal can be determined . The time di f ference can be expressed as digital value based on the counts associated with the signals . The calculation unit can be coupled to the TDC elements via respective hit buf fers at which the hit events are stored .

[0012] According to at least one embodiment , the chip comprises an instruction driven communication interface comprising at least two bidirectional data pins . That the communication interface is instruction driven can mean that data can be trans ferred to or from the chip via respective commands provided to the communication interface . For example , the communication interface is configured to receive a read command . The read command can speci fy a speci fic address of a memory element comprised by the chip . For example , the memory element comprises one or more buf fers or other storage components of the chip, at which present or previous measurement results are stored . It is also possible that the chip receives configuration data over the communication interface . Further, the chip may send an interrupt signal via the communication interface , for example to indicate to a microprocessor that readout can be started . The chip may distinguish di f ferent instructions by speci fic operation codes , opcodes . The communication interface may comprise further bidirectional data pins , for example at least four bidirectional data pins . It may further comprise a select pins and / or a clock pin . By means of the communication interface the chip can be configured and data, in particular measurement data from various hit events , can be read out . According to at least one embodiment , a CMOS integrated chip comprising a time-to-digital converter, TDC, circuit for light detection and ranging, lidar, applications , comprises a start channel comprising an input for a start signal . It further comprises at least one stop channel comprising an input for a stop signal . It further comprises a TDC element for each of the start and stop channels , wherein the TDC element is configured to store respective counts when triggered by the start signal or the stop signal , respectively . It further comprises a calculation unit coupled to each TDC element and configured to determine a time di f ference associated with the start signal and the stop signal based on the counts . It further comprises an instruction driven communication interface comprising at least two bidirectional data pins .

[0013] The CMOS integrated chip described here is based on the following considerations , among others .

[0014] There is a plurality of requirements for lidar time-to- digital conversion . For example , a lidar TDC chip has to provide various measuring rates , for example from 200kHz to 4MHz , to cover typical measuring ranges , for example from 600m ( outdoor applications like hunting or gol f ) via 300m ( range of moving obj ects ) via 150m ( industrial applications ) to 75m ( indoor applications ) . Further, the time resolution has to be better than 50ps , which corresponds to 15mm based on the speed of light . In addition, the readout data format is an issue , since a high number of bits is necessary to cover the various measuring ranges with a suf ficient resolution . Combined with the above-mentioned measuring rates the time for readout dominates the measuring time processing i f only one single data line is used . Flexible data processing requires interfaces to standard components like processors or field programmable gate arrays , FPGAs . While the flexibility of programable FPGAs enables control of nearly all flavors of interfaces at highest speed and enable fastest data processing, FPGAs are not the preferred choice because of device cost and additional ef fort in programming .

[0015] The proposed chip comprises an instruction driven communication interface that addresses said requirements . In particular, the communication interface comprises at least two bidirectional data pins for receiving and sending data, thereby increasing processing speed . Further, the communication interface may of fer the use of a system-on- chip, SoC, processor with direct memory access , DMA. SoC processors of fer high data processing with a multicore approach, flexible programming, and attractive price , while DMA allows certain hardware subsystems to access main system memory independently of the central processing unit , CPU . Thus , by means of the communication interface a fast data trans fer from the lidar TDC circuit chip to a processor can be provided . The availability of measurement data may be signaled to the SoC processor, for example , by an interrupt signal that is provided on a dedicated interrupt pin of the chip or via the communication interface . Thus , the response time of the chip can be reduced . Further, since the chip is reali zed by standard CMOS processes , the fabrication costs can be low .

[0016] According to at least one embodiment , the communication interface of the chip is based on a dual , quadruple , or octal serial peripheral interface , SPI . In case of a dual SPI , the communication interface may comprise two bidirectional data pins . In case of a quadruple SPI , the communication interface may comprise four bidirectional data pins . In case of an octal SPI , the communication interface may comprise eight bidirectional data pins . The more data pins , the faster the data transmission can be reali zed . Further, the SPI interface is a fast multiwire interface that is compatible to modern SoC processors . The SPI interface can be operated with opcode to control read and write access . In particular, the SPI interface is suited for an adapted read protocol .

[0017] According to at least one embodiment , the communication interface is configured to be controlled using a direct memory access , DMA, protocol . In an example , the chip comprises two stop channels with a respective hit buf fer si ze of two hit events to be stored . While two pulses may occur on the second stop channel , only one pulse may occur on the first stop channel . A processor may read, by one read access using DMA, the maximum possible measurement results , wherein not occurred stop signals ( in this example a second pulse on the first stop channel ) are marked with an error marker . In this example , a possible readout sequence and data structure may be the following :

[0018] - LOOP : Wait for Interrupt

[0019] - Write Opcode and Address CSN=0 + OPC_READ +3Adress-Bytes

[0020] - Read TOF of pulse#l of STOP1 +3Bytes

[0021] - Read Width of pulse#l of STOP1 +3Bytes

[0022] - Read dummy bytes +3Bytes of OxFFFFFF

[0023] - Read dummy bytes +3Bytes of OxFFFFFF

[0024] - Read TOF of pulse#l of STOP +3Byte

[0025] - Read Width of pulse#l of STOP2 +3Bytes

[0026] - Read TOF of pulse#2 of STOP2 +3Bytes Read Width of pulse#2 of STOP2 +3Bytes +CSN=1

[0027] It can be seen that all respective time differences of a measurement cycle are read in a single read access of the processor or DMA controller, respectively. In addition, a pulse width of the stop signals may be read. Further, an error marker (in this case OxFFFFFF) can be used to mark not occurred stop signals, i.e. if the number of hit events to be stored is larger than the actual detected hit events.

[0028] Thus, according to at least one embodiment, the communication interface is configured to be used for reading out all respective time differences and / or pulse widths of a measurement cycle by a single read access of a DMA controller. Further, readout of the data may be performed without interbyte gaps.

[0029] According to at least one embodiment, the at least one stop channel comprises a first stop channel with an input for a first stop signal and a second stop channel with an input for a second stop signal. For example, the first stop channel and the second stop channel form different measuring channels. For example, the first stop signal is generated by a different detector than the second stop signal. For example, the first stop signal is a reference signal, while the second stop signal is an actual measurement signal that originates from a laser pulse reflected by a scene. More than one second stop signal can be provided to the input of the second stop channel at different times of a measurement cycle. The plurality of second stop signals may come from a laser pulse that is reflected by different objects at different distances . According to at least one embodiment , the chip further comprises an edge detector for each stop channel coupled between the respective input and TDC elements . The edge detector is configured to di f ferentiate between a rising and a falling edge of the respective stop signal , wherein the calculation unit is further configured to determine a pulse width based on the rising and falling edge . The edge detector may be configured to distribute each rising a falling edge of respective stop signals to dedicated channels . For a given 180nm CMOS process two channels for separate measurement of the rising and falling edge might be necessary . However, it is also possible that the rising and falling edge is measured on one channel . By measurement of the rising and the falling edge the pulse width of the respective stop signal can be determined . Thus , it is possible to di f ferentiate between reflections from the associated laser source and unwanted reflections from other light sources . For example , the pulse width of the associated laser source is about 20ns , which is mainly given by the requirement of eye safety . The calculation unit may be configured to sort out hit events which are shorter or longer in terms of the pulse width . The calculation unit may be configured to determine the pulse width with a resolution of 2ns .

[0030] According to at least one embodiment , the chip further comprises a hit buf fer for each TDC element of the at least one stop channel , the hit buf fer being coupled between the respective TDC element and the calculation unit and being configured to store at least one , at least two , at least four, or at least eight signal measurements associated with respective stop signals . In other words , one , two , three , four, five , six, seven or eight signal measurements or hit events , respectively, can be stored in each hit buf fer . Thus , a high number of hit events can be detected, stored, and evaluated .

[0031] According to at least one embodiment, the number of stored signal measurements is separately adjustable for each hit buffer. This can mean, for example, that a hit buffer associated with the first stop channel is configured to store only one hit event. Further stop signals on the first stop channel are ignored and corresponding hit events are not stored. A hit buffer associated with the second stop channel, on the other side, can be configured to store eight hit events, for example. Thus, the number of signal measurements / hit events to be stored may be different for at least two hit buffers. In the above example, in which the first stop signal is a reference signal, the storage of only one hit event is sufficient .

[0032] According to at least one embodiment, the hit buffer is configured to store an error marker if no stop signal is provided. This can mean that, if the hit buffer size is configured to store a specific number of hit events but the number of actually detected hit events is smaller, an error marker is stored instead. By reading the error marker a processor is informed that a stop signal has not occurred.

[0033] According to at least one embodiment, the chip further comprises a clock channel comprising an input for a reference clock signal. For example, the reference clock signal is provided by a connected quartz. A quartz crystal offers stability and accuracy in generating clock signals. When used as a reference for an integrated circuit IC, it contributes to minimizing timing errors and maintaining synchronization within the system. The reference clock signal can be temperature stabili zed . The clock channel may further comprise a TDC element that converts the reference clock signal into a digital signal . The digitali zed reference clock signal may serve as time measure for calculation of the time di f ference associated with the start signal and the stop signal .

[0034] According to at least one embodiment , the calculation unit is further configured to calibrate the determined time di f ference to fractions of the reference clock . For example , the reference clock signal has a defined frequency . The clock channel may sample a first time stamp of a first rising edge of the reference clock signal , and may further sample a second time stamp of a second rising edge of the reference clock signal . A time di f ference of the first and the second time stamp reflects a calibration value used to calibrate the determined time di f ference of the start and stop signals in fractions of the reference clock signal . Calibration may be performed continuously and in parallel to the regular start and stop signal measurements . The calculation unit may calibrate the determined time di f ference in configurable fractions of the reference clock signal , for example in Ips or l Ops steps . Time stamps of hit events on all TDC channels are sampled with an internal resolution of the TDC ring oscillator, which however is sensitive to variations , for example in temperature . By using the calibration, a reference is provided to calibrate the internal TDC resolution with the ( external ) reference clock signal , which is less prone to variations . As mentioned above , a reference clock signal provided by a quartz crystal is more temperature-stable . Thus , calculation of the time di f ference can be more accurate . According to at least one embodiment , the chip further comprises a trigger unit configured to provide a trigger signal with spread spectrum clock for the generation of a laser pulse . The trigger unit may comprise an output where the trigger signal is provided . The output of the trigger unit forms an output of the chip, and the trigger signal can be provided to an external laser device not forming part of the chip . Usually, each system of repetitive measurements is confronted with interference ef fects from other sources operating with the same frequency . By using a trigger signal with spread spectrum clock, i . e . with phase noise , interference with other light sources can be suppressed .

[0035] According to at least one embodiment , the chip further comprises a stop mask unit configured to suppress noise at the at least one stop channel by introducing a measurement delay . The measurement delay is configurable externally and provided to an input of the stop mask unit . In addition or alternatively, the measurement delay is configurable on chip by means of a tapped ring oscillator, a delay-locked loop, DLL, or a phase-locked loop, DLL . In other words , after the start signal is provided, the stop mask unit defines a time window in which stop signals are ignored . This time window may be referred to as noise mask window and defines the measurement delay . This can mean that measurements of reflections from obj ects nearby are suppressed . This also avoids overflow of the hit buf fers . Thus , applying the measurement delay is a suitable measure for outdoor and indoor applications . The length of the noise mask window can be configured in the nanosecond range . For example , the noise mask window can be configured in steps of Ins , corresponding to 300mm based on the speed of light ( or 150mm in a reflective setup as light travels forth and back) . This time interval can be configured by means of a tapped ring oscillator, a DLL, or a DLL that are arranged on chip . It is also possible that a stop mask signal defining the noise mask window, i . e . the measurement delay, is generated externally and provided to an input of the stop mask unit . The input of the stop mask unit may form an input pin of the chip .

[0036] Further, a time-of- f light , ToF, measurement system is provided . The ToF measurement system comprises the CMOS integrated chip as described above . This means that all features disclosed for the CMOS integrated chip are also disclosed for the ToF measurement system and vice versa .

[0037] According to at least one embodiment , the ToF measurement system further comprises a laser device configured to emit a laser pulse towards a scene . For example , the laser device is or comprises a pulsed laser diode . The laser device may be configured to receive a trigger signal form an external microcontroller or from the trigger unit on chip . The trigger signal may trigger the generation of the laser pulse . Light from the laser pulse may be directed, for example via optics of the ToF measurement system, towards the scene , where the laser light is reflected by an obj ect .

[0038] According to at least one embodiment , the ToF measurement system comprises a receiver configured to detect the laser pulse after reflection from the scene . The receiver can be or comprise an avalanche photo diode , APD, for example . The receiver generates a detection signal upon sensing the laser pulse . Said detection signal or a derivative of the detection signal may form the stop signal or one of the stop signals . According to at least one embodiment , the start signal is provided to the input of the start channel when the laser pulse is emitted . Thus , the start signal and the emission of the laser pulse are synchroni zed . By means of the start signal the chip is provided with the information that a laser pulse is emitted and stores a timestamp of the start signal .

[0039] According to at least one embodiment , the stop signal is provided to the input of the at least one stop channel when the reflected laser pulse is detected . By means of the stop signal the chip is provided with the information that the originally emitted laser pulse was reflected by an obj ect and hit the receiver . The chip can store a timestamp of the stop signal and calculate a time di f ference between the start signal and the stop signal , wherein the time di f ference indicates the distance of the obj ect to the ToF measurement system . In addition or alternatively, the emitted light pulse is detected via a separate measurement channel that provides the first stop signal . Said first stop signal can be used as reference and a time di f ference is calculated between the first stop signal and possible further stop signals .

[0040] Further, a method of operating a CMOS integrated chip is provided . The method is preferably carried out using the CMOS integrated chip as described above . This means that all features disclosed for the CMOS integrated chip are also disclosed for the method of operating the CMOS integrated chip, and vice versa .

[0041] According to at least one embodiment , the method comprises providing a start signal to the input of the start channel . According to at least one embodiment , the method further comprises providing a stop signal to the input of the at least one stop channel. According to at least one embodiment, the method further comprises storing, by the TDC elements, respective counts when triggered by the start signal or the stop signal, respectively. According to at least one embodiment, the method further comprises determining, by the calculation unit, a time difference associated with the start signal and the stop signal based on the counts. According to at least one embodiment, the method further comprises reading the time difference via the data pins of the communication interface .

[0042] The described method has the same advantages as the CMOS integrated chip. In particular, the transfer of measurement data via the communication interface can be fast, since a fast multiwire interface is provided that is compatible to modern SoC processors.

[0043] According to at least one embodiment, the method further comprises reading all respective time differences of a measurement cycle by a single read access of a DMA controller. The method may utilize an adapted read protocol, wherein the time-of-f light data as well as the pulse widths of all measurement signals are read in a single read access. Reading of the data may be performed without interbyte gaps.

[0044] According to at least one embodiment of the method, an error marker is stored and read if no stop signal is provided. This can mean that, if the hit buffer size is configured to store a specific number of hit events but the number of actually detected hit events is smaller, an error marker is stored instead. By reading the error marker a processor is informed that a stop signal has not occurred. The following description of Figures may further illustrate and explain aspects of the CMOS integrated chip comprising the TDC circuit , the ToF measurement system, and the method of operating the CMOS integrated chip . Components and parts of the CMOS integrated chip that are functionally identical or have an identical ef fect are denoted by identical reference symbols . Identical or ef fectively identical components and parts might be described only with respect to the Figures where they occur first . Their description is not necessarily repeated in successive Figures .

[0045] Figure 1A shows a CMOS integrated chip comprising a time-to- digital converter circuit according to an embodiment .

[0046] Figure IB shows an implementation detail of the CMOS integrated chip according to Figure 1A.

[0047] Figure 2 shows a transaction of a communication interface .

[0048] Figures 3 and 4 show signal timing diagrams of a time-to- digital converter circuit during operation .

[0049] Figure 5 shows a time-to-digital converter circuit according to an embodiment .

[0050] Figure 6 shows a time-of- f light measurement system according to an embodiment .

[0051] Figure 7 schematically shows a method of operating a CMOS integrated chip comprising a time-to-digital converter circuit according to an embodiment .

[0052] In Figure 1A a CMOS integrated chip 1 comprising a time-to- digital converter, TDC, circuit 2 is shown. The CMOS integrated chip 1 with the TDC circuit 2 can in particular be used for light detection and ranging, lidar, applications.

[0053] The CMOS integrated chip 1, called "chip" in the following, comprises a start channel 10 comprising an input 11 for a start signal. The input 11 is implemented as low-voltage differential signaling, LVDS, interface, wherein an LVDS receiver 12 is provided with a positive and a negative start signal from respective input pins 11, 11' .

[0054] The chip 1 further comprises at least one stop channel 20, 30 comprising an input 21, 31 for a stop signal. In the shown example, the chip 1 comprises a first stop channel 20 with an input 21 for a first stop signal and a second stop channel 30 with an input 31 for a second stop signal. The respective inputs 21, 31 are implemented as LVDS interfaces, wherein a respective LVDS receiver 22, 32 is provided with a positive and a negative stop signal from respective input pins 21, 21' or 31, 31' , respectively.

[0055] The chip 1 further comprises a TDC element 40 for each of the start 10 and stop channels 20, 30, wherein the TDC element 40 is configured to store respective counts when triggered by the start signal or the stop signal, respectively. Each TDC element 40 may be implemented as storage or sample-and-hold element that is coupled to a ring oscillator, as shown in Figure 5. In particular, each TDC element 40 may be coupled to the same ring oscillator. The ring oscillator is not shown in Figure 1A. The TDC elements 40 comprise a first 41, a second 42, a third 43, a fourth 44, a fifth 45, and a sixth TDC element 46. The first TDC element 41 is associated with the start channel 10 and electrically coupled to the input 11 (with the LVDS receiver 12 ) via an edge detector 13 . As indicated, the edge detector 13 may detect a rising edge of the start signal , for example .

[0056] The second 42 and the third TDC element 43 are associated with the first stop channel 20 and electrically coupled to the input 21 (with the LVDS receiver 22 ) via an edge detector

[0057] 23 . As indicated, the edge detector 23 di f ferentiates between a rising and a falling edge of the first stop signal . The second TDC element 42 is coupled at its input side to an output of the edge detector 23 that is associated with the detection of the rising edge . The third TDC element 43 is coupled at its input side to an output of the edge detector 23 that is associated with the detection of the falling edge .

[0058] The fourth 44 and the fi fth TDC element 45 are associated with the second stop channel 30 and electrically coupled to the input 31 (with the LVDS receiver 32 ) via an edge detector 33 . As indicated, the edge detector 33 di f ferentiates between a rising and a falling edge of the second stop signal . The fourth TDC element 44 is coupled at its input side to an output of the edge detector 33 that is associated with the detection of the rising edge . The fi fth TDC element 45 is coupled at its input side to an output of the edge detector 33 that is associated with the detection of the falling edge .

[0059] The respective edge detectors 23 , 33 of the stop channels 20 , 30 may be coupled to their respective inputs 21 , 31 via a switch 24 , 34 , as shown in Figure 1A. For example , the switch

[0060] 24 , 34 is coupled to a stop mask unit 100 and / or to an input 101 of the stop mask unit 100 and configured to receive a stop mask signal. Based on the state of the stop mask signal the respective stop signals are transmitted to the edge detectors 23, 33, or not. For example, if the stop mask signal is high, this indicates that a noise mask window is active, such that respective stop signals at the inputs 21, 31 of the stop channels 20, 30 are not counted. The noise mask window may define a time interval directly after providing the start signal. During the noise mask window noise at the inputs 21, 31 of the stop channels 20, 30 is suppressed .

[0061] Further, the edge detectors 23, 33 may be coupled to each other via a switchable interconnection 25, as shown in Figure 1A. Thus, a further operation mode is possible: Stop signals on input 21 of the first stop channel 20 are measured alternating by the TDC elements 42, 43 and the TDC elements 44, 45. For example, a first pulse on input 21 is differentiated in rising and falling edge by the edge detector 23. A second pulse on input 21 is differentiated in rising and falling edge by edge detector 33. In this case, the second stop channel 30 may not be used. In this operation mode not only the measurable pulse width is minimal, but also the pulse-to-pulse distance is minimal.

[0062] In the shown example, each TDC element 40 is coupled to a hit buffer 70, wherein the hit buffers 70 may be configured to store up to eight TDC counts or stop signal measurements, respectively. The hit buffers 70 comprise a start hit buffer 71 that is coupled to the first TDC element 41. Further, the hit buffers 70 comprise a first 72, a second 73, a third 74 and a fourth stop hit buffer 75 that are respectively coupled to the TDC elements 42 to 45 of the stop channels 20, 30. In other words, the chip 1 may comprise a stop hit buffer 72-75 for each TDC element 42-45 of the at least one stop channel 20, 30.

[0063] The chip 1 further comprises a calculation unit 50 coupled to each TDC element 40 and configured to determine a time difference associated with the start signal and the stop signal based on the counts. In the shown example, the calculation unit 50 is coupled to the TDC elements 40 via the respective hit buffers 70.

[0064] In the start hit buffer 71 data that is associated with a point in time at which the start signal occurred is saved. That data is provided by the first TDC element 41 and may correspond to a state of the ring oscillator. In the hit buffers 72-75 data that is associated with one or more points in time at which respective stop signals occurred is saved. That data is provided by the respective TDC elements 42-45 and may correspond to further states of the ring oscillator. Each hit buffer 72-75 may be configured to store at least one, at least two, at least four, or at least eight signal measurements associated with respective stop signals. The number of stored signal measurements may be separately adjustable for each hit buffer. For example, the first 72 and the second hit buffers 73 may be configured to store only one signal measurement, while the third 74 and the fourth hit buffer 75 are configured to store two, three, four, five, six, seven or eight signal measurements. In some hit buffers, in particular in the hit buffers 72 and 74, time points of respective rising edges are saved, while in other hit buffers, in particular in hit buffers 73 and 75, time points of respective falling edges are saved. The calculation unit 50 determines a time difference associated with the start signal and one of the stop signals based on the data saved in the buffers 70. The calculation unit 50 may determine the time difference between all occurred stop signals and the start signal. In addition, the calculation unit 50 may be configured to determine a pulse width of the stop signals based on the time points of the rising edge and the falling edge of the respective stop signal.

[0065] The chip 1 further comprises an instruction driven communication interface 60 comprising at least two bidirectional data pins 63, 64. In the shown example, the communication interface 60 comprises four bidirectional data pins 63-66. It further comprises a select pin 61 and a clock pin 62. Thus, the shown communication interface 60 can be a quad serial peripheral interface, QSPI, for example. It is however also possible that the communication interface is based on a dual or octal serial peripheral interface, SPI . The communication interface 60 is coupled to the calculation unit 50. Thus, it is possible to read out, via the communication interface 60, the time differences and pulse widths determined by the calculation unit 50 after a respective read instruction. For example, the communication interface 60 is configured to be controlled using a direct memory access, DMA, protocol. For example, all respective time differences of a measurement cycle can be read by a single read access of a DMA controller.

[0066] The chip 1 shown in Figure 1A further comprises a configuration unit 69. For example, the configuration unit is configured to receive configuration data via the communication interface 60. The configuration unit 69 may configure the chip 1, for example in terms of hit buffer size, measurement range or the like. The chip 1 shown in Figure 1A further comprises a clock channel 80 comprising an input 81 for a reference clock signal . In particular, the clock channel 80 may comprise an input 81 for a quartz-oscillator as reference clock as well as an output 81 ' for the quartz-oscillator as reference clock . The clock channel 80 further comprises the sixth TDC element 46 that is coupled to the input 81 and configured to convert the clock signal into a digital signal for the measurement of its period . The sixth TDC element 46 is coupled to all hit buf fers 70 , i . e . to the start hit buf fer 71 and the hit buf fers 72-75 . In this way, the calculation unit may be further configured to calibrate the determined time di f ference to fractions of the reference clock .

[0067] As indicated in Figure 1A, the chip 1 optionally further comprises a trigger unit 90 configured to provide a trigger signal with spread spectrum clock for the generation of a laser pulse . The trigger unit 90 comprises an output 91 where the trigger signal is provided . For example , a laser device that is connected to the output 91 can be configured to emit a laser pulse i f provided with the trigger signal .

[0068] Further, the chip 1 may comprise a stop mask unit 100 configured to suppress noise at the at least one stop channel 20 , 30 by introducing a measurement delay . This can mean that the measurement is enabled internally after a delay . For example , the measurement delay is configurable externally and provided to an input 101 of the stop mask unit 100 . It is also possible that the measurement delay is configurable on chip by means of a tapped ring oscillator, a delay-locked loop, or a phase-locked loop (not shown in Figure 1A) . In this case , the delay may be started by a pulse on the input 11 of the start channel 10 . The measurement delay can be transmitted via a stop mask signal to the respective stop channels 20, 30, for example by controlling the switches 24, 34, as mentioned above.

[0069] Further, the chip 1 may comprise a voltage control unit 110 with respective inputs and outputs 111, 111' . As shown in Figure 1A, the chip 1 may comprise further pins. For example, the chip comprises supply terminals 120-124 for different supply voltages. The supply terminals 120-124 can be separated in terms of supply voltages for analog and digital circuit parts. The chip 1 may further comprise ground (GND) terminals 130-133, which can also be separated for analog and digital circuit parts.

[0070] The chip 1 may further comprise an interrupt terminal 150 at which an interrupt signal can be provided. The interrupt terminal 150 forms an output pin of the chip 1. The interrupt terminal 150 is coupled to a timeout unit 151. The timeout unit 151 may be configured to force interruption / timeout of the measurement cycle, for example if not enough stop hit events (measurement signals) were captured. In other words, the timeout unit 151 may be implemented as internal configurable counter, which sets the maximal measuring time. The timeout may indicate that the measurement is finished by setting the interrupt signal to a low state. The low state may indicate to a receiving device (e.g. a microprocessor) that data is available to be read out by the communication interface 60. The interrupt signal goes back to a high state when all data are read out and all hit buffers 70 are empty.

[0071] Moreover, the chip 1 may comprise an initialization terminal 140 for providing an initialization signal. Thus, (re-) initialization of the TDC circuit for subsequent measurements can be carried out. For example, (re-) initialization is carried out when all data were read out from the hit buffers 72-75 and / or when the interrupt signal went back to a high state. Alternatively, (re-) initialization is carried out when a respective instruction is provided via the communication interface. Such instruction may be provided independently from the hit buffer filling states and even during an active measuring sequence. Alternatively, (re-) initialization is triggered by providing the initialization signal via the initialization terminal 140. By (re-) initialization the TDC elements 40, the edge detectors 13, 23, 33 and the hit buffers 70 can be set into a reset state. This guarantees that any failed hit or state does not disturb or suppress subsequent measurements. The initialization signal may be asynchronous to the reference clock signal, the start signal and / or the stop signal.

[0072] All of the above-mentioned circuit components may be part of the TDC circuit 2. However, at least some of the above- mentioned circuit components, for example the communication interface 60, the trigger unit 90 and the voltage control unit 110, can also be part of additional circuitry on the CMOS integrated chip 1.

[0073] In Figure IB a detail of an implementation of the CMOS integrated chip 1 is shown. It shows that the edge detectors 23, 33 of the output channels 20, 30 form separate edge detectors for detecting a rising edge and a falling edge, respectively. One TDC element 43, 45 is coupled to a respective edge detector for a rising edge, while another TDC element 42, 44 is coupled to a respective edge detector for a falling edge. The respective edge detectors can be coupled to each other, as shown in Figure IB. With this implementation the pulse width is minimal , as the rising and falling edge are processed in di f ferent TDC channels . Thus , the minimal pulse width is much shorter than the processing time of one hit in TDC channel .

[0074] In Figure 2 a transaction of the communication interface 60 is shown . In particular, the transaction can be a quad serial peripheral interface , QSPI , transaction . In the first line a clock signal is shown . Instead of using a single output and single input interface , QSPI , uses four separate bidirectional data lines S 0-S3 for both transmitting and receiving data . For example , the shown transaction is a read transaction . A read command is sent in a command phase CP on the first line S O while all others are on hold . Next , in an address phase AP, the host sends the address ; the address can be sent on all four data lines S 0-S3 , so that the full address can be transmitted in only eight clock cycles . Then, two dummy bytes in four clock cycles follow in a dummy phase MP to allow the device additional time to set up the initial address . Then, the device sends data bytes in a data phase DP on all four data lines S 0-S3 . The communication protocol is suited for using a system-on-chip, SoC, processor with direct memory access , DMA. Advantageously, with such an adapted read protocol fast processor handling without interbyte gaps is possible .

[0075] In Figure 3 a possible signal timing of a time-to-digital converter circuit 2 is shown . It shows a start signal ST , a stop mask signal SMS , and a stop signal SP . When the start signal ST goes high, this indicates the start of the measurement . However, as long as the stop mask signal SMS is low, a noise mask window NMW is defined, at which possible stop signals ( in the shown example the stop signal SPO ) are not counted (it should be noted that the stop mask signal SMS may be implemented differently, in particular inversely: the stop mask signal SMS may go high to suppress stops) . Only stop signals that are detected during a measurement window MW are valid, such as the stop signals SP1, SP2 and SP3. The measurement window MW is defined by the time interval in which the stop mask signal SMS is high and timeout TO. The time at which timeout TO occurs can be determined by the maximal measurement range in time units, e.g. 4ps for far range applications, and can be configurable in steps of the reference clock, e.g. 100ns. By this time, the hit buffers 72-75 might not be filled. Possible stop signals that are detected after timeout TO, e.g. stop signal SP4, are not valid signal measurements and are not counted.

[0076] In Figure 4 another possible signal timing is shown. Compared to Figure 3 it additionally shows a (re-) initialization signal RE-INIT, an interface signal SPI, and an interrupt signal INT . The RE-INIT signal may be triggered via an opcode sent via the communication interface 60 and may be configured to (re-) initialize the TDC circuit 2 after configuration. The TDC circuit 2 will be active and consume current. Further, the TDC circuit 2 is then waiting for a start event. The start signal ST represents the first hit which occurred on the input 11 of the start channel 10. Further hits on said input 11 are ignored during this cycle. As mentioned above, the stop mask signal SMS is configured to suppress noise on the inputs 21, 31 of the stop channels 20, 30. The stop mask signal SMS is either defined by the input 101 of the stop mask unit 100 or by internal configuration of the noise mask window NMW and timeout TO. As long as the stop mask signal

[0077] SMS is low, hits on the stop channel inputs 21, 31 are ignored and are not measured by the TDC circuit 2. The stop signals SP may be signals on the input 21 of the first stop channel 20 or on the input 31 of the second stop channel 30 . Respective time di f ferences AT can be calculated based on the times at which the start signal ST and the respective stop signals SP are detected . Timeout TO marks the end of accepting valid stop signals SP in the measurement window MW . It may be an internally configurable counter, which sets the maximal measuring time and indicates that the measurement is ready for readout by setting the interrupt signal INT to low . Further, the interrupt signal INT may be set to low when the last accepted stop signal has filled the configured hit buf fer space . In case that the hit buf fer space was not filled at the end of the measurement window MW, the interrupt signal INT will be set low at the end of the measurement window MW and may stay low until the last measurement is read out from the hit buf fers 72-75 . The interface signal SPI triggers the readout period RD . By a further initiali zation signal RE- INIT , the TDC circuit 2 is initiali zed for the next measurement cycle .

[0078] In Figure 5 an exemplary time-to-digital converter circuit 2 is shown . The shown TDC circuit 2 can be integrated in the chip 1 of Figure 1A. However, other circuit designs are also possible . The TDC circuit 2 of Figure 5 comprises a plurality of TDC elements 40 , which can be implemented as sample-and- hold registers . For example , the TDC elements 40 are reali zed as flip- flops . The TDC circuit 2 further comprises a ring oscillator 47 . An output 38 of the ring oscillator 47 is connected to respective inputs 39 of the TDC elements 40 , thus forming a signal bus for each signal at output 38 to the TDC elements 40 . The TDC elements 40 each comprise a further input 36 that is connected to the respective edge detectors 13 , 23 , 33 as shown in Figure 1A. An output of the TDC elements 40 is connected to the hit buf fers 70 . The ring oscillator 47 comprises a plurality of inverters 48 that are arranged in series . The output 38 of the ring oscillator 47 is electrically connected to each of the inverter outputs . The ring oscillator 47 further comprises an input 37 that is the input of a NAND-gate arranged before the inverters 48 .

[0079] The ring oscillator 47 further comprises a counter 49 between a further input of the NAND-gate and the output 38 . The output of the NAND-gate and the further input of the NAND- gate are also connected to the output 38 of the ring oscillator 47 . The shown TDC circuit 2 comprises three TDC elements 40 and three inverters 48 . However, more than three TDC elements 40 and inverters 48 are also possible . In particular, the TDC circuit 2 can comprise six TDC elements 40 corresponding to Figure 1A.

[0080] In Figure 6 a time-of- f light , ToF, measurement system is shown . The ToF measurement system comprises the CMOS integrated chip 1 . It further comprises a laser device 180 configured to emit a laser pulse towards a scene . It further comprises a receiver 210 configured to detect the laser pulse after reflection from the scene . The start signal ST is provided to the input 11 of the start channel 10 when the laser pulse is emitted . The stop signal SP is provided to the input 21 , 31 of the at least one stop channel , 20 , 30 when the reflected laser pulse is detected .

[0081] The ToF measurement system may further comprises a microcontroller 170 for providing a trigger signal to an ampli fier 160 , which in turn provides an ampli fied signal to the laser device 180 for the generation of the laser pulse .

[0082] However, the chip 1 may comprise its own trigger unit 90 for the generation of the trigger signal . I f the trigger signal is generated by the microcontroller 170 , a simultaneous start signal ST may be transmitted from the microcontroller 170 to the input 11 of the chip 1 .

[0083] The laser pulse may propagate to a beam splitter 190 of the ToF measurement system . Part of the laser light is directed to an obj ect 300 within the scene via optics 200 of the ToF measurement system . At the obj ect 300 the laser light is reflected and propagates back to the optics 200 or another optical element of the ToF measurement system . Then, it hits the receiver 210 . After detection by the receiver 210 , the receiver transmits a detection signal to a further ampli fier 160 , which in turn provides a respective ampli fied signal to one of the inputs 21 , 31 of the stop channels 20 , 30 . Said respective ampli fied signal can be the stop signal SP that is provided at the input 31 of the second stop channel 30 . Another part of the laser light may be directed from the beam splitter 190 to a detector 220 , which in turn may provide a further stop signal SP' to the input 21 of the first stop channel 20 . By means of the further stop signal SP' signal delays can be considered . For example , delays occur between the generation of the trigger signal and the emission of the laser pulse . Thus , the further stop signal SP' may serve as alternative start signal for the calculation of respective time di f ferences AT .

[0084] In Figure 7 a method of operating the CMOS integrated chip 1 comprising the time-to-digital converter circuit 2 is shown schematically . In a first step 701 , a start signal ST is provided to the input 11 of the start channel 10 (before step 701 the chip may be ( re- ) initiali zed by providing an initiali zation signal ) . In a second step 702 , a stop signal SP is provided to the input 21 , 31 of the at least one stop channel 20, 30. In a third step 703 respective counts are stored, by the TDC elements 40, when triggered by the start signal ST or the stop signal SP, respectively. In fourth step 704 a time difference AT associated with the start signal ST and the stop signal SP is determined, by the calculation unit 50, based on the counts.

[0085] In a fifth step 705, the time difference AT is read via the data pins of the communication interface 60. As mentioned above, all respective time differences AT of a measurement cycle can be read by a single read access of a DMA controller. Further, if no stop signal SP is provided (e.g. because the laser pulse is not reflected by an object) an error marker can be stored in the hit buffer 72-75 or the calculation unit 50 and read.

[0086] The embodiments of the CMOS integrated chip 1, the ToF measurement system, and the method of operating the chip 1 disclosed herein have been discussed for the purpose of familiarizing the reader with novel aspects of the idea. Although preferred embodiments have been shown and described, many changes, modifications, equivalents, and substitutions of the disclosed concepts may be made by one having skill in the art without unnecessarily departing from the scope of the claims .

[0087] It will be appreciated that the disclosure is not limited to the disclosed embodiments and to what has been particularly shown and described hereinabove. Rather, features recited in separate dependent claims or in the description may advantageously be combined. Furthermore, the scope of the disclosure includes those variations and modifications, which will be apparent to those skilled in the art and fall within the scope of the appended claims. The term "comprising", insofar it was used in the claims or in the description, does not exclude other elements or steps of a corresponding feature or procedure. In case that the terms "a" or "an" were used in conjunction with features, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope. This patent application claims the priority of German patent application 102023134962.7, the disclosure content of which is hereby incorporated by reference.

[0088] Reference numerals

[0089] 1 chip

[0090] 2 time-to-digital converter circuit

[0091] 10 start channel

[0092] 11 input of start channel

[0093] 12 LVDS receiver of start channel

[0094] 13 edge detector of start channel

[0095] 20 first stop channel

[0096] 21 input of first stop channel

[0097] 22 LVDS receiver of first stop channel

[0098] 23 edge detector of fist stop channel

[0099] 24 switch

[0100] 25 switchable interconnection

[0101] 30 second stop channel

[0102] 31 input of second stop channel

[0103] 32 LVDS receiver of second stop channel

[0104] 33 edge detector of second stop channel

[0105] 34 switch

[0106] 36 first input of TDC element

[0107] 37 input of ring oscillator

[0108] 38 output of ring oscillator

[0109] 39 second input of TDC element

[0110] 40-46 TDC element

[0111] 47 ring oscillator

[0112] 48 inverter

[0113] 49 counter

[0114] 50 calculation unit

[0115] 60 communication interface

[0116] 61 select pin

[0117] 62 clock pin

[0118] 63- 66 data pin

[0119] 69 configuration unit 70 hit buf fer

[0120] 71 start hit buf fer

[0121] 72-75 hit buf fer

[0122] 80 clock channel

[0123] 81 input of clock channel

[0124] 90 trigger unit

[0125] 91 output of trigger unit

[0126] 100 stop mask unit

[0127] 101 input of stop mask unit

[0128] 110 voltage control unit

[0129] 111 output of voltage control unit

[0130] 120- 124 supply terminal

[0131] 130- 133 ground terminal

[0132] 140 initiali zation terminal

[0133] 150 interrupt terminal

[0134] 151 timeout unit

[0135] 160 amp 1 i f i e r

[0136] 170 microcontroller

[0137] 180 laser

[0138] 190 beam splitter

[0139] 200 optics

[0140] 210 receiver

[0141] 220 detector

[0142] 300 obj ect

[0143] 701-705 step

[0144] AP address phase

[0145] CP command phase elk clock signal

[0146] DP data phase

[0147] INT interrupt signal

[0148] MP dummy phase

[0149] MW measurement window

[0150] NMW noise mask window RD readout period

[0151] RE-INIT reinitialization signal

[0152] SMS stop mask signal

[0153] SP stop signal

[0154] SPI interface signal

[0155] SP0-SP4 stop signal

[0156] ST start signal

[0157] S0-S3 data signal

[0158] TO timeout

[0159] AT time difference

Claims

Claims1. CMOS integrated chip (1) comprising a time-to-digital converter, TDC, circuit (2) for light detection and ranging, lidar, applications, comprising:— a start channel (10) comprising an input (11) for a start signal (ST) ,— at least one stop channel (20, 30) comprising an input (21, 31) for a stop signal (SP) ,— a TDC element (40) for each of the start (10) and stop channels (20, 30) , wherein the TDC element (40) is configured to store respective counts when triggered by the start signal (ST) or the stop signal (SP) , respectively,— a calculation unit (50) coupled to each TDC element (40) and configured to determine a time difference (AT) associated with the start signal (ST) and the stop signal (SP) based on the counts, and— an instruction driven communication interface (60) comprising at least two bidirectional data pins (63, 64) .

2. CMOS integrated chip (1) according to the preceding claim, wherein the communication interface (60) is based on a dual, quadruple, or octal serial peripheral interface, SPI .

3. CMOS integrated chip (1) according to one of the preceding claims, wherein the communication interface(60) is configured to be controlled using a direct memory access, DMA, protocol.

4. CMOS integrated chip (1) according to one of the preceding claims, wherein the at least one stop channel (20, 30) comprises a first stop channel (20) with an input (21) for a first stop signal (SP' ) and a second stop channel (30) with an input (31) for a second stop signal (SP) .

5. CMOS integrated chip (1) according to one of the preceding claims, further comprising an edge detector (23, 33) for each stop channel (20, 30) coupled between the respective input (21, 31) and TDC elements (40) , the edge detector (23, 33) differentiating between a rising and a falling edge of the respective stop signal (SP) , wherein the calculation unit (50) is further configured to determine a pulse width based on the rising and falling edge.

6. CMOS integrated chip (1) according to one of the preceding claims, further comprising a hit buffer (72, 73, 74, 75) for each TDC element (40) of the at least one stop channel (20, 30) , the hit buffer (72, 73, 74, 75) being coupled between the respective TDC element (40) and the calculation unit (50) and being configured to store at least one, at least two, at least four, or at least eight signal measurements associated with respective stop signals (SP) .

7. CMOS integrated chip (1) according to according to the preceding claim, wherein the number of stored signal measurements is separately adjustable for each hit buffer(72, 73, 74, 75) .

8. CMOS integrated chip (1) according to one of the preceding claims, further comprising a clock channel (80) comprising an input (81) for a reference clock signal.

9. CMOS integrated chip according to the preceding claim, wherein the calculation unit (50) is further configured to calibrate the determined time difference (AT) to fractions of the reference clock.

10. CMOS integrated chip according to one of the preceding claims, further comprising a trigger unit (90) configured to provide a trigger signal with spread spectrum clock for the generation of a laser pulse.

11. CMOS integrated chip according to one of the preceding claims, further comprising a stop mask unit (100) configured to suppress noise at the at least one stop channel (20, 30) by introducing a measurement delay, wherein the measurement delay is configurable externally and provided to an input (101) of the stop mask unit (100) , or configurable on chip by means of a tapped ring oscillator, a delay-locked loop, DLL, or a phase-locked loop, DLL.

12. Time-of-f light , ToF, measurement system, comprising:— the CMOS integrated chip (1) according to one of the preceding claims,— a laser device (180) configured to emit a laser pulse towards a scene,— a receiver (210) configured to detect the laser pulse after reflection from the scene, wherein— the start signal (ST) is provided to the input (11) of the start channel (10) when the laser pulse is emitted, and— the stop signal (SP) is provided to the input (21, 31) of the at least one stop channel (20, 30) when the reflected laser pulse is detected.

13. Method of operating the CMOS integrated chip (10) according to one of claims 1 to 11, the method comprising :— providing (701) a start signal (ST) to the input (11) of the start channel (10) ,— providing (702) a stop signal (SP) to the input (21, 31) of the at least one stop channel (20, 30) ,— storing (703) , by the TDC elements (40) , respective counts when triggered by the start signal (ST) or the stop signal (SP) , respectively,— determining (704) , by the calculation unit (50) , a time difference (AT) associated with the start signal (ST) and the stop signal (SP) based on the counts, and— reading (705) the time difference (AT) via the data pins (63, 64) of the communication interface (60) .

14. Method according to claim 13, further comprising reading all respective time differences (AT) of a measurement cycle by a single read access of a DMA controller.

15. Method according to claim 13 or 14, wherein an error marker is stored and read if no stop signal (SP) is provided .

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