9results about "Time-to-digital converters" patented technology

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

Phase-locked loop circuitry is provided that includes a time-to-digital converter, a first frequency divider circuit coupled to an output of the time-to-digital converter, and a second frequency divider circuit coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator with a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit. The phase interpolator can be calibrated using the time-to-digital converter.

Embodiments of a sampling system and a method for sampling are disclosed. In an embodiment, a sampling system includes a sampler array that includes sampling cells, a timing controller connected to the sampler array to form a closed loop and configured to correct a timing mismatch in the sampler array, and a time to digital converter (TDC) configured to perform indexing of the sampling cells in the sampler array.

A CMOS integrated chip (1) comprising a time-to-digital converter (TDC) circuit (2) for light detection and ranging (lidar) applications, the chip comprising a start channel (10) comprising an input (11) for a start signal (ST) and at least one stop channel (20, 30) comprising an input (21, 31) for a stop signal (SP). It further comprises a TDC element (40) for each of the start and stop channels (10, 20, 30), wherein the TDC element (40) is configured to store a respective count when triggered by the start signal (ST) or the stop signal (SP), respectively. It further comprises a computing unit (50) coupled to each TDC element (40) and configured to determine a time difference (AT) associated with the start signal (ST) and the stop signal (SP) based on said counts, and an instruction-driven communication interface (60) comprising at least two bidirectional data pins (63, 64). Furthermore, a time-of-flight measurement system and a method of operating a CMOS integrated chip (1) are provided.

The application discloses a device for reducing dead time in a time measurement system and relates to the technical field of time measurement. The device comprises a delay chain, a high-speed sampling clock module, an event acquisition module, a plurality of event recording modules, a low-speed processing clock module and an event combination module. The event acquisition module is used for periodically sampling and processing the delay chain at a high-speed sampling working frequency to obtain a data stream. The plurality of event recording modules are used for respectively and alternately recording the data stream from the event acquisition module. The event combination module is used for periodically and synchronously reading a plurality of data streams recorded in the plurality of event recording modules at a low-speed processing working frequency, and combining final time information according to the plurality of data streams. Thus, the low dead time purpose can be achieved, and the risk that the timing cannot meet the requirements in the FPGA layout and wiring can be reduced by means of processing resource exchange time.

A time to digital converter including multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different transition delays of each buffer. The buffers may be configured to be compatible with a standard cell layout. The buffers may be configured as standard cell logic gate with modified connections. The buffers may be calibrated by selecting a fastest delay value that does not cause overflow in response to a calibration pulse.

To provide a time to digital (TD) converter having low switching noise generated from an electric power source during a gating action so as to achieve excellent noise characteristics, and provide a phase locked loop (PLL) having the TD converter.SOLUTION: A TD converter 10 comprises a plurality of oscillators 400 comprising at least a first oscillator 400A and a second oscillator 400B which operate in different operation modes having different oscillatory frequencies depending on a control signal representing a time difference between a reference clock and an object clock; and an operation circuit 500 that calculates a digital output value depending on the time difference for each of the plurality of oscillators using one of a plurality of pieces of phase information held therein according to the reference clock. The first oscillator and the second oscillator are each operative in two operation modes, a high-speed operation mode and a low-speed operation mode having the oscillatory frequency lower than that of the high-speed operation mode.SELECTED DRAWING: Figure 18

A system includes a first device coupled with a link which transmits a signal having a repeating pattern, and a second device coupled with the link. The second device is to receive the signal, generate one or more delayed signals from the signal, determine a first duration of a first portion of the repeating pattern and a second duration of a second portion of the repeating pattern using the one or more delayed signals, and adjust a current duty cycle of the signal based on the first duration and the second duration.

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.