332results about "Time-to-digital converters" patented technology

Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.

In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.

A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I / O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I / O buffer.

The invention discloses a high-precision high-speed pipeline time-to-digital converter. The converter comprises a pulse selection circuit, a parallel delay line TDC, a margin extraction module, a time register type TDC, a vernier type TDC and a digital encoder. The pulse selection circuit converts an input bipolar time signal into a unipolar time signal and generates a polarity bit, the three TDCs are sequentially in transmission connection to form a three-stage running water working mode, and the first-stage parallel delay line TDC is used for roughly quantizing and determining a value of a high binary bit; meanwhile, the output end is connected with the margin extraction module to generate time margin and transmit the time margin to the second stage for fine quantization, thereby compensating the quantization error of the first stage and improving the accuracy. And after the second-stage time register type TDC is quantized, the time margin can be directly generated and transmitted to the third-stage vernier type TDC for fine quantization, so that the use of a digital time converter is reduced, and the conversion efficiency is improved. And the digital encoder encodes and outputs the TDC quantized data.

A method is for measuring a time lapse between a trigger and a pulse of a clock of a time-to-digital converter (TDC) device. The method includes the steps of: a) providing a delay line signal to a delay line of a TDC device; b) subsequently, at a measurement clock pulse: obtaining a measurement delay line state representing states of the delay cells; c) subsequently and within half a clock period of the measurement clock pulse: basing the delay line signal on a clock signal and providing the delay line signal based on the clock signal to the delay line; d) subsequently, at a calibration clock pulse: obtaining a calibration delay line state representing states of the delay cells, and e) computing the time lapse between the trigger and the measurement clock pulse based on the measurement amount of delay cells and the calibration amount of delay cells.

A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.

A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

A CMOS integrated chip (1) comprising a time-to-digital converter, TDC, circuit (2) for light detection and ranging, lidar, applications, comprises a start channel (10) comprising an input (11) for a start signal (ST), and at least one stop channel (20, 30) comprising an input (21, 31) for a stop signal (SP). It further comprises a TDC element (40) for each of the start and stop channels (10, 20, 30), wherein the TDC element (40) is configured to store respective counts when triggered by the start signal (ST) or the stop signal (SP), respectively. It further comprises a calculation unit (50) coupled to each TDC element (40) and configured to determine a time difference (ΔT) associated with the start signal (ST) and the stop signal 8SP) based on the counts, and an instruction driven communication interface (60) comprising at least two bidirectional data pins (63, 64). Further, a time-of-flight measurement system and a method of operating the CMOS integrated chip (1) is provided.

The invention is suitable for the technical field of automatic measurement, and particularly relates to a time-to-digital conversion method and a time converter, and the method comprises the steps: inputting a to-be-measured signal into a carry chain, and generating a delay signal of the first to-be-measured signal; determining the edge of the to-be-detected signal according to the clock signal and the delay signal of the to-be-detected signal, wherein the edge of the to-be-detected signal comprises a rising edge and a falling edge; determining a coarse time count value of the to-be-measured signal according to the edge of the to-be-measured signal; determining a fine time measurement value of the to-be-measured signal according to the delay signal of the to-be-measured signal; and determining the timestamp of the edge of the to-be-measured signal according to the fine time measurement value of the to-be-measured signal and the coarse time count value of the to-be-measured signal. According to the invention, the rising edge and the falling edge of the first to-be-tested signal are determined to obtain the timestamps of the rising edge and the falling edge on the same time axis, so that the duration time of the to-be-tested signal can be quickly and accurately obtained.

The present invention relates a multi-shot time-to-digital converter and a time-measurement device. The multi-shot time-to-digital converter includes a time-to-digital conversion circuit and a timing control circuit. The timing control circuit is coupled to the time-to-digital conversion circuit and sending a start signal to the time-to-digital conversion circuit multiple times for measuring a time interval corresponding to the start signal. The time-to-digital conversion circuit obtains a fine phase time based on a plurality of clock signals to measure the time interval and provides a plurality of time-to-digital codes for digital processing. The clock signals have different phases. The time-to-digital codes are further processed to obtain the time-to-digital codes with better resolution.

The invention relates to an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and calculation integrated chip, and the circuit comprises a first comparator which is used for comparing an input first voltage signal with a first reference signal, so as to output a first digital signal; the charge pump is used for receiving the first digital signal as an enable voltage, performing voltage reduction on an input first voltage signal under the enable voltage and outputting a second voltage signal; the voltage-time converter is used for mapping the second voltage signal into a time domain signal; and a time-to-digital converter for mapping the time domain signal into a second digital signal and outputting the first digital signal and the second digital signal as a combination. The whole input voltage range is folded once through the two-stage structure, the linear input interval and performance of the VTC under the large input voltage are optimized through the charge pump and the self-bias low-voltage cascode current mirror, and the time domain analog-to-digital conversion circuit with the wide input range and high precision is achieved.

The invention is suitable for the technical field of measurement, and provides a time interval measurement method and device, a time-to-digital converter and a medium, and the time interval measurement method comprises the steps: carrying out the delay processing of a received signal, and obtaining a plurality of delay signals; sampling the received signal at a first hopping edge and a second hopping edge of a sampling clock signal to obtain a first sampling moment; sampling the plurality of delay signals at a first hopping edge and a second hopping edge of a sampling clock signal to obtain a second sampling moment; and according to the first sampling moment and the second sampling moment, determining a receiving moment of the received signal, and obtaining a time interval between a transmitting moment of a transmitting signal and the receiving moment. According to the scheme, the measurement accuracy of the time interval is improved, and occupation of logic resources is reduced.

The invention discloses an implementation method of a high-precision time-to-digital converter, and relates to the technical field of time mode signal processing. The delay chain comprises a Start signal channel and a plurality of Stop signal channels, each delay chain corresponds to one channel, each delay chain is formed by cascading a circuit with a delay function as a delay unit, the chain structure is divided into an integral chain and a differential chain, the integral chain is that one channel corresponds to one independent delay chain, and the differential chain is that one channel corresponds to one independent delay chain. The difference chain regards two delay chains corresponding to two adjacent channels as a group, and the time difference of signals reaching the input ends of the two delay chains is maintained for 1 / 2 of the delay duration of a single-stage delay unit through a back-end constraint physical layout wiring rule, so that difference is formed. According to the invention, the maximum time resolution of TDC can reach about 12ps, and the test precision is lt; and the dynamic range is about 67 ms, so that high-precision time interval measurement capable of being dynamically calibrated is realized.

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

Provided is a TD converter including: a plurality of oscillators which at least include a first oscillator and a second oscillator receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock; and a computation circuit which calculates a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention relates to a particle number resolution time-to-digital conversion system, method and equipment and a medium. The system comprises a signal processing module which is used for processing a received pulse signal through an amplification delay circuit, a first amplification circuit and a second amplification circuit to obtain a first analog signal, a second analog signal and a third analog signal; the time-to-digital conversion module is used for processing the first analog signal and the second analog signal and outputting a time thermometer code representing time information; the particle number distinguishing module is used for receiving the third analog signal and carrying out particle number distinguishing to generate a particle number thermometer code representing particle number information; and the data processing storage module is used for respectively converting the time thermometer code and the particle number thermometer code into a time binary code and a particle number binary code and storing the time binary code and the particle number binary code in the same storage word. By adopting the system, multi-type particle detection and large-range and high-precision time measurement can be realized.

The invention relates to a differential voltage time-digital converter for preventing large based on Double-tailed, and the differential voltage time-digital converter comprises a Double-tailed dynamic latch comparator which carries out the linear amplification of an input differential voltage, and outputs a differential voltage; a voltage time domain converter (VTC) which converts the output differential voltage into a time difference signal and outputs a first delay voltage and a second delay voltage; the input end of the polarity judging device is connected with the VTC, and the polarity judging device is used for outputting a polar code as the highest bit of a thermometer code; the input end of the edge selector ELS is connected with the VTC, and the edge selector ELS is used for generating an EARLY signal and a LATE signal according to the first delay voltage and the second delay voltage; and the input end of the delay chain type time-to-digital domain converter TDC is connected with the edge selector ELS, and the delay chain type time-to-digital domain converter TDC is used for quantizing the time difference between the EARLY signal and the LATE signal and generating a thermometer code. According to the invention, the idea of high-speed latch is introduced to obtain stable differential input voltage with smooth waveform, so that the VTC module can carry out time domain transformation on the differential input voltage, and the resolution of the TDC is improved.

The invention relates to a zero carry mismatch digit-expandable high-precision photon flight time timing circuit, and belongs to the technical field of photoelectric detection / three-dimensional laser radar. The device comprises a photosensitive element, a photosensitive element pixel circuit connected with the photosensitive element, a timing circuit connected with the photosensitive element pixel circuit, and a data reading circuit connected with the timing circuit. The timing circuit comprises a time-to-digital conversion circuit which is connected with a peripheral clock and time sequence control circuit and comprises a high-precision low-order sampling circuit and a high-order sampling circuit, and a mismatch correction circuit which is connected with the time-to-digital conversion circuit and comprises a phase jump trigger circuit and a digital continuity comparison circuit. And the carry mismatch correction circuit is connected with the flip detection circuit and comprises a numerical value continuity comparison circuit. According to the invention, the problems of high error code of timing quantization, non-monotonous timing result and reduced timing precision when a timing circuit is applied to a device with a larger array scale can be solved, the time quantization range is expanded, and the timing precision of practical application is improved.

A phase-locked loop (PLL) includes a digitally controlled oscillator (DCO) that generates a DCO output signal. A feedback divider is coupled to the DCO output signal, divides the DCO output signal, and generates a feedback clock signal. The feedback clock signal is generated as a pulse having a pulse width equal to one period of the DCO output signal. A time-to-digital converter (TDC) receives a reference clock signal and the feedback clock signal and generates a TDC output that indicates a phase difference between the reference clock signal and the feedback clock signal. The TDC output also provides gain information indicating how many delay elements correspond to the period of the DCO output signal. The gain information can be used to more accurately cancel quantization error in the PLL.

The present invention discloses a neural network measurement and calibration system and method for TDL-TDC, the system comprising: a TDL-TDC module, which uses a code density calibration method to complete the initial calibration of the delay chain and obtain an initial calibration value; a temperature sensing module, which collects the system operating temperature on the FPGA chip and obtains operating temperature information; a host computer neural network calibration module, which builds a multi-layer learning network, uses the operating temperature information and the initial calibration value as the input of the network, outputs the delay time of the delay unit, and establishes a corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit. The present invention finds out the corresponding nonlinear change relationship between the delay time data of the delay unit and the temperature data through the learning network, and in actual work, only one calibration and temperature collection are required to obtain a more accurate nonlinear calibration result of each section of the current delay chain.

A time to digital conversion circuit includes a first measurement block and one or a plurality of second measurement blocks. The first measurement block activates a control signal in accordance with activation of a start signal and measures time from the activation of the start signal to a first edge of a common clock signal. The second measurement block includes a lower measurement circuit and an upper measurement circuit, which are enabled by the activation of the control signal. The lower measurement circuit measures time from activation of a stop signal to a second edge of the common clock signal, and the upper measurement circuit measures time from the first edge to the second edge.

An integrated CMOS chip (1) with a time-to-digital converter (TDC) circuit (2) for light detection and ranging (LIDAR) applications comprises a start channel (10) with an input (11) for a start signal (ST) and at least one stop channel (20, 30) with an input (21, 31) for a stop signal (SP). It further comprises a TDC element (40) for each of the start and stop channels (10, 20, 30), wherein the TDC element (40) is configured to store corresponding counts when triggered by the start signal (ST) or the stop signal (SP), respectively. It further comprises a calculation unit (50) coupled to each TDC element (40) and configured to determine a time difference (ΔT) associated with the start signal (ST) and the stop signal (ΔSP) on the basis of the counts, and a command-controlled communication interface (60) comprising at least two bidirectional data pins (63, 64).Furthermore, a time-of-flight measurement system and a method for operating the integrated CMOS chip (1) are provided.

A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.

A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

Systems and methods for correcting timing information associated with captured nuclear imaging data, and for reconstructing medical images based on the corrected timing information, are disclosed. In some embodiments, an image scanning system scans a subject, detects an event, and generates timing data for the detected event. The timing data includes a first number of bits, and characterizes a time that a crystal of the image scanning system detected the event. The image scanning system shifts the first number of bits by a predetermined amount to generate a second number of bits, where the second number of bits includes at least one bit representing a lower order time value than the least significant bit of the first number of bits of the timing data. Further, the image scanning system generates timing correction data for the event based on the second timing data.

Provided is a time to digital converter that outputs time interval digital data having multiple bits according to a time interval from a first timing to a second timing, the time to digital converter including a first circuit configured to generate lower order bits among the multiple bits, a second circuit configured to generate higher order bits among the multiple bits, and a third circuit configured to synchronize the first circuit and the second circuit by generating a second signal with use of a first signal output from the first circuit and outputting the second signal to the second circuit, in which the first signal is generated by using a signal with multiple bits among the lower order bits.