217results about "Time-to-digital converters" patented technology

A method is for measuring a time lapse between a trigger and a pulse of a clock of a time-to-digital converter (TDC) device. The method includes the steps of: a) providing a delay line signal to a delay line of a TDC device; b) subsequently, at a measurement clock pulse: obtaining a measurement delay line state representing states of the delay cells; c) subsequently and within half a clock period of the measurement clock pulse: basing the delay line signal on a clock signal and providing the delay line signal based on the clock signal to the delay line; d) subsequently, at a calibration clock pulse: obtaining a calibration delay line state representing states of the delay cells, and e) computing the time lapse between the trigger and the measurement clock pulse based on the measurement amount of delay cells and the calibration amount of delay cells.

A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

The present invention relates a multi-shot time-to-digital converter and a time-measurement device. The multi-shot time-to-digital converter includes a time-to-digital conversion circuit and a timing control circuit. The timing control circuit is coupled to the time-to-digital conversion circuit and sending a start signal to the time-to-digital conversion circuit multiple times for measuring a time interval corresponding to the start signal. The time-to-digital conversion circuit obtains a fine phase time based on a plurality of clock signals to measure the time interval and provides a plurality of time-to-digital codes for digital processing. The clock signals have different phases. The time-to-digital codes are further processed to obtain the time-to-digital codes with better resolution.

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

Provided is a TD converter including: a plurality of oscillators which at least include a first oscillator and a second oscillator receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock; and a computation circuit which calculates a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention relates to a differential voltage time-digital converter for preventing large based on Double-tailed, and the differential voltage time-digital converter comprises a Double-tailed dynamic latch comparator which carries out the linear amplification of an input differential voltage, and outputs a differential voltage; a voltage time domain converter (VTC) which converts the output differential voltage into a time difference signal and outputs a first delay voltage and a second delay voltage; the input end of the polarity judging device is connected with the VTC, and the polarity judging device is used for outputting a polar code as the highest bit of a thermometer code; the input end of the edge selector ELS is connected with the VTC, and the edge selector ELS is used for generating an EARLY signal and a LATE signal according to the first delay voltage and the second delay voltage; and the input end of the delay chain type time-to-digital domain converter TDC is connected with the edge selector ELS, and the delay chain type time-to-digital domain converter TDC is used for quantizing the time difference between the EARLY signal and the LATE signal and generating a thermometer code. According to the invention, the idea of high-speed latch is introduced to obtain stable differential input voltage with smooth waveform, so that the VTC module can carry out time domain transformation on the differential input voltage, and the resolution of the TDC is improved.

A phase-locked loop (PLL) includes a digitally controlled oscillator (DCO) that generates a DCO output signal. A feedback divider is coupled to the DCO output signal, divides the DCO output signal, and generates a feedback clock signal. The feedback clock signal is generated as a pulse having a pulse width equal to one period of the DCO output signal. A time-to-digital converter (TDC) receives a reference clock signal and the feedback clock signal and generates a TDC output that indicates a phase difference between the reference clock signal and the feedback clock signal. The TDC output also provides gain information indicating how many delay elements correspond to the period of the DCO output signal. The gain information can be used to more accurately cancel quantization error in the PLL.

A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

Systems and methods for correcting timing information associated with captured nuclear imaging data, and for reconstructing medical images based on the corrected timing information, are disclosed. In some embodiments, an image scanning system scans a subject, detects an event, and generates timing data for the detected event. The timing data includes a first number of bits, and characterizes a time that a crystal of the image scanning system detected the event. The image scanning system shifts the first number of bits by a predetermined amount to generate a second number of bits, where the second number of bits includes at least one bit representing a lower order time value than the least significant bit of the first number of bits of the timing data. Further, the image scanning system generates timing correction data for the event based on the second timing data.

Provided is a time to digital converter that outputs time interval digital data having multiple bits according to a time interval from a first timing to a second timing, the time to digital converter including a first circuit configured to generate lower order bits among the multiple bits, a second circuit configured to generate higher order bits among the multiple bits, and a third circuit configured to synchronize the first circuit and the second circuit by generating a second signal with use of a first signal output from the first circuit and outputting the second signal to the second circuit, in which the first signal is generated by using a signal with multiple bits among the lower order bits.

This application discloses a method, apparatus, device, and storage medium for digitizing flicker pulses. The digitization method includes: presetting at least two thresholds; synchronously and in parallel comparing a flicker pulse to be processed with the at least two thresholds to determine at least two state change signals corresponding to the at least two thresholds when the flicker pulse to be processed crosses a threshold; performing delay processing on at least one of the state change signals to obtain at least two corresponding delayed state change signals; and using the same sampling module to sequentially sample the delayed state change signals to obtain the corresponding flicker pulse threshold-time pairs. This application can achieve the reuse of the sampling module while ensuring sampling accuracy, greatly saving logic resources.

The application relates to a delay calibration circuit for a time-to-digital converter. The delay calibration circuit comprises a frequency discriminator, a charge pump, a filtering capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is used for receiving a starting signal and outputting a feedback signal after time delay; the frequency discriminator is used for receiving the starting signal and the feedback signal, converting a phase difference between the starting signal and the feedback signal into a voltage pulse signal, and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with a corresponding pulse width to the filtering capacitor under the control of the voltage pulse signal; the filtering capacitor is used for converting the current signal into a time delay control voltage, and applying the time delay control voltage to an input end of the bias voltage generating unit; the bias voltage generating unit is used for generating a bias voltage under the action of the time delay control voltage, and controlling a delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit is convenient to realize and high in precision.

There is provided an apparatus for processing timestamps generated by two or more time-to-digital converters (TDCs) that comprises: at least two TDCs, a reference clock, a counter and a stream generator that output a timestamp data stream (TD #1), a first input signal that is periodic or quasi periodic, a second input signal, an electronic circuit or computer program that takes said timestamp data stream as an input and generates a new timestamp data stream (TD #2). Said electronic circuit or computer program performs refining and rescaling calculations thereby providing means to enhance the accuracy of a plurality of timestamps and to express a plurality of timestamps in a different time reference frame.

A time measurement apparatus 10 includes a TAC circuit 12, a measurement gate 11, a control unit 14 for setting a gate dead time, which is a time during which the measurement gate 11 is set to be in the second state, in the measurement gate 11, and the control unit 14 for deriving and outputting time information related to the detection signal based on a measurement signal output from the TAC circuit 12, and the control unit 14 functioning as a setting unit sets a time, which is an integral multiple of a repetition period of fluorescence detected by the detector 4 and is longer than a dead time of the TAC circuit 12 itself, in the measurement gate 11 as a gate dead time.

The invention discloses a successive approximation hybrid analog-to-digital converter, which comprises a first-stage time domain analog-to-digital converter, a time-to-voltage converter and a second-stage voltage domain analog-to-digital converter, the first-stage time domain analog-to-digital converter is used for carrying out coarse quantization on a time signal converted from an input signal and generating a time residual error; the time-voltage converter is used for converting the time residual error into a voltage residual error and amplifying the voltage residual error; the second-stage voltage domain analog-to-digital converter is used for performing fine quantization on the voltage residual error; and the analog-to-digital converter is used for outputting a digital code according to the roughly quantized signal and the finely quantized signal. The analog-to-digital converter provided by the invention is beneficial to improving the conversion precision and speed. The method can be widely applied to the technical field of electronics.

An ADC (50) is disclosed. It has two VTCs (110a, 110b) for converting a first and a second input voltage, respectively, to pulses with delays corresponding to the magnitudes of these voltages. It further has a pulse-detector circuit (120) coupled to outputs (114a, 114b) of the two VTCs (110a, 110b). The pulse-detector circuit (120) is configured to make a transition from a first logic state (‘0’) to a second logic state (‘F) at a first output (124a) of the pulse-detector circuit (120) in response to the start of the pulse from one of the VTCs (110a) and to make a transition from the first logic state (‘0’) to the second logic state (‘F) at a second output (124b) of the pulse-detector circuit (120) in response to the start of the pulse from the other VTC. Furthermore, the pulse-detector circuit (120) is configured to reset both the first and the second output (124a, 124b) to the first logic state (‘0’) in response to both the first output (124a) and the second output (124b) of the pulse-detector circuit (120) being set in the second logic state (‘1’). The ADC (50) further has a first TDC (130a) coupled to the first output (124a) of the pulse-detector circuit (120) and a second TDC (130b) coupled to the second output (124b) of the pulse-detector circuit (120).

A time-to-digital converter (TDC) circuit including serially-coupled delay units is disclosed. A feedback loop is coupled between a final delay unit of the serially-coupled delay units and an input to the serially-coupled delay units. A counter with a clock input is coupled to an output of the final delay unit. A value of the counter is to be incremented responsive to the counter receiving a toggle signal from the final delay unit.

An embodiment of the present disclosure provides a time-to-digital converter and a control method. The time-to-digital converter includes: at least one time-to-digital conversion unit, the time-to-digital conversion unit including a delay locking module and a signal acquisition module, the delay locking module and the signal acquisition module including a common delay link, the time-to-digital converter having a delay locking mode and a time-to-digital conversion mode; in the delay locking mode, the delay locking module locks the basic delay time of the delay link; in the time-to-digital conversion mode, the signal acquisition module acquires the output signal of the delay link based on the basic delay time of the delay link to determine a signal time difference.

A time to digital converter including multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different transition delays of each buffer. The buffers may be configured to be compatible with a standard cell layout. The buffers may be configured as standard cell logic gate with modified connections. The buffers may be calibrated by selecting a fastest delay value that does not cause overflow in response to a calibration pulse.

The invention discloses a novel time measurement interpolation circuit, which is characterized by comprising a controller, an enabling controlled delay interpolation circuit, k paths of ring oscillation delay chains, a coarse counter, k quantization latch circuits, an encoder and a serializer, the controller generates an enable signal EN and a time measurement latch signal Latch according to the example pulse; the enabling controlled delay interpolation circuit generates a plurality of sub-level enabling signals with the difference of delta tau time in sequence according to the signal EN to drive each loop oscillation delay chain; the coarse counter counts by using a tail-stage output signal of the first loop oscillation delay chain as a counting clock, and inputs a counting value into the serializer; each double-edge sampling quantization latch in the ith quantization latch circuit records time information in the ith loop oscillation delay chain according to the signal Latch and sends the time information to an encoder; the encoder encodes the received time information into binary numbers and inputs the binary numbers into the serializer; and the serializer converts the counting numerical value and the binary number which are input in parallel into serial output.

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.

A time to digital converter including multiple delay lines and an output adder. Each delay line includes multiple series-coupled buffers receiving a start signal, multiple latches each having an input coupled to an output of a buffer and an output providing one of multiple binary values in response to a stop signal, and an adder. Each adder adds the binary values from corresponding latches in response to the stop signal and provides a corresponding one of multiple digital output values. The output adder adds the digital output values from the delay lines and provides a digital output value indicative of a measured delay. The start and stop signals may be buffered to provide multiple start and stop signals each provided one of the delay lines. Each start signal may be delayed by one of multiple different delays. Select logic may combine multiple delay lines into a longer delay line group.

The present application relates to a particle number-resolved time-to-digital conversion system, method, device, and medium. The system includes a signal processing module for processing a received pulse signal through an amplification delay circuit, a first amplification circuit, and a second amplification circuit to obtain a first analog signal, a second analog signal, and a third analog signal; a time-to-digital conversion module for processing the first and second analog signals to output a time thermometer code representing time information; a particle number resolution module for receiving the third analog signal and performing particle number resolution to generate a particle number thermometer code representing particle number information; and a data processing and storage module for converting the time thermometer code and the particle number thermometer code into a time binary code and a particle number binary code, respectively, and storing them in the same memory word. This system enables multi-type particle detection and large-scale, high-precision time measurement.

This invention provides a delay chain analysis system, including a test signal generator, an FPGA chip, and a host computer. The FPGA chip includes a delay chain module and an integrated logic analyzer. The delay chain module includes one or more delay chains. The host computer includes a test controller and a data analyzer. The test signal generator is connected to the FPGA chip, the output of the delay chains is connected to the integrated logic analyzer, and the output of the integrated logic analyzer is connected to the host computer. The test signal generator generates a test signal close to the clock of the delay chains. The delay chains are used to measure minute time intervals. The integrated logic analyzer continuously captures the temperature codes output by the delay chain registers at the rising edge of the clock and transmits them to the host computer. The test controller controls the test process, receives the temperature codes output by the integrated logic analyzer, and stores them as an analyzable file. The data analyzer analyzes the file stored by the test controller to generate a delay time schedule. This invention can reduce the actual bit error rate of the delay chains.

The present invention provides a time-to-digital conversion device with superior resolution in the time domain and a wider measurement range. [Solution] An embodiment of the time-to-digital converter includes a first oscillator configured to output a first clock signal in response to a first event, and a second oscillator configured to output a second clock signal in response to a second event. The embodiment of the time-to-digital converter further includes a phase detector configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is lagging behind the phase of the first clock signal. The count value indicates the time difference between the first event and the second event.

A method for calibrating phase nonlinearity of a digital-to-time converter is provided. The method includes generating a reference signal using a phase-locked loop (PLL) based on a control word. The reference signal has a frequency equal to the frequency of an output signal of the digital-to-time converter. Furthermore, the method includes measuring a temporal sequence of transitions of the output signal from a first signal level to a second signal level and a temporal sequence of transitions of the reference signal from the first signal level to the second signal level. The method also includes adjusting a first entry of a lookup table based on the measured temporal sequence.

A time-to-digital conversion device according to an embodiment of the present disclosure is a time-to-digital conversion device configured to output time digital data according to a time from a first timing to a second timing, including a first circuit that includes an upper counter configured to start counting a clock signal according to the first timing, and generates upper bits of the time digital data; a second circuit that includes a delay element configured to start operation according to the second timing and a lower counter configured to count an oscillation cycle of the delay element, and generates lower bits of the time digital data; and a control circuit that controls a phase of an output signal of the delay element based on the clock signal.