High-precision high-speed pipeline time-to-digital converter

Abstract

The invention discloses a high-precision high-speed pipeline time-to-digital converter. The converter comprises a pulse selection circuit, a parallel delay line TDC, a margin extraction module, a time register type TDC, a vernier type TDC and a digital encoder. The pulse selection circuit converts an input bipolar time signal into a unipolar time signal and generates a polarity bit, the three TDCs are sequentially in transmission connection to form a three-stage running water working mode, and the first-stage parallel delay line TDC is used for roughly quantizing and determining a value of a high binary bit; meanwhile, the output end is connected with the margin extraction module to generate time margin and transmit the time margin to the second stage for fine quantization, thereby compensating the quantization error of the first stage and improving the accuracy. And after the second-stage time register type TDC is quantized, the time margin can be directly generated and transmitted to the third-stage vernier type TDC for fine quantization, so that the use of a digital time converter is reduced, and the conversion efficiency is improved. And the digital encoder encodes and outputs the TDC quantized data.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a high-precision, high-speed pipeline time-to-digital converter. Background Art

[0002] High-performance analog-to-digital converters (ADCs) are the core components of electronic information systems and are also the most complex research hotspots and difficulties in the current integrated circuit design field. With the rapid development of broadband wireless communication technology, higher requirements are also placed on the resolution and sampling rate of analog-to-digital converters. For example, RF direct sampling is the trend of wireless communication development, but the signal bandwidth is hundreds of megahertz or even several gigahertz. Only RF ADCs with ultra-high sampling rates can meet the sampling requirements of such large bandwidth signals. At present, the research results of medium and low precision high-speed analog-to-digital converters greater than 10GS / s at home and abroad also adopt pipeline or time-interleaved hybrid architecture, which is sampled and converted by multiple medium and low speed sub-ADCs through multi-phase clock time-sharing, and finally unified output through timing control coding to achieve high-speed sampling conversion rate. However, if the conversion rate of a single channel is low, more sampling channels are required, and the design difficulty and power consumption are greater, which is far from meeting the needs of the development of current advanced high-performance electronic equipment.

[0003] With the improvement of process technology, the chip operating power supply voltage is also continuously reduced. Traditional single-channel voltage domain ADC is difficult to break through the requirements of low power consumption, high precision and sampling conversion exceeding 1Gsps. In addition, some interleaved work using time domain analog-to-digital converter (TDC) can achieve a signal-to-noise-distortion ratio (SNDR) close to or even exceeding that of SAR ADC under the condition of sampling rate higher than 10GSPS, but there is no time domain interleaved structure that can achieve SNDR similar to that of single channel and traditional pipeline structure. The new ADC architecture based on the principle of time domain quantization to achieve high stability and PVT robustness is the development trend of high-speed and high-performance ADC in the future. How to further integrate the voltage domain and time domain architectures and be compatible with diversified digital single-channel ADC architectures to improve the sampling conversion rate to achieve the purpose of improving system energy efficiency is the main direction of future high-speed and high-performance ADC research. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision, high-speed pipeline time-to-digital converter. By converting the voltage domain signal into a time signal and then quantizing it step by step, the problem that the traditional single-channel voltage domain analog-to-digital converter is difficult to achieve high-speed and high-precision conversion under low power supply voltage conditions is solved.

[0005] The invention provides a high-precision and high-speed pipeline time-to-digital converter, comprising: a pulse selection circuit, a parallel delay line TDC, a margin extraction module, a time register type TDC, a vernier type TDC, and a digital encoder.

[0006] The pulse selection circuit is used to convert the input bipolar time signal into a unipolar time signal and send it to the parallel delay line TDC, and generate a polarity bit; three TDCs are connected in sequence to form a three-stage pipelined working mode; the parallel delay line TDC and the margin extraction module are used as the first stage to roughly quantify and determine the value of the higher-order binary bits, and at the same time, the output stop is connected to the margin extraction module to generate a time margin and transfer it to the second stage for fine quantization; the time register type TDC is used as the second stage to finely quantify the time margin of the first stage and compensate for the quantization error of the first-stage binary bits; after quantization, the time register type TDC cooperates with the external Trigger signal to generate a FULL signal, and can directly generate a time margin and transfer it to the third stage; the cursor type TDC is used as the third stage to precisely quantify the time difference margin between the second-stage Trigger and FULL and output it as a low-order binary value; each stage of TDC contains a temperature code to binary code module, and the output of each stage of TDC is a binary code; the digital encoder processes the binary codes generated by the three-stage TDC to obtain a complete binary code.

[0007] Preferably, the pulse selection circuit includes two groups of combined circuits formed by connecting 4 NMOS transistors and 4 PMOS transistors respectively, a D flip-flop, and an inverter; for the first combined circuit, the source of the P1 transistor is connected to VDD, the drain is connected to the source of the P2 transistor, the gate is connected to the time pulse input terminal TP, the gate of the P2 transistor is connected to the time pulse input terminal TN, the drain of the P2 transistor is connected to the drain of the N1 transistor, the gates of the N1 and N2 transistors are connected to TP, the source of the N1 transistor is connected to the drain of the N2 transistor, and the source of the N2 transistor is grounded; the source of the P3 transistor is connected to VDD, the drain is connected to the source of the P4 transistor, the gate is connected to the time pulse input terminal TN, the gate of the P4 transistor is connected to the time pulse input terminal TP, the drains of the P2, P4, N1, and N3 transistors are connected to the input terminal of the inverter, and the output of the inverter is used as the star output terminal of the first combined circuit; the gates of the N3 and N4 transistors are connected to TN, the source of the N3 transistor is connected to the drain of the N4 transistor, and the source of the N4 transistor is grounded; the input signals of each gate of the second combined circuit and the first combined circuit are symmetric up and down to obtain the stop output terminal. The D flip-flop has a data input terminal T1, an input terminal T2, and a positive output terminal; the data input terminal of the D flip-flop is connected to the time pulse input terminal TP, the input terminal T2 is connected to the time pulse input terminal TN, and the positive output terminal, that is, the polarity output terminal Polar, is connected to the digital encoder.

[0008] Preferably, the parallel delay line TDC includes N delay lines, N D flip-flops and an encoder 1; the D flip-flop has a data input terminal, a clock input terminal, and a data output terminal; the N delay lines are formed by connecting digital logic gates in series, and the delay times of the N delay lines increase in accordance with the minimum resolution time multiplied by the binary weight value. The input terminals of the delay lines are all connected to the star output terminal of the pulse selection circuit, and the output terminals of the delay lines are respectively connected to the data input terminals of the N D flip-flops from the highest bit to the lowest bit according to the decreasing delay; the output terminal star_res of the maximum delay line is connected to the time input terminal star1 of the time register type TDC; the clock input terminals of the N D flip-flops are all connected to the stop output terminal of the pulse selection circuit; the encoder 1 encodes the thermometer code from the lowest bit to the highest bit generated by the data output terminals of the N D flip-flops into a binary code for output, and the binary code output is connected to the input terminal of the remainder extraction module and the digital encoder.

[0009] Preferably, the remainder extraction module includes a delay line and a delay controller; the delay line is formed by connecting delay units formed by cascading multiple two-stage inverters in series; the clock input terminal of the remainder extraction module is connected to the stop output terminal of the pulse selector, and the clock input terminal of the remainder extraction module is connected to each delay unit of the delay line, and the clock feeding point is selected by the delay controller; the delay controller controls the delay time of the stop signal by connecting the clock input terminal of the remainder extraction module to each delay unit of the delay line and selecting the clock feeding point by the delay controller, and the output terminal of the delay line is stop_res and is connected to the time input terminal stop1 of the time register type TDC.

[0010] Preferably, the time register type TDC includes a pulse generation circuit, transmission gate switches, delay units, D flip-flops, and an encoder 2. The pulse generation circuit consists of a D flip-flop with a reset terminal and an OR gate. The data input terminal of the D flip-flop is connected to VDD, the clock input terminal is the time input terminal star1 of the time register type TDC and is connected to the output terminal star_res of the parallel delay line TDC, and the reset terminal is the time input terminal stop1 of the time register type TDC and is connected to the output terminal stop_res of the margin extraction module. The output terminal of the D flip-flop and the external Trigger signal are connected to the two input terminals of the OR gate. The delay unit has an enable terminal and a reset terminal. The enable terminals are all connected to the output terminal of the OR gate. A plurality of delay units are connected in series to form a delay line. The input terminal of the first delay unit is connected to the external SET signal, and at the same time, the inverted SET signal is connected to the reset terminal of each delay unit. The connection points of the delay units of the delay line are all connected to the input terminals of different transmission gate switches and the data input terminals of different D flip-flops. The stop1 signal is connected to the clock input terminals of all D flip-flops after a certain delay. The output terminals of the D flip-flops are connected to the encoder 2. The encoder 2 encodes the thermometer code formed by the output of the D flip-flops into a binary code and generates corresponding control signals to be connected to the control terminals of each transmission gate switch. The output terminals of the transmission gate switches are all connected to the TFULL output terminal of the time register type TDC. The Trigger and TFULL signals form a time margin signal and are respectively connected to the star2 and stop2 input terminals of the cursor type TDC.

[0011] Preferably, the cursor type TDC includes a slow delay line L1, a slow delay line L2, D flip-flops, and an encoder 3. The input terminal of the slow delay line is connected to star2, the fast delay line is connected to stop2, and the output of the delay unit of the slow delay line is connected to the data input terminals of different D flip-flops. The output of the delay unit of the fast delay line is connected to the clock input terminals of the corresponding D flip-flops. The output terminals of the D flip-flops are connected to the encoder 3. The encoder 3 combines the thermometer code output by the D flip-flops with the polarity output by the pulse selector and converts it into a polarity binary code 2 and outputs it to the digital encoder.

[0012] Preferably, the digital encoder performs an addition operation on the non-polar binary codes output by the first-stage and second-stage TDCs, and further combines the polarity encoding output by the pulse selector into a polarity binary code D[M:N]. The polarity binary code D[M:N] performs a subtraction operation when encoded negatively. Further, the binary code output by the cursor type TDC is encoded into a polarity binary code D[0:M - 1]. Further, the polarity binary code D[M:N] is connected and aligned with the polarity binary code D[0:M - 1] output by the cursor type TDC to obtain a complete analog-to-digital conversion value D[0:N].

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] By using the parallel delay line TDC to perform coarse quantization on the higher binary bits and then using the subsequent stage TDC for fine quantization compensation, the accuracy and conversion rate of analog-to-digital conversion are improved. By adopting the full-time-domain quantization method, the requirement for the working power supply voltage is reduced. At the same time, the delay lines are all composed of digital logic gates, which can reduce the overall circuit power consumption and is more suitable for the current advanced process technology. Brief Description of the Drawings

[0015] Figure 1 is the circuit structure of the high-precision high-speed pipelined time-to-digital converter according to an embodiment of the present invention;

[0016] Figure 2 is the circuit structure diagram of the pulse selector according to an embodiment of the present invention;

[0017] Figure 3 is the circuit structure diagram of the parallel delay line TDC and the residue extraction module according to an embodiment of the present invention;

[0018] Figure 4 is the circuit structure diagram of the time register type TDC according to an embodiment of the present invention. Detailed Embodiments

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following provides a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings. Examples of these embodiments are illustrated in the drawings. The embodiments of the present invention shown in the drawings and described according to the drawings are merely exemplary and are not limited to these embodiments.

[0020] In addition, it should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and / or processing steps closely related to the solutions of the present invention are shown in the drawings, while other details less relevant to the present invention are omitted. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0022] To illustrate the technical solutions described in the present invention, the following will be described through specific embodiments, and only the parts related to the embodiments of the present invention are shown.

[0023] Refer to Figure 1, a high-precision high-speed pipelined time-to-digital converter provided by the present invention mainly includes: a pulse selection circuit, a parallel delay line TDC, a margin extraction module, a time register type TDC, a vernier type TDC, and a digital encoder.

[0024] Specifically, the pulse selection circuit is used to convert the input bipolar time signal into a unipolar time signal and send it to the parallel delay line TDC to generate a polarity bit; the three TDCs are connected in sequence to form a three-stage pipelined working mode; the parallel delay line TDC and the margin extraction module are used as the first stage to roughly quantify and determine the value of the higher binary bits, and at the same time, the output end stop is connected to the margin extraction module to generate a time margin and transfer it to the second stage for fine quantization; the time register type TDC is used as the second stage to finely quantify the time margin of the first stage and compensate for the quantization error of the first-stage binary bits; after quantization, the time register type TDC cooperates with an external Trigger signal to generate a FULL signal, which can directly generate a time margin and transfer it to the third stage; the vernier type TDC is used as the third stage to precisely quantify the time difference margin between the second-stage Trigger and FULL and output it as a lower binary value; each stage of the TDC contains a temperature code to binary code module, and the output of each stage of the TDC is a binary code; the digital encoder processes the binary codes generated by the three-stage TDC to obtain a complete binary code.

[0025] Refer to Figure 2 , the pulse selection circuit includes two groups of combined circuits composed of 4 NMOS transistors and 4 PMOS transistors respectively, a D flip-flop, and an inverter; for the first combined circuit, the source of the P1 transistor is connected to VDD, the drain is connected to the source of the P2 transistor, the gate is connected to the time pulse input terminal TP, the gate of the P2 transistor is connected to the time pulse input terminal TN, the drain of the P2 transistor is connected to the drain of the N1 transistor, the gates of the N1 and N2 transistors are connected to TP, the source of the N1 transistor is connected to the drain of the N2 transistor, and the source of the N2 transistor is grounded; the source of the P3 transistor is connected to VDD, the drain is connected to the source of the P4 transistor, the gate is connected to the time pulse input terminal TN, the gate of the P4 transistor is connected to the time pulse input terminal TP, the drains of the P2, P4, N1, and N3 transistors are connected to the input terminal of the inverter, and the output of the inverter is used as the star output terminal of the first combined circuit; the gates of the N3 and N4 transistors are connected to TN, the source of the N3 transistor is connected to the drain of the N4 transistor, and the source of the N4 transistor is grounded; the gate input signals of the second combined circuit and the first combined circuit are symmetric up and down to obtain the stop output terminal. The D flip-flop has a data input terminal T1, an input terminal T2, and a positive output terminal; the data input terminal of the D flip-flop is connected to the time pulse input terminal TP, the input terminal T2 is connected to the time pulse input terminal TN, and the positive output terminal, that is, the polarity output terminal Polar, is connected to the digital encoder.

[0026] Refer to Figure 3, the parallel delay line TDC includes N delay lines, N D flip-flops and an encoder 1; the D flip-flop has a data input terminal, a clock input terminal, and a data output terminal; the N delay lines are formed by connecting digital logic gates in series, and the delay times of the N delay lines increase in a manner of multiplying the minimum resolution time by the binary weight value. The input terminals of the delay lines are all connected to the star output terminal of the pulse selection circuit, and the output terminals of the delay lines are respectively connected to the data input terminals of the N D flip-flops from the highest bit to the lowest bit according to the decreasing order of delay; the output terminal star_res of the maximum delay line is connected to the time input terminal star1 of the time register type TDC; the clock input terminals of the N D flip-flops are all connected to the stop output terminal of the pulse selection circuit; the encoder 1 encodes the thermometer code from the lowest bit to the highest bit generated by the data output terminals of the N D flip-flops into a binary code for output, and the binary code output is connected to the input terminal of the remainder extraction module and the digital encoder.

[0027] Further, the remainder extraction module includes a delay line and a delay controller; the delay line is formed by connecting delay units formed by cascading multiple two-stage inverters in series; the clock input terminal of the remainder extraction module is connected to the stop output terminal of the pulse selector, the clock input terminal of the remainder extraction module is connected to each delay unit of the delay line, and the clock feeding point is selected by the delay controller; the delay controller controls the delay time of the stop signal according to the binary code output by the parallel delay line TDC by connecting the clock input terminal of the remainder extraction module to each delay unit of the delay line and selecting the clock feeding point by the delay controller, and the output terminal of the delay line is stop_res and is connected to the time input terminal stop1 of the time register type TDC.

[0028] Specifically, the working principle of the remainder extraction module is that if the delay of the delay unit of the delay line is Td, the number of enabled units of the delay controller is n, and the enabled delay units are the last n delay units of the delay line, and the delay controller selects the first enabled delay unit as the feeding end of the stop signal, then the delay time of the stop signal controlled by the remainder extraction module is Tc = n × Td, where Td is the minimum resolution time of the parallel delay line.

[0029] Specifically, the calculation method for controlling the delay magnitude of the stop signal is that assuming the maximum delay passed by the star signal is Tmax and the time quantized by the parallel delay line TDC is Tq, then the time magnitude Tc to be controlled for the delay of the stop signal is Tc = Tmax - Tq, that is, the delay time of the controlled stop signal and the quantized time are in a complementary relationship. The star_res and stop_res signals after delay are the first-stage remainder signals.

[0030] Refer to Figure 4, the time register type TDC includes a pulse generation circuit, transmission gate switches, delay units, D flip-flops, and an encoder 2; the pulse generation circuit consists of a D flip-flop with a reset terminal and an OR gate. The data input terminal of the D flip-flop is connected to VDD, the clock input terminal is the time input terminal star1 of the time register type TDC and is connected to the output terminal star_res of the parallel delay line TDC, and the reset terminal is the time input terminal stop1 of the time register type TDC and is connected to the output terminal stop_res of the remainder extraction module. The output terminal of the D flip-flop and the external Trigger signal are connected to the two input terminals of the OR gate; each delay unit has an enable terminal and a reset terminal. The enable terminals are all connected to the output terminal of the OR gate. Multiple delay units are connected in series to form a delay line. The input terminal of the first delay unit is connected to the external SET signal, and at the same time, the inverted SET signal is connected to the reset terminal of each delay unit. The connection points of the delay units of the delay line are all connected to different transmission gate switch input terminals and different D flip-flop data input terminals. The stop1 signal is connected to the clock input terminals of all D flip-flops after a certain delay. The output terminals of the D flip-flops are connected to the encoder 2; the encoder 2 encodes the thermometer code formed by the output of the D flip-flops into a binary code and generates corresponding control signals to be connected to the control terminal of each transmission gate switch; the output terminals of the transmission gate switches are all connected to the TFULL output terminal of the time register type TDC; the Trigger and TFULL signals form a time margin signal and are respectively connected to the star2 and stop2 input terminals of the cursor type TDC.

[0031] Further, the cursor type TDC includes a slow delay line L1, a slow delay line L2, D flip-flops, and an encoder 3; the input terminal of the slow delay line is connected to star2, the fast delay line is connected to stop2, and the output of the delay unit of the slow delay line is connected to different D flip-flop data input terminals; the output of the delay unit of the fast delay line is connected to the clock input terminal of the corresponding D flip-flop, and the output terminal of the D flip-flop is connected to the encoder 3; the encoder 3 combines the thermometer code output by the D flip-flop with the polarity output by the pulse selector and converts it into a polarity binary code 2 and outputs it to the digital encoder.

[0032] Further, the digital encoder performs an addition operation on the non-polar binary codes output by the first-stage and second-stage TDCs, and further combines the polarity encoding output by the pulse selector into a polarity binary code D[M:N]; the polarity binary code D[M:N] performs a subtraction operation when negatively encoded; further, the binary code output by the cursor type TDC is encoded into a polarity binary code D[0:M - 1], and further, the polarity binary code D[M:N] is connected and aligned with the polarity binary code D[0:M - 1] output by the cursor type TDC to obtain a complete analog-to-digital conversion value D[0:N].

[0033] Although the preferred embodiments of the present invention have been described, additional changes and modifications can be made by those skilled in the art once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present invention.

[0034] It should be noted that, herein, the terms "including", "comprising", or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement "including one" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0035] Finally, it should be noted that: Obviously, the above embodiments are merely examples for clearly illustrating the present invention and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or variations derived therefrom still fall within the protection scope of the present invention.

Claims

1. A high-precision, high-speed pipeline time-to-digital converter, characterized in that: include: Pulse selection circuit, parallel delay line TDC, margin extraction module, time register type TDC, vernier type TDC, digital encoder; The pulse selection circuit is used to convert the input bipolar time signal into a unipolar time signal and send it to the parallel delay line TDC to generate a polarity bit; the three TDCs are connected in sequence to form a three-stage pipeline working mode; the parallel delay line TDC and the margin extraction module are used as the first stage to coarsely quantize and determine the value of the high binary bit, and at the same time, the output end is connected to the margin extraction module to generate the time margin and pass it to the second stage for fine quantization; the time register type TDC is used as the second stage to finely quantize the first stage time margin and compensate for the first stage binary bit quantization error; the time register type TDC generates a FULL signal in conjunction with an external Trigger signal after quantization, and can directly generate a time margin and pass it to the third stage; the vernier type TDC is used as the third stage to precisely quantize the time difference margin between the second stage Trigger and FULL and output it as a low-bit binary value; each stage of TDC contains a temperature code to binary code module, and each stage of TDC outputs a binary code; the digital encoder processes the binary code generated by the three-stage TDC to obtain a complete binary code.

2. The high-precision high-speed pipeline time-to-digital converter according to claim 1, characterized in that: The pulse selection circuit comprises two groups of combinational circuits formed by connecting 4 NMOS tubes and 4 PMOS tubes, a D trigger and an inverter; in the first combinational circuit, the source of tube P1 is connected to VDD, the drain is connected to the source of tube P2, the gate is connected to the time pulse input terminal TP, the gate of tube P2 is connected to the time pulse input terminal TN, the drain of tube P2 is connected to the drain of tube N1, the gates of tube N1 and tube N2 are connected to TP, the source of tube N1 is connected to the drain of tube N2, and the source of tube N2 is grounded; the source of tube P3 is connected to VDD, the drain is connected to the source of tube P4, the gate is connected to the time pulse input terminal TN, the gate of tube P4 is connected to the time pulse input terminal TP, the drains of tubes P2, P4, N1 and N3 are connected to the input terminal of the inverter, and the output of the inverter is used as the star output terminal of the first combinational circuit, the gates of tubes N3 and N4 are connected to TN, the source of tube N3 is connected to the drain of tube N4, and the source of tube N4 is grounded; the gate input signals of the second combinational circuit and the first combinational circuit are symmetrical up and down to obtain the stop output terminal. The D flip-flop has a data input terminal T1, an input terminal T2 and a positive output terminal; the data input terminal of the D flip-flop is connected to the time pulse input terminal TP, the input terminal T2 is connected to the time pulse input terminal TN, and the positive output terminal, namely the polarity output terminal Polar, is connected to the digital encoder.

3. The high-precision high-speed pipeline time-to-digital converter according to claim 1, characterized in that: The parallel delay line TDC includes N delay lines, N D flip-flops and an encoder 1; the D flip-flops have a data input terminal, a clock input terminal and a data output terminal; the N delay lines are all formed by digital logic gates connected in series, and the delay time of the N delay lines increases by the minimum resolution time multiplied by the binary bit weight value, the delay line input terminals are all connected to the star output terminals of the pulse selection circuit, and the delay line output terminals are respectively connected to the data input terminals of N D flip-flops from high to low according to the delay from large to small; the lead-out output terminal star_res of the maximum delay line is connected to the time input terminal star1 of the time register type TDC; the clock input terminals of the N D flip-flops are all connected to the stop output terminal of the pulse selection circuit; the encoder 1 encodes the thermometer code from low to high generated by the data output terminals of the N D flip-flops into a binary code output, and the binary code output is connected to the input terminal of the residual extraction module and the digital encoder.

4. The high-precision high-speed pipeline time-to-digital converter according to claim 1, characterized in that: The residual extraction module includes a delay line and a delay controller; the delay line is composed of delay units formed by multiple two-stage inverters connected in series; the clock input end of the residual extraction module is connected to the stop output end of the pulse selector, the clock input end of the residual extraction module is connected to each delay unit of the delay line, and the clock feed point is selected by the delay controller; the delay controller controls the enable quantity and clock feed point of the delay unit according to the binary code output by the parallel delay line TDC, and then controls the delay time of the stop signal, and the output end of the delay line is stop_res connected to the time input end stop1 of the time register type TDC.

5. The high-precision high-speed pipeline time-to-digital converter according to claim 1, characterized in that: The time register type TDC includes a pulse generating circuit, a transmission gate switch, a delay unit, a D flip-flop, and an encoder 2; the pulse generating circuit is composed of a D flip-flop with a reset terminal and an OR gate, the data input terminal of the D flip-flop is connected to VDD, the clock input terminal is the time input terminal star1 of the time register type TDC connected to the output terminal star_res of the parallel delay line TDC, the reset terminal is the time input terminal stop1 of the time register type TDC connected to the output terminal stop_res of the residual extraction module, the output terminal of the D flip-flop and the external Trigger signal are connected to the two input terminals of the OR gate; the delay unit has an enable terminal and a reset terminal, the enable terminals are all connected to the output terminal of the OR gate, and multiple delay units are connected in series to form a delay line, and the first delay The input end of the delay unit is connected to the external SET signal, and the SET signal is connected to the reset end of each delay unit after being inverted. The connection points of the delay units of the delay line are all connected to different transmission gate switch input ends and data input ends of different D flip-flops. The stop1 signal is connected to the clock input ends of all D flip-flops after a certain delay, and the output end of the D flip-flop is connected to the encoder 2; the encoder 2 encodes the thermometer code formed by the output of the D flip-flop into a binary code and generates a corresponding control signal connected to each transmission gate switch control end; the output ends of the transmission gate switch are all connected to the TFULL output end of the time register type TDC; the Trigger and TFULL signals constitute the time margin signal and are respectively connected to the star2 and stop2 input ends of the vernier type TDC.

6. The high-precision high-speed pipeline time-to-digital converter according to claim 1, characterized in that: The vernier TDC includes a slow delay line L1 and a slow delay line L2, a D trigger, and an encoder 3; the input end of the slow delay line is connected to star2, the fast delay line is connected to stop2, and the delay unit output of the slow delay line is connected to the data input end of different D triggers; the delay unit output of the fast delay line is connected to the clock input end of the corresponding D trigger, and the output end of the D trigger is connected to the encoder 3; the encoder 3 converts the thermometer code output by the D trigger into a binary code and outputs it to the digital encoder.

7. The high-precision high-speed pipeline time-to-digital converter according to claim 1, characterized in that: The digital encoder adds the non-polarity binary codes output by the first-stage and second-stage TDCs, and further combines the polarity codes output by the pulse selector to form a polarity binary code D[M:N]; the polarity binary code D[M:N] performs a subtraction operation when the polarity code is negative; the binary code output by the vernier TDC is further encoded into a polarity binary code D[0:M-1], and the polarity binary code D[M:N] is further connected and aligned with the polarity binary code D[0:M-1] output by the vernier TDC to obtain a complete analog-to-digital conversion value D[0:N].

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