158 results about "Test input" patented technology

The invention relates to a fuzzy test Kubernete-based three-party component vulnerability mining method, which comprises the following steps of: firstly, automatically identifying a user controllable function by combining a large language model based on an official document, a configuration list and source code information of a three-party component, and constructing a keyword dictionary to assist in large-scale identification of a potential target function; then analyzing context information of the target function and an interaction relation of the target function in a Kubernetes cluster, constructing a front dependency library required by fuzzy testing, and automatically generating a fuzzy testing driving program; integrating a fuzzy test driving program with a three-party component source code, performing code instrumentation, pre-compiling and corpus optimization, generating test input according to a set variation strategy, dynamically monitoring a coverage rate and an abnormal behavior, and continuously optimizing a test corpus; and finally, based on the crash behavior of the fuzzy test record, analyzing a trigger path of the vulnerability, performing vulnerability verification in a local Kubernetes cluster environment, and finally generating a vulnerability analysis report.

An example system includes: a first large language model; a memory storing instructions and one or more processors operable to execute the instruction to: receive a natural language text string from a client device, where the natural language text string comprises a formal rule expressed in natural language; input the natural language text string and a control string into a large language model (LLM), where the control string is configured to cause the LLM to generate a formal expression representing the formal rule of the natural language text string; output, by the large language model, the formal expression to an output device; and evaluate a consistency of the formal expression using a test input.

The invention discloses a performance test method and device of a storage device, an electronic device and a storage medium, and relates to the technical field of data storage, and the performance test method comprises the steps of controlling the storage device to execute data operation in response to test input; wherein the data operation comprises read operation and / or write operation; in the process of executing the data operation by the storage device, obtaining performance data of the storage device through the performance test model; wherein the performance data comprises performance data of a data link of the storage device and performance data of the storage controller, the storage controller is electrically connected with the storage device through the data link, the data link is used for transmitting data between the storage controller and the storage device, and the performance test model comprises at least one performance monitoring tool. The at least one performance monitoring tool is used for performing performance monitoring on the data link and the storage controller; and generating a performance test report of the storage device according to the performance data. The technical effect of improving the performance test efficiency of the storage device can be achieved.

The invention provides a test script generation method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining test input information containing demand information and test data, carrying out the structural processing of the test input information into a parameter dictionary, and determining a target feature based on the test input information to match a target test template constructed based on a specific grammar template engine, and finally, binding the parameter dictionary with the target test template, and dynamically rendering to generate a script file conforming to a test rule. According to the method, the test input information is subjected to structured processing to form the parameter dictionary, the target template is accurately matched and dynamically rendered, and the script generation efficiency and quality are greatly improved.

Containerized orchestration of secure socket layer virtual private network benchmarking is disclosed. A test portal can accommodate developing test event information (TEI) based on test input information. Test input information can be used to generate event images, e.g., containers, that can be readily scaled, mutated, etc., via a containerization environment instance. One or more event image can be groups into a pod. An event image can be a new container, a previously used container, or a permutation of a container. Event image(s) can be retrieved from external sources, e.g., a library, a commercial vendor of event images, etc. TEI can be based on a pod(s) and communicated to a device-under-test (DUT). DUT performance can be measured, and results can be accessed by an entity, e.g., a test engineer, a results analysis engine, etc. Results can be employed to direct subsequent DUT testing.

The invention belongs to the technical field of automatic testing, and particularly relates to a web automatic testing method and system.The method comprises the steps of automatic script recording and dynamic adaptation, layered framework collaborative testing and data verification and continuous integration testing and test report generation. Wherein automatic script recording is dynamically adapted: recording a page operation script through a playwright tool and applying the page operation script to a UI layer, and when the page UI changes, recording the script again and replacing the original script without element-by-element positioning and code modification; in the hierarchical framework collaborative testing and data verification, a data access layer inputs test data, a UI layer executes page operation and captures display data, and a business logic layer calls an API interface to obtain real data and compares the real data with the display data for verification. According to the method, a web automatic test framework is constructed in combination with the advantages of playwright, a structured engineering project is more suitable for project operation and maintenance, and a sustainable integrated test environment is constructed by utilizing jenkins, so that test input, execution and output are automated.

A semiconductor device includes a plurality of test circuits connected between a test input pin and a test output pin, and a TAP controller connected to a plurality of test control pins and configured to define a data transmission path between the test input pin and the test output pin in response to test control signals received by the plurality of test control pins, the data transmission path including at least one of the plurality of test circuits.

The invention relates to the technical field of software testing, and discloses an LLM and SMT solver-based test case generation method, which is characterized in that a search type test is taken as a core drive, when coverage stagnation occurs, an execution path is subjected to semantic analysis by means of an LLM, a logic expression for describing a target path condition is generated, and in consideration of the limitation of the LLM in logical reasoning, a test case is generated; the system further introduces an SMT solver to perform verification and reasoning on a logic expression output by the LLM, finally feasible test input is generated, and the test efficiency and the coverage rate are improved. According to the method, the efficiency and precision of path coverage are improved, good adaptability and universality are achieved, the method is suitable for various languages and complex program structures, and the intelligent level and engineering practical value of automatic testing are effectively improved. The problem of insufficient accuracy of a large language model in complex path constraint reasoning is effectively relieved.

A network function configuration and test generation framework are configured to generate a test script indicative of a configuration and test cases for verifying a virtual function implemented in a virtualized computing environment. A test input is received that encodes information for verifying a network function. The information includes identification of a test tool, a target testbed for testing the network function, and network information including parameters for network conditions to be operational during testing of the network function. A data parser translates and formats the test input. The formatted test input in input to a topology discoverer configured to identify a network topology of the testbed and which network functions deployed on the testbed are emulated and which network functions deployed on the testbed are real. A configuration generator generates a configuration file usable to configure applicable network functions and their functionalities.

The invention relates to the technical field of software development, and discloses a code testing method and device, computer equipment and a storage medium. The code testing method comprises the following steps: determining test input information and a target test type through an obtained target test request; determining a to-be-tested code and a test scheme file according to the test input information, and preprocessing the to-be-tested code and the test scheme file to obtain a target knowledge graph corresponding to the target test request; searching a target test design task matched with the target test type from a preset test task list; determining a task cue word, a task analysis model and a task output template according to the target test design task, and obtaining a task output result according to the task cue word, the target knowledge graph, the task analysis model and the task output template; when it is confirmed that the task output result is the target test case, test processing on the to-be-tested code is executed according to the target test case, and a target test result is obtained. According to the invention, the interaction complexity is reduced, and the test efficiency and the test accuracy are improved.

A method of updating a sequence model for meta-continual learning, the method including generating an episode comprising a training dataset and a test dataset, updating an internal state of the sequence model by performing a forward pass of the training dataset on the sequence model, wherein the internal state is updated based on a parameter of the sequence model, generating an output corresponding to a test input included in the test dataset by performing a forward pass of the test input on the sequence model based on the updated internal state and the parameter, determining a difference between the output corresponding to the test input and a target test result corresponding to the test input as a meta-loss, and updating the parameter of the sequence model based on the meta-loss.

A network function configuration and test generation framework are configured to generate a test script indicative of a configuration and test cases for verifying a virtual function implemented in a virtualized computing environment. A test input is received that encodes information for verifying a network function. The information includes identification of a test tool, a target testbed for testing the network function, and network information including parameters for network conditions to be operational during testing of the network function. A data parser translates and formats the test input. The formatted test input in input to a topology discoverer configured to identify a network topology of the testbed and which network functions deployed on the testbed are emulated and which network functions deployed on the testbed are real. A configuration generator generates a configuration file usable to configure applicable network functions and their functionalities.

A computing platform may receive test input information comprising input information to validate code for an application. The computing platform may test the code by inputting the test input information into the application and executing the code to produce initial test results. The computing platform may store the test input information / initial test results in a table. The computing platform may identify that subsequent testing should be initiated. The computing platform may automatically identify the test input information and the corresponding initial test results using the stored table. The computing platform may automatically test the application by inputting the test input information into the application and executing the application to produce automated test results. The computing platform may compare the automated test results to the initial test results. Based on identifying that the automated test results match the initial test results, the computing platform may deploy the application.

The invention discloses a method and a system for automatically repairing context learning code vulnerabilities of a large language model, and aims to solve the problems that invalid patches are easily generated, vulnerability causes are misunderstood and verification is lacked in existing LLM zero sample repairing, and a traditional method depends on annotated data or test input. The method comprises the following steps: processing a vulnerability code-patch pair containing a plurality of different CWE types and a target vulnerability code, extracting vulnerability-related codes and constructing an example pool; an adaptive example is selected through comprehensive comparison of semantics, lexical and structural similarity; generating prompt words in combination with related codes and adaptive examples, driving LLMs to generate candidate patches, and outputting effective patches after verification of multiple LLMs; the system comprises a code processing module, an example selection module and a patch generation and verification module. According to the method, LLM and a large amount of annotated data do not need to be finely adjusted, the repair efficiency and accuracy are improved, the labor cost is reduced, multi-language extension is supported, and industrialization potential is achieved.

This application belongs to the field of computer information processing technology and specifically discloses a fuzz testing input optimization device for IoT device firmware. The device includes a static analysis module for analyzing firmware through an API interface, identifying input transfer points of bare metal firmware, and realizing automatic identification through a custom script; a dynamic simulation module for identifying input transfer points of real-time operating system firmware, and implementing a length inference mechanism and a final input transfer algorithm; an input routing mapping module for identifying and dynamically monitoring data retrieval points, input processing points, and availability check instructions in the firmware to obtain mapping results; an input transfer point identification module for automatically identifying the firmware's input transfer points based on the mapping results; and a perception module for dynamically determining the minimum and maximum lengths of input data at the input transfer points, optimizing the input transfer points of firmware fuzz testing, and dynamically calculating the retained data length. This application can improve the efficiency of fuzz testing.

The invention provides a chip trimming system and method, and relates to the technical field of chip trimming, and the system comprises a test mode pin, a selection circuit, a core circuit and a physical trimming circuit. When the test mode pin is enabled, the selection circuit sends a test mode instruction to the core circuit through the first output end. When the core circuit enters a test mode, the test input pin inputs various different signals to the selection circuit; the selection circuit processes the various different signals to obtain various different first trimming code combinations, and sends the various different first trimming code combinations to the core circuit through the second output end; the core circuit responds to a plurality of different first trim code combinations to determine a target trim code combination. And the physical trimming circuit performs packaging-level rewiring connection configuration on the trimming bonding pad of the chip layer according to the target trimming code combination. The chip trimming system can reduce the time and cost of chip production on the premise of ensuring the trimming precision.

The embodiment of the invention discloses an automatic test method and system for an intelligent cockpit large model, and the method comprises the steps: uploading a to-be-tested case document, and generating a test input signal according to the to-be-tested case document; receiving the test input signal, executing a test task for the test input signal, and generating a test response result; collecting a test response result, wherein the test response result comprises a voice recognition result, a human-computer interaction interface screenshot and a system operation log; performing semantic comparison and scoring on the test response result through a judgment large model, and outputting a related index corresponding to the test response result; and generating a test result evaluation report according to the related indexes corresponding to the test response result, and outputting a typical error case list according to the test cases which do not reach the standard in the test result evaluation report. According to the method, the accuracy, the efficiency and the reproducibility of the intelligent cabin model test can be improved.

The invention provides an automatic test system and test method for an input board, and relates to the technical field of railway signal equipment detection application. The method comprises the following steps: the industrial control computer controls the power supply to start and perform self-inspection; the upper computer software carries out initialization setting on communication parameters and working states of the processing board unit, the IO part mainboard, the camera, the controllable power supply and the tested input board and establishes a test log; the upper computer software judges whether each test point of the tested input board is short-circuited or adhered or not, whether an indicator lamp works normally or not and whether each channel runs normally or not by controlling the short-circuit judgment module, the camera and each path of output of the tested input board; and the upper computer software generates all test results into test records and uploads the test records to the control center. According to the invention, by simulating the real working state of the input board, the automatic test of the function and performance of the input board is realized, the test efficiency and the measurement accuracy are improved, the labor intensity is reduced, and the data management is more convenient.

The present application relates to a device for testing electrical performance parameters of bipolar transistors, comprising a test fixture for operatively mechanically and electrically coupling a bipolar transistor to be tested, a test circuit for applying a test input signal to the transistor under test, a measurement circuit for measuring an output signal of the transistor and determining electrical performance parameters thereof, and a controller for automating the testing process and analyzing the measurement data, wherein the test fixture has fluid cavities formed through its length by one or more flow holes, and at least one cooling section in the form of a uniform or non-uniform spiral is arranged in each fluid cavity to extend along the corresponding fluid cavity. The test circuit comprises a signal generator for generating the input signal and a power supply for providing necessary bias voltages to the transistor; the measurement circuit comprises an oscilloscope for measuring the output signal and a computer for processing the measurement data; the controller is capable of automatically acquiring and analyzing the measurement data of the transistor to determine the electrical performance parameters.

The present application discloses a performance testing method and apparatus for a storage device, an electronic device, and a storage medium, relating to the field of data storage technology. The method comprises controlling a storage device to perform data operations in response to a test input; wherein the data operations include read operations and / or write operations; obtaining performance data of the storage device through a performance testing model during the storage device performing the data operations; wherein the performance data includes performance data of a data link of the storage device and performance data of a storage controller, wherein the storage controller is electrically connected to the storage device via a data link, and the data link is used to transmit data between the storage controller and the storage device; the performance testing model comprises at least one performance monitoring tool, and the at least one performance monitoring tool is used to perform performance monitoring on the data link and the storage controller; and generating a performance test report for the storage device based on the performance data. The method can achieve the technical effect of improving the performance testing efficiency of the storage device.

Methods and systems for automated generation of an advanced planning tool (APT) for an advanced planning system (APS) are described. One or more input questions for an operations plan are received. A generic APT contract that is relevant to a given one input question is retrieved. The generic APT contract is customized by mapping parameters defined in the data schema associated with the operations plan to placeholders in the generic APT contract. Generic APT code corresponding to the generic APT contract is customized by replacing placeholders in the generic APT code with parameters defined in the data schema, in accordance with the mapping. The customized APT code is deployed to obtain the executable customized APT. Verification of the customized APT is performed by automatically performing test executions of the customized APT using test inputs automatically generated using the data schema. The customized APT contract is outputted to a user device.

A device (1) having a DA conversion circuit is provided with at least: a processor (10P) that outputs a DA conversion target value; a pre-stage circuit (10FNT) that receives the DA conversion target value from the processor (10P), corrects the DA conversion target value in accordance with the correction data, and outputs the corrected DA conversion target value; a main body circuit (10BDY) that includes one or more DA converter elements to be corrected and that performs DA conversion on the corrected DA conversion value; and an AD converter (10AD). Here, the DA converter element to be corrected is a hybrid DA converter element that outputs, from an output terminal, an analog value obtained by adding an analog value output by a first-type circuit section (SEG1) responsible for an upper level and an analog value output by a second-type circuit section (SEG2) responsible for a lower level. Furthermore, as a calibration test for creating or updating calibration data, the processor (10P): A) acquires a plurality of test pairs, each of which is a pair of a test input value and a test result value having the following characteristics: (A1) the test input value is a value input to the main circuit in a corrected or uncorrected manner as a value to be subjected to DA conversion, and (A2) the test result value is a value input to the main circuit in a corrected or uncorrected manner as a value to be subjected to DA conversion; (A2) The test result value is a value obtained by AD-converting an analog value output by inputting the test input value to the main body circuit by means of an AD converter, and (B) the correction data is updated on the basis of the plurality of test pairs in (A). Here, the number of test pairs acquired during the calibration test is less than N power of 2, N being the number of bits indicating the resolution of the DA converter element to be calibrated.

The invention relates to the technical field of chip testing, and discloses a chip noise anti-interference testing system which comprises a first direct-current power supply, a signal generator, a coupling plate, an evaluation plate and an oscilloscope. The coupling plate is provided with a signal input connector, a power supply input connector, a filter circuit, an electronic switch and an output connector. The signal input connector is connected with the signal generator. The power supply input connector is connected with the output end of the first direct-current power supply. The control end of the electronic switch is connected with the signal input connector, the input end is connected with the power supply input connector through the filter circuit, and the output end is connected with the output connector. The evaluation board is provided with a test input connector, a test output connector, a feedback connector and a chip test seat which is electrically connected with the three connectors. The test input connector is connected with the output connector, the test output connector is connected with the oscilloscope, and the feedback connector is connected with the feedback end of the first direct-current power supply. The system can carry out anti-interference test on a high-current and low-voltage chip with low cost.

The present application provides a method, device and system for testing RRAM. The RRAM testing method is used for a test board; the test board includes a memristor array arranged in rows B and columns W, and an FPGA. The method includes: a host computer displays a parameter setting interface for the current test of the RRAM; the parameter setting interface displays the parameters to be input; receiving parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generating and sending a host computer instruction; the memristor to be tested is one or more memristors in the memristor array; the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and the host computer instruction received; the drive signal is sent to the memristor to be tested; the return signal of the memristor to be tested is received, and the current test is performed.

The invention discloses a deep learning auxiliary test case generation method for parallel program path coverage, and aims to improve the test efficiency of parallel program path coverage. The method comprises the following specific steps: (1) sampling a test input set conforming to uniform distribution characteristics, obtaining a parallel program execution path of each test input, and forming a representative training sample set; (2) training a deep learning model by using the representative training sample set, estimating a candidate test case of the target path by means of the model, and judging whether the candidate case can cover the target path or not; and (3) updating the deep learning model based on the candidate test cases not covering the target paths and the execution paths of the candidate test cases, and repeatedly iterating application and updating of the deep learning model until a test case set covering all the target paths is generated.

Containerized orchestration of secure socket layer virtual private network benchmarking is disclosed. A test portal can accommodate developing test event information (TEI) based on test input information. Test input information can be used to generate event images, e.g., containers, that can be readily scaled, mutated, etc., via a containerization environment instance. One or more event image can be groups into a pod. An event image can be a new container, a previously used container, or a permutation of a container. Event image(s) can be retrieved from external sources, e.g., a library, a commercial vendor of event images, etc. TEI can be based on a pod(s) and communicated to a device-under-test (DUT). DUT performance can be measured, and results can be accessed by an entity, e.g., a test engineer, a results analysis engine, etc. Results can be employed to direct subsequent DUT testing.

The invention discloses a deep learning library API fuzzy testing method based on semantic analysis, and belongs to the field of reliability testing of deep learning systems. The method comprises the following steps of: 1, analyzing an input check logic by using a large language model, extracting an edge condition and forming a structured expression; 2, converting the edge conditions into formalized logic predicates, performing semantic embedding and vectorization processing, and selecting representative conditions to form a variation condition set; 3, generating an executable test program, and automatically repairing a non-running program to form an executable seed program; and 4, generating diversified test input, running at the rear ends of the CPU and the GPU respectively, and identifying potential implementation defects of the deep learning framework by detecting collapse behaviors, running exceptions and cross-device output inconsistency. According to the method, the boundary condition coverage capability can be effectively improved, and the defect detection efficiency of the deep learning library API is improved.

This application proposes a software automated testing method and system, relating to the field of software testing technology. The method includes: constructing a directed acyclic graph (DAG), identifying call path fragments, and constructing test input data; driving the software system under test to execute a test run and generating new function call information; converting the new function call information into a sequence of new nodes, and performing structural difference analysis with historical test run records to generate a cumulative composite difference value; if the cumulative composite difference value is greater than a preset threshold, storing the test input data in a pre-constructed test case library as a new test case, forming an updated test case library; and executing multiple rounds of test runs on the software system under test based on the updated test case library. This allows potential defect paths that were previously continuously uncovered to be systematically discovered, reproduced, and solidified, fundamentally alleviating the dilemma of insufficient accuracy and resource waste caused by the non-evolving nature of testing behavior.

The invention discloses a method and a system for testing synchronous digital quantity injection of a regional stability control system based on network time synchronization, and the method is characterized in that the method comprises the following steps: S1, determining a test case needed by each control strategy function test of the stability control system according to the architecture and functions of the regional stability control system; s2, based on the test state sequence and the test input quantity determined by the test case, automatically generating a stability control system digital quantity injection test script matched with the test state sequence and the test input quantity; s3, through a network time synchronization mechanism, it is ensured that clock references of the test computer systems of all the sites are consistent, triggering time marks of test cases are set in a unified mode, and generated test case scripts are distributed to stability control devices of all the sites; and S4, analyzing the received test case script by the stability control device of each station, and extracting a test state sequence and characteristic parameters related to the station device.

The present invention provides a memory testing method, system, device, and storage medium. The method includes: obtaining test input data based on the bit width of the memory to be tested; constructing test elements based on the test input data according to preset timing rules; and sequentially executing each test element on the memory to be tested; the preset timing rules satisfy the following conditions: after reading the previous address, writing the current address, the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, and the previous address and the current address are adjacent in both logical address sequence and physical address sequence. By adding test elements with insufficient timing margin, the present invention can prevent missed detection of the memory to be tested, thereby improving the test coverage of the memory testing method, increasing the qualified rate of produced memory, and reducing the user's losses caused by unqualified chips.