151 results about "Demultiplexer" patented technology

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

In one embodiment, an optical transceiver includes a digital signal processor, a transmitter coupled to the digital signal processor, and a receiver coupled to the digital signal processor. The receiver is configured to receive an optical signal. The receiver includes a demultiplexer for optical demultiplexing of the optical signal into a plurality of channels, and a plurality of dispersion management devices. Each of the dispersion management devices is associated with a respective channel of the plurality of channels of the demultiplexer and is configured for dispersion compensation at the respective channel. Each of the dispersion management devices includes a thermal control component configured to thermally adjust the dispersion compensation by the dispersion management device based on an output of the digital signal processor.

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

To provide a display device with a narrow border. 【Solution means】A display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit. The second layer has a demultiplexer circuit. The third layer has a display portion. Pixels are arranged in a matrix in the display portion. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit, and the output terminals of the demultiplexer circuit are electrically connected to the pixels. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the pixels. Further, the gate driver circuit and the data driver circuit are not clearly separated and have an overlapping region. Five or more gate driver circuits and data driver circuits can be provided respectively.

This invention relates to a method for fabricating a low insertion loss spatial multiplexer / demultiplexer for multi-core optical fibers, belonging to the field of multi-core optical fiber communication technology. By using single-core fibers of different core diameters at the splice points, this invention effectively improves the fault tolerance of the multiplexer's core arrangement while reducing optical signal leakage at the splice points, thereby reducing insertion loss. This allows for the multiplexing of signals from single-core fibers into multi-core fibers at the input end and the demultiplexing of signals from multi-core fibers into single-core fibers at the output end. The spatial multiplexing / demultiplexer device prepared using this method exhibits lower insertion loss compared to the traditional bundled method, and is simpler and less expensive to operate than polymer waveguide and fused taper methods. The prepared spatial multiplexer / demultiplexer is small, flexible, durable, and suitable for mass production.

The invention provides a display device and an electronic device. The display device includes: a base layer; pixels, each including a sub-pixel; a demultiplexer; a drive circuit portion; a data line connecting the demultiplexer to the sub-pixel; a data base line connecting the demultiplexer to the driving circuit portion and including a first data base line and a second data base line; a data connection line connected to the data base line and including a first data connection line having a 1-1 data connection line and a 1-2 data connection line and a second data connection line having a 2-1 data connection line and a 2-2 data connection line; a bridge layer including a first bridge layer connected to the (1-1) th data connection line and the (1-2) th data connection line, and a second bridge layer connected to the (2-1) th data connection line and the (2-2) th data connection line; and an intermediate bridge pattern layer connecting the first data base line to the first bridge layer, overlapping the second bridge layer, and having a width greater than a width of the first data base line.

Methods, systems, and devices for wireless communication are described. A wireless device may generate a first set of bits and a second set of bits based on inputting information bits and cyclic redundancy check (CRC) bits into a demultiplexer; and performing a constellation shaping operation on the first set of bits. Performing the constellation operation may include: generating a first set of coded bits based on inputting the first set of bits into a polarization encoder; generating a set of shaped bits based on the second set of bits and the transmit power parameter; and generating a set of output bits based on the first set of coded bits and the set of shaped bits. Further, the wireless device may perform an error correction encoding (ECE) operation on the set of output bits and the second set of bits to generate encoded bits; and transmitting the encoded bits.

Disclosed herein are methods and systems for routing traffic. One exemplary system includes a muxponder module deployed in an optical network, the muxponder having an optical receiver, a first and second electrical port, a demultiplexer having a built-in digital cross-connect, and a processor accessing a first calculated carrier frequency to assign traffic streams associated with a first service identification code to a first and second host lane of the first electrical port, and a second calculated carrier frequency to assign traffic streams associated with a second service identification code to a third and fourth host lane of the second electrical port, and having logic to control the digital cross-connect to route a first and a second traffic stream to the first electrical port based on the first service identification code, and a third and a fourth traffic stream to the second electrical port based on the second service identification code.

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

The invention provides a display device and a media data processing method. A media format detector and a demultiplexer are integrated into an automatic demultiplexer module, so that a media data reading module and the automatic demultiplexer module have a one-to-one correspondence relationship, and on the basis of the correspondence relationship, format detection is not needed after the media data reading module reads the media data, so that the media data reading efficiency is improved. Media data can be directly transmitted to the automatic demultiplexer module to be analyzed and processed. The media format detector and the demultiplexer are integrated in the automatic demultiplexer module, so that the media format detector and the demultiplexer can read the media data from the shared buffer area corresponding to the automatic demultiplexer module, and therefore, in the processing process of the media data, the number of independent modules is reduced, and the processing efficiency of the media data is improved. According to the embodiment of the invention, the running memory fixedly occupied by the independent module during running can be effectively reduced, and only one media data needs to be read once and only one piece of media data needs to be cached, so that the occupation of the running memory can be effectively reduced.

A data driver circuit and a display device are discussed, which are capable of reducing peak current and improving ground bouncing by optimizing a spread time of a MUX stage based on the counted bit toggle value of the image data. The display device can include a display panel in which a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a demultiplexer are disposed; a data driver circuit that supplies a data voltage corresponding to image data to a plurality of data channels; and a controller that controls the data driver circuit and supplies the image data to the data driver circuit. The demultiplexer includes a plurality of MUX stages and controls connection between the plurality of data channels and the plurality of data lines through switching operations of the plurality of MUX stages.

The invention discloses a satellite backbone network edge node all-optical data distribution method and system. The system comprises a pumping unit, a data processing unit, a high-nonlinearity medium module, a coupler and a demultiplexer. The backbone laser link is injected into the data processing unit; a first input port and a second input port of the coupler are respectively connected with the pumping unit and the data processing unit; signal light generated by the data processing unit and pump light generated by the pump unit are transmitted to the high-nonlinearity medium module through the coupler, the optical nonlinear four-wave mixing effect is excited, idler frequency light is generated, the obtained idler frequency light has the characteristic of spectrum separation, and then all-optical data distribution processing is achieved through filtering of the demultiplexer. According to the method and the system, the satellite network node data processing performance can be greatly improved, satellite resources are saved, and the problems of data parallel and real-time distribution processing of the high-speed backbone laser link at the edge node of the satellite backbone network are effectively solved.

The invention provides an electronic device. The electronic device comprises a plurality of electronic elements. Each of the plurality of electronic components includes a pixel circuit and a plurality of tunable circuits. A plurality of tunable circuits are coupled to the pixel circuits. The pixel circuit comprises at least one scanning transistor, a plurality of demultiplexer transistors, a plurality of bias transistors and a storage capacitor. The plurality of demultiplexer transistors are coupled to the at least one scan transistor. The plurality of bias transistors are coupled to the plurality of demultiplexer transistors. The storage capacitor is coupled to the data line through at least one scanning transistor. The number of scanning lines of the electronic device can be effectively reduced.

An eight-mode multiplexer / demultiplexer based on a refractive index step type non-degenerate mode main channel is characterized in that a transmission channel is formed by one eight-mode elliptical fiber core (EC) and seven single-mode fiber cores, and the elliptical fiber core at the coordinate center serves as a transmission main channel and penetrates through two sections; the single-mode fiber core serving as a side core is a transmission coupling channel, two ends of the single-mode fiber core are coupled, and the second section is arranged at the rear end of the longest coupling length of the first section; the length of a transmission main channel of the elliptical fiber core is 11.37 mm, the ellipticity rho of the elliptical core is 1.58, the length of a major semi-axis is 7.02 [mu] m, and the length of a minor semi-axis is 4.44 [mu] m; the length of the SMF-HG10 is 8.112 mm, the length of the SMF-HG01 is 4.976 mm, the length of the SMF-HG20 is 3.258 mm, the length of the SMF-HG11 is 1.190 mm, the length of the SMF-HG30 is 1.626 mm, and the length of the SMF-HG21 is 1.964 mm; the refractive index difference between the main modes of the multiplexer and the demultiplexer is greater than 1 * 10 <-3 >, the mode degeneracy of HG30 and HG02 is broken, and the mode preserving function is realized; the refractive index fiber core made of pure silicon dioxide is adopted to reduce loss; the side core is divided into two sections for coupling, so that low-loss and low-crosstalk multiplexing and demultiplexing of eight modes are realized, and MIMO-FREE operation is realized.

The application discloses a multi-channel self-interference cancellation device combined with an optical domain and a digital domain, which comprises a signal branch module a, a reference branch module b and a signal post-processing module c. The signal branch module a comprises n signal processing channels with the same structure, a wavelength division multiplexer (3), a dispersion medium (4), a wavelength division demultiplexer (5) and a multi-wavelength light source (8); each signal processing channel comprises a low-noise amplifier (1), a double-parallel Mach-Zehnder modulator (2), an optical power amplifier (6) and an optical-electricity detector (7) which are all the same. The reference branch module b comprises a low-noise amplifier (1), a double-parallel Mach-Zehnder modulator (2), a tunable laser (12), an optical splitter (9) and a multi-channel analog matching detection branch. The signal post-processing module c comprises an electric coupler (13), an analog-digital converter (14) and a digital signal processing (15). The application also discloses a multi-channel self-interference cancellation method combined with an optical domain and a digital domain. The application realizes self-interference cancellation of an array multi-channel in-band full-duplex system and beam forming of multi-channel useful signals with small array element scale and low operation cost.

A non-degenerate mode few-mode multiplexer / demultiplexer based on a four-core transmission main channel is characterized in that a transmission channel of the mode division multiplexer / demultiplexer is composed of an elliptical four-core super-mode fiber core FEC-SFC and three single-mode fiber cores, the elliptical four-core super-mode fiber core at the coordinate center serves as the transmission main channel, and the single-mode fiber cores SMF1, SMF2 and SMF3 are transmission coupling channels; the length of the transmission main channel FEC-SFC is 3.588 mm, and the lengths of the SMF1, the SMF2 and the SMF3 are respectively 3.588 mm, 1.658 mm and 1.808 mm; the mode field characteristics in the optical fiber can be changed by reasonably setting parameters such as the position, the size and the refractive index distribution of the fiber core; according to the ultra-mode fiber core, the advantages of a pure silicon dioxide fiber core, an elliptical core and an ultra-mode fiber core are fused, the mode degeneracy of LP11a / LP11b is broken, four ultra-mode multiplexing and demultiplexing of LP01, LP11a, LP11b and LP21b are achieved, the refractive index fiber core made of pure silicon dioxide is adopted, and the low-loss performance is achieved; a transmission channel with a large effective refractive index difference is adopted, and the position and the length of the transmission channel are reasonably set, so that the low-crosstalk and high-extinction-ratio performance is realized, and the low-crosstalk and high-extinction-ratio optical fiber can be used for MIMO-FREE operation.

A photonic content addressable memory (CAM) (100) is provided. The photonic CAM (100) comprises: N search lines (101) and a plurality of match lines (102), each match line comprising N photonic CAM cells (110). Each search line (101) is configured to receive a search optical signal and each search optical signal comprises a different wavelength encoding one of N parallel search symbols. Each match line (102) is configured to receive: a wavelength division multiplexed content optical signal comprising a plurality of wavelengths, each wavelength encoding one of N parallel content symbols; and the N search optical signals from the N search lines (101). Each photonic CAM cell is configured to compare a respective search symbol with a respective content symbol and provide an output optical signal that is responsive to the comparison. Each match line (102) also comprises a content optical demultiplexer (120), configured to demultiplex the wavelength division multiplexed content optical signal and provide each CAM cell (110) with the respective content symbol.

In one embodiment, an optical transceiver includes a digital signal processor, a transmitter coupled to the digital signal processor, and a receiver coupled to the digital signal processor, a method for dispersion compensation by the optical transceiver, a computer system, and a storage medium. The receiver is configured to receive an optical signal. The receiver includes a demultiplexer for demultiplexing an optical signal into a plurality of channels and a plurality of dispersion management devices. Each dispersion management device of the plurality of dispersion management devices is associated with a respective channel of the plurality of channels of the demultiplexer and is configured for dispersion compensation at the respective channel. Each dispersion management device includes a thermal control component configured to thermally adjust a dispersion compensation of the dispersion management device based on an output of the digital signal processor.

The present invention discloses a four-mode mode division multiplexing / demultiplexing device based on Y-branching and multimode interference couplers. The device includes a four-mode multiplexer and a four-mode demultiplexer. The four-mode multiplexer and the four-mode demultiplexer multiplex four transmission modes through a four-mode bus waveguide. The four-mode multiplexer and the four-mode demultiplexer are mirror-symmetric structures, each composed of a dual-mode Y-waveguide, a four-mode Y-waveguide, a 2×2 single-mode input paired interferometer (MMI) type, and a 2×2 multimode input general interferometer (MMI) type basic unit. The present invention achieves four-mode multiplexing and demultiplexing by controlling the mode phase in the Y-waveguide and the MMI multimode coupler. The four-mode mode division multiplexer and demultiplexer have low loss, wide bandwidth, compact size, and wide manufacturing tolerance.

A system may include: a first electronic device that receives service classical data and key management system classical data from a first quantum layer, and classical data from a classical data layer, a first multiplexer / demultiplexer that multiplexes the service classical data, the key management system classical data, and the classical data into multiplexed classical data, and the first circulator receives the multiplexed classical data at a first port and routes the multiplexed classical data to a fiber optic channel via a second port. A second circulator at a second electronic device receives the multiplexed classical data from the fiber optic channel on a second port, and routes the multiplexed classical data to the second multiplexer / demultiplexer on a third port, and a second multiplexer / demultiplexer demultiplexes and outputs the service classical data, the key management system classical data, and the classical data.

The present disclosure relates to central units and remote units. One example central unit includes at least one digital-to-analog converter (DAC), at least one first electro-optical converter configured to convert an analog electrical signal output by the DAC into an analog optical signal, at least one first optical processor configured to process the analog optical signal output by the first electro-optical converter, where the first optical processor includes at least one of at least one first optical filter, at least one first optical phase shifter, and at least one first optical power amplifier, a first multiplexer configured to combine analog optical signals output by the first optical processor into one analog optical signal, and a first demultiplexer configured to decompose the one analog optical signal into multiple analog optical signals at different wavelengths.

To provide a multi-stage optical MIMO demultiplexer.SOLUTION: An optical polarization demultiplexer 200 is formed by: a polarization splitter and rotator (PBSR) 202; two 50 / 50 couplers 204 and 206; and two phase shifters 208 and 210. The two phase shifters 208 and 210 are controlled by another control signals Φ1212 and Φ2214. Each of the two phase shifters 208 and 210 is a differential phase shifter. The phase shifter 208 is mounted as an interferometer having two individual phase shift elements 208a and 208b that adjust an optical phase to one direction with one arm of an interferometer, and adjust an optical phase to an opposite direction with the other arm. The phase shifter 210 also has the same structure.SELECTED DRAWING: Figure 2

The invention discloses an embedded multimedia card host device and a loopback test method thereof, and relates to the technical field of embedded multimedia card host devices. The embedded multimedia card host device comprises a loopback test control circuit which generates first pseudo-random sequence data and a data strobe signal corresponding to a first transmission mode, and verifies loopback test data according to a third clock signal to generate a flag signal; the transmitter circuit samples the two according to a transmission clock signal so as to output second pseudorandom sequence data and the first clock signal; the receiver circuit receives the first pseudo-random sequence data and the second pseudo-random sequence data through the input / output interface and outputs the third pseudo-random sequence data and the second clock signal; the delay phase-locked loop outputs the second clock signal as a receiving clock signal; the demultiplexer is used for processing the third pseudorandom sequence data according to the received clock signal so as to generate loopback test data; and a delay circuit which delays the receiving clock signal to generate a third clock signal.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The present disclosure relates to a digital-to-analog converter comprising an impedance network and a transfer function modification circuit. The transfer function modification circuit comprises a DAC and a demultiplexer. The demultiplexer may be used to selectively connect the output of the DAC to different respective nodes of the impedance network, allowing positive or negative currents to be injected into the node and modify the transfer function. By using a demultiplexer to selectively couple to different nodes, the node into which the current is injected may be modified post-manufacture, allowing transfer function modification.

The invention discloses a display panel, a driving method thereof and a display device. The display panel includes: a plurality of sub-pixels; the data lines are electrically connected with the sub-pixels; each demultiplexer comprises n transistors, first electrodes of the n transistors in the same demultiplexer are electrically connected with the same data signal end, second electrodes of the n transistors in the same demultiplexer are electrically connected with the n data lines in a one-to-one correspondence mode, and n is an integer larger than 1; in the first time period, the conduction sequence of the n transistors in the same demultiplexer is a first sequence, in the second time period, the conduction sequence of the n transistors in the same demultiplexer is a second sequence, and the first sequence is different from the second sequence. The embodiment of the invention provides a display panel, a driving method thereof and a display device. The problem of uneven display of the display panel can be solved.

To solve the problem, the present invention aims to provide an optical multiplexer / demultiplexer circuit that is detachable and can adjust a branching ratio, and a branching ratio adjustment method thereof.The optical multiplexer / demultiplexer circuit 301 according to the present invention includes two blocks (10a, 10b) having a groove 12 on one surface 11 and configured such that polished surfaces (51a, 51b) of side-polished optical fiber core wires (50a, 50b) are fitted into the groove 12 to become a part of the surface 11, pressurizing units (20a, 20b) that pressurize the two blocks (10a, 10b) having the surfaces 11 in contact with each other with a magnetic force P in a direction (Z direction) in which the blocks come closer to each other, and an adjustment unit 30 that moves the two blocks (10a, 10b) being pressurized by the pressurizing units (20a, 20b) in a direction of a plane (X-Y plane) including the surfaces 11 to adjust a branching ratio.

In some embodiments, a method includes receiving, at a central processing unit (CPU)-based demultiplexer of a CPU, an input video data stream; performing, at the CPU, an accelerator decoding configuration assessment of an accelerator decoding configuration of an accelerator; and based upon the accelerator decoding configuration assessment, dynamically decoding CPU-based demultiplexer output from the CPU-based demultiplexer using a CPU-based decoding unit and an accelerator-based decoding unit. In some embodiments of the method, the accelerator decoding configuration assessment includes performing an accelerator-based decoding unit hardware configuration assessment of the accelerator-based decoding unit and a CPU-based decoding unit software configuration assessment of the CPU-based decoding unit software utilized for the CPU-based decoding unit.

The application provides a quantum encryption transmission method, system and computer readable storage medium, and the method comprises the following steps: a first network management module sends configuration management information to a first encryption module; the first encryption module forwards the configuration management information to a first QKD module; the first QKD module generates a quantum state optical signal according to the configuration management information; a first multiplexer / demultiplexer transmits the quantum state optical signal to a second multiplexer / demultiplexer, so that a second QKD module measures the quantum state optical signal, generates a quantum key agreement signal according to the quantum state measurement result obtained after the measurement, and makes a second encryption module encrypt and / or sign the quantum key agreement signal; and quantum encryption transmission is realized based on the processed quantum key agreement signal. The method, system and computer readable storage medium can solve the problem that the quantum encryption transmission corresponding to the classical transmission equipment, the QKD module and the encryption module in the prior art cannot be uniformly managed, thereby causing network management and maintenance difficulties.