363 results about "Demultiplexer" patented technology

The invention relates to the technical field of computer network communication, and relates to a reconfigurable router architecture based on buffer sharing and a dynamic routing method. The router architecture comprises a demultiplexer used for distributing data packets to centralized buffer areas of other ports according to port load states; the virtual channel distribution module is configured to determine an output port of the data packet according to a routing algorithm and generate a corresponding virtual channel ID; the centralized buffer area supports multi-port sharing and is divided into a plurality of logic sub-channels according to virtual channel IDs, and each sub-channel manages a data packet queue through a head pointer and a tail pointer; the credit management module is used for monitoring the idle capacity of the centralized buffer area and transmitting congestion information through a reserved bit of a data packet; and the congestion register dynamically records the congestion state of the neighbor node through the congestion information table. According to the invention, the problems of unbalanced load, low utilization rate of a buffer area and high congestion control cost of a traditional router are solved.

The invention discloses a display panel and a display device. A second display area of the display panel is located on at least one side of a first display area in the first direction. The display area comprises a plurality of data lines extending in the second direction; the first data line is arranged in the first display area; the second data line is arranged in the second display area; the non-display area comprises a plurality of multiplexers; the display area comprises a plurality of auxiliary wires; the demultiplexer comprises N switch elements; the first ends of the switch elements of the same demultiplexer are electrically connected with the input end of the demultiplexer; the N first data lines are electrically connected with the second ends of the N switch elements in the same first demultiplexer in a one-to-one correspondence manner; the N auxiliary wires are electrically connected with the second ends of the N switch elements in the same second demultiplexer in a one-to-one correspondence manner; the ratio of the number of the first multiplexers to the number of the second multiplexers ranges from 0.8 to 1.5. According to the technical scheme provided by the invention, the narrow frame design of the display panel is further realized.

A communication network includes first switches interconnected with second switches. Each first switch includes a first integrated circuit (IC) switch chip, downlink ports, and uplink ports. Each second switch includes ports coupled to at least one uplink port of each of the first switches, and a second IC switch chip in an IC package. To permit each second IC switch chip to forward packets amongst a large number of first switches and to reduce a number of external interconnects of the IC package, each second IC switch chip includes sets of multiplexer / demultiplexer circuitry, each multiplexer / demultiplexer circuitry being coupled between an external interconnect, and a set of multiple internal network interfaces of the second IC switch chip. The multiplexer / demultiplexer circuitry demultiplexes a data stream from the external interconnect to multiple internal network interfaces, and multiplexes multiple data streams from the multiple internal network interfaces to the external interconnect.

A display device includes a data driver for supplying a reference voltage and a plurality of data signals to each of output lines, a divider including demultiplexers for supplying the reference voltage and the plurality of data signals, which are supplied from the each of the output lines, to a plurality of data lines, corresponding to control signals, a timing controller for supplying the control signals, and pixels connected to scan lines and the data lines. The pixels located on at least two different horizontal lines are simultaneously supplied with the reference voltage.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

A method of operating a network device is provided. The method can include obtaining incoming data packets, conveying the incoming data packets through a parallel data bus, and using a demultiplexer to split the incoming data packets being conveyed through the parallel data bus onto a plurality of separate independent data paths within the network device. The method can further include using a multiplexer to aggregate or merge data packets from the plurality of data paths onto an egress parallel data bus.

The present disclosure relates to a communication device such as a multiplexer or a demultiplexer, comprising: a housing comprising a common first port and a plurality of second ports; a plurality of cavity filters for transmitting a wireless signal between the first port and a corresponding one of the second ports, each of the plurality of cavity filters comprising one or more cavities formed in the housing and a resonator arranged in each cavity; and a coupler for coupling the first port to each cavity filter. The coupler is arranged in one cavity of each cavity filter, and is coupled to the resonator in the one cavity.

The invention discloses a circuit and a chip for enabling a CXL protocol to support a low-rate serial link. The circuit provided by the invention comprises a link management state machine containing a sending SDS state, a 4-byte clock skew compensation character SKP4B generation circuit and an analysis circuit, an encoder and a decoder supporting a data stream start character SDS, a 128b / 130b encoder and a decoder, a data stream start detection circuit, a 40: 1 parallel-serial conversion circuit, a 32: 1 parallel-serial conversion circuit, a multiplexer, a 1: 40 serial-parallel conversion circuit and a 1: 1 parallel-serial conversion circuit, the output end of the multiplexer is connected with the input end of the demultiplexer through a serial link, and the output end of the demultiplexer is connected with the input end of the demultiplexer through a serial link. The invention aims to enable the CXL protocol to extend and support PCIe Gen1 and Gen2 rates, so that the FPGA chip can use the CXL protocol, and the ASIC chip can use the CXL protocol at a low rate.

A video dynamic mesh coding (v-DMC) decoding system, includes a de-multiplexer that receives and demultiplexes an encoded v-DMC bitstream into: a parameter set and mesh data, geometry, atlas data, and attribute video substreams. The decoding system also includes: a mesh data substream decoder; a video decoder that decodes the geometry data substream; an atlas data substream decoder; a mesh subdivision component that subdivides the one or more base meshes into one or more resampled base meshes based upon the decoded atlas data; a displacement decoder that outputs one or more displacements to verticies of the one or more resampled base meshes; a mesh position refinement component that applies the one or more displacements to the one or more resampled base meshes and outputs one or more resultant meshes; and a video decoder that decodes the attribute video substream into one or more texture images.

The invention discloses a high-capacity optical communication adaptive damage compensation and demodulation system, which is applied to the technical field of optical communication. Comprising a beam splitter, an XFTC-Net model, a wavefront corrector and an OAM demultiplexer. The beam splitter divides the received distorted OAM light beam into transmission light and reflection light, the transmission light and the reflection light are distorted OAM information light beams, the transmission light is input to the wavefront corrector, the reflection light is input to the XFTC-Net model, the wavefront corrector completes distorted OAM light beam adaptive damage compensation by using a first output result of the XFTC-Net model, and the distorted OAM light beam adaptive damage compensation is realized by using a second output result of the XFTC-Net model. And the OAM demultiplexer completes OAM light beam demodulation by using the second output result of the XFTC-Net model. According to the invention, on the basis of completing atmospheric turbulence distortion phase reconstruction, the mode identification of the OAM light beam is realized, a probe light beam path does not need to be additionally arranged, and while the correction precision is ensured, the system complexity is effectively reduced, and the OAM integrating miniaturization and high precision is realized.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

A digital image transmitter includes a wavelength division multiplexer and demultiplexer, a printed circuit board (PCB) unit connected to the wavelength division multiplexer and demultiplexer, a first housing accommodating the wavelength division multiplexer and demultiplexer and the PCB unit, and a second housing covering the first housing, wherein a contact body is arranged between the wavelength division multiplexer and demultiplexer and the first housing, and each of the wavelength division multiplexer and demultiplexer and the first housing contacts the contact body.

In some examples, a tunable dense wavelength division multiplexing (DWDM) optical time domain reflectometer (OTDR) may include a fiber optic link analyzer, executed by at least one hardware processor, to tune a test wavelength of the DWDM OTDR to an effective wavelength of DWDM channels. A non-temperature compensated multiplexer / demultiplexer (Mux / DeMux) located at a distant location, collocated with, or embedded within the DWDM OTDR may selectively connect, based on the test wavelength, the DWDM OTDR to a fiber optic link of a plurality of fiber optic links to test the fiber optic link. A reflective device may be connected to an output of the Mux / DeMux to provide a reference for setting the test wavelength of the DWDM OTDR on a selected channel of the Mux / DeMux.

In some examples, a tunable dense wavelength division multiplexing (DWDM) optical time domain reflectometer (OTDR) may include a fiber optic link analyzer, executed by at least one hardware processor, to tune a test wavelength of the DWDM OTDR to an effective wavelength of DWDM channels. A non-temperature compensated multiplexer / demultiplexer (Mux / DeMux) located at a distant location, collocated with, or embedded within the DWDM OTDR may selectively connect, based on the test wavelength, the DWDM OTDR to a fiber optic link of a plurality of fiber optic links to test the fiber optic link. A reflective device may be connected to an output of the Mux / DeMux to provide a reference for setting the test wavelength of the DWDM OTDR on a selected channel of the Mux / DeMux.

Embodiments are directed to photonic integrated circuits that include a tunable echelle grating mux / demuxes. The tunable echelle grating mux / demuxes are configured to, during operation, selectively generate a monotonic refractive index gradient across a free propagation region in order to adjust the peak transmission wavelength(s) of one or more channels of the echelle grating mux / demux. The tunable echelle grating mux / demuxes described herein may tune these peak transmission wavelengths in a power efficient manner as compared to conventional tunable echelle grating mux / demuxes.

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

A display device includes a circuit layer including emission pixel drivers, and data lines transferring data signals of the emission pixel drivers; a data driver generating the data signals of the emission pixel drivers; and a demultiplexer circuit electrically connected between the data driver and the data lines and including a first demultiplexer transistor turned on by a first demultiplexer control signal and a second demultiplexer transistor turned on by a second demultiplexer control signal. A first data line of the data lines is electrically connected to the data driver through the first demultiplexer transistor and a transfer path shorter than a first extension length. A second data line of the data lines is electrically connected to the data driver through the second demultiplexer transistor and a transfer path longer than or equal to the first extension length.

A display panel and a display device are provided. The display panel includes first data lines located in a first area and connected to first sub-pixels in the first area; second data lines located in a second area and connected to second sub-pixels in the second area; transfer lines located in a display area and connected to the first data lines; and demultiplexers including N switches. Input terminals of the N switches of a same demultiplexer are connected. A first data line is connected to a demultiplexer through a transfer line. i first data lines and j second data lines are connected to output terminals of the N switches. For the same demultiplexer, light-emitting color of first sub-pixels connected to the i first data lines is same as light-emitting color of second sub-pixels connected to the j second data lines; and N≥2, and i+j=N.

The invention discloses a signal transmission system, relates to the technical field of communication, and is used for improving the utilization rate of optical fiber resources. Comprising a first combiner / splitter, a second combiner / splitter, a time-frequency synchronization master station unit, a time-frequency synchronization slave station unit, a first light conversion unit and a second light conversion unit, a first input port of the first combiner / demultiplexer is connected with the time-frequency synchronization master station unit; a second input port of the first combiner / demultiplexer is connected with the first optical conversion unit; a first output port of the first combiner / demultiplexer is connected with a first input port of the second combiner / demultiplexer; a first output port of the second combiner / splitter is connected with the time-frequency synchronization slave station unit; and a second output port of the second combiner / demultiplexer is connected with the second optical conversion unit.

A memory device includes functionality (e.g., mode, command, etc.) to concurrently activate / access a plurality of rows across a corresponding plurality of memory banks. When concurrently accessing the memory banks, the row address and column address are provided to all of the memory banks being accessed. Multiplexer / demultiplexer (e.g., steering logic) may be used to route non-payload (e.g., metadata) from the concurrently activated memory banks to / from the data interface of the memory device. The steering logic may route and / or serialize the metadata from the concurrently activated memory banks of the bank group such that the non-payload data from a respective memory bank is communicated via the same data signal(s) (e.g., DQ[0], DQ[1], etc.) of the data interface.

The present disclosure generally relates to improving the efficiency of a network switching fabric. Some aspects of the present disclosure relate to an apparatus that includes: multiple ports configured to interface with multiple hardware accelerators; multiple multiplexers configured to communicate with the ports via multiple input channels; multiple demultiplexers configured to communicate with the ports via multiple output channels; a first router coupled to the multiplexers and the demultiplexers via a set of header channels, the first router configured to route header portions of one or more messages; and a second router coupled to the multiplexers and the demultiplexers via a set of data channels, the second router configured to route data portions of the one or more messages.

In one embodiment, an optical transceiver includes a digital signal processor, a transmitter coupled to the digital signal processor, and a receiver coupled to the digital signal processor. The receiver is configured to receive an optical signal. The receiver includes a demultiplexer for optical demultiplexing of the optical signal into a plurality of channels, and a plurality of dispersion management devices. Each of the dispersion management devices is associated with a respective channel of the plurality of channels of the demultiplexer and is configured for dispersion compensation at the respective channel. Each of the dispersion management devices includes a thermal control component configured to thermally adjust the dispersion compensation by the dispersion management device based on an output of the digital signal processor.

A time of flight sensor includes a time of flight (TOF) processor having a digital TOF port, a digital input port, and a digital output port, the TOF processor comprising a phase detector including cyclically rotating demultiplexer (DEMUX), a first summer coupled to a first DEMUX output, a second summer coupled to a second DEMUX output, a third summer coupled to a third DEMUX output, a fourth summer coupled to a fourth DEMUX output, and a phase estimator coupled to outputs of the first summer, the second summer, the third summer and the fourth summer and having a phase estimate output; a driver having a digital driver port coupled to the digital TOF port and a driver output port; and an analog-to-digital converter (ADC) having an output port coupled to the digital input port of the digital TOF processor.

Systems and methods are provided for implementing an ultra-scalable high-performance computing (“HPC”) network using dense wavelength-division multiplexing (“DWDM”). The HPC system includes an interconnection of GPU devices, multiplexer / demultiplexer (“mux / demux”) devices, amplifiers, wavelength selective switches (“WSSs”), and optical circuit switches (“OCSs”). Each OCS includes a plurality of micro-electromechanical systems (“MEMS”) mirrors and a plurality of input / output (“I / O”) ports each communicatively coupled to one WSS mux / demux device one WSS. Each WSS mux / demux device is either communicatively coupled to one of the I / O ports of an OCS or one of a plurality of GPU mux / demux devices via an amplifier. Each GPU mux / demux device is communicatively coupled to a number of GPU devices, each including another number GPUs and one or more optoelectronic devices. Selectively controlling the MEMS mirrors of the OCSs and the WSS mux / demux devices of the WSSs allows connecting the GPUs in a network topology for computing a series of computations.

A display panel and a display apparatus, in the display panel, a pixel unit includes a plurality of sub-pixels, the sub-pixels in a same pixel unit are electrically connected to a same scan line and are each electrically connected to different data lines / the display panel further includes demultiplexers, each demultiplexer includes two output terminals connected to different data lines, and is configured to transmit data signals to different data lines. The plurality of sub-pixels of the same pixel unit include at least three sub-pixels with different colors. Accordingly, the pixel units need not to borrow sub-pixels from each other while achieving full-color display of the display panel, which is conducive to improving the stability of display quality, using 1:2 demultiplexers to transmit data signals to sub-pixels ensures that each sub-pixel has sufficient charging time, thereby being conducive to ensuring the display quality of the display panel.

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

The present disclosure relates to a communication device such as a multiplexer or a demultiplexer, comprising: a housing comprising a common first port and a plurality of second ports; a plurality of cavity filters for transmitting a wireless signal between the first port and a corresponding one of the second ports, each of the plurality of cavity filters comprising one or more cavities formed in the housing and a resonator arranged in each cavity; and a coupler for coupling the first port to each cavity filter. The coupler is arranged in one cavity of each cavity filter, and is coupled to the resonator in the one cavity.

Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal. The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

To provide a display device with a narrow border. 【Solution means】A display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit. The second layer has a demultiplexer circuit. The third layer has a display portion. Pixels are arranged in a matrix in the display portion. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit, and the output terminals of the demultiplexer circuit are electrically connected to the pixels. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the pixels. Further, the gate driver circuit and the data driver circuit are not clearly separated and have an overlapping region. Five or more gate driver circuits and data driver circuits can be provided respectively.

This invention relates to a method for fabricating a low insertion loss spatial multiplexer / demultiplexer for multi-core optical fibers, belonging to the field of multi-core optical fiber communication technology. By using single-core fibers of different core diameters at the splice points, this invention effectively improves the fault tolerance of the multiplexer's core arrangement while reducing optical signal leakage at the splice points, thereby reducing insertion loss. This allows for the multiplexing of signals from single-core fibers into multi-core fibers at the input end and the demultiplexing of signals from multi-core fibers into single-core fibers at the output end. The spatial multiplexing / demultiplexer device prepared using this method exhibits lower insertion loss compared to the traditional bundled method, and is simpler and less expensive to operate than polymer waveguide and fused taper methods. The prepared spatial multiplexer / demultiplexer is small, flexible, durable, and suitable for mass production.