247 results about "Demultiplexer" patented technology

The invention relates to the technical field of computer network communication, and relates to a reconfigurable router architecture based on buffer sharing and a dynamic routing method. The router architecture comprises a demultiplexer used for distributing data packets to centralized buffer areas of other ports according to port load states; the virtual channel distribution module is configured to determine an output port of the data packet according to a routing algorithm and generate a corresponding virtual channel ID; the centralized buffer area supports multi-port sharing and is divided into a plurality of logic sub-channels according to virtual channel IDs, and each sub-channel manages a data packet queue through a head pointer and a tail pointer; the credit management module is used for monitoring the idle capacity of the centralized buffer area and transmitting congestion information through a reserved bit of a data packet; and the congestion register dynamically records the congestion state of the neighbor node through the congestion information table. According to the invention, the problems of unbalanced load, low utilization rate of a buffer area and high congestion control cost of a traditional router are solved.

A display device includes a data driver for supplying a reference voltage and a plurality of data signals to each of output lines, a divider including demultiplexers for supplying the reference voltage and the plurality of data signals, which are supplied from the each of the output lines, to a plurality of data lines, corresponding to control signals, a timing controller for supplying the control signals, and pixels connected to scan lines and the data lines. The pixels located on at least two different horizontal lines are simultaneously supplied with the reference voltage.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

A method of operating a network device is provided. The method can include obtaining incoming data packets, conveying the incoming data packets through a parallel data bus, and using a demultiplexer to split the incoming data packets being conveyed through the parallel data bus onto a plurality of separate independent data paths within the network device. The method can further include using a multiplexer to aggregate or merge data packets from the plurality of data paths onto an egress parallel data bus.

The present disclosure relates to a communication device such as a multiplexer or a demultiplexer, comprising: a housing comprising a common first port and a plurality of second ports; a plurality of cavity filters for transmitting a wireless signal between the first port and a corresponding one of the second ports, each of the plurality of cavity filters comprising one or more cavities formed in the housing and a resonator arranged in each cavity; and a coupler for coupling the first port to each cavity filter. The coupler is arranged in one cavity of each cavity filter, and is coupled to the resonator in the one cavity.

The invention discloses a circuit and a chip for enabling a CXL protocol to support a low-rate serial link. The circuit provided by the invention comprises a link management state machine containing a sending SDS state, a 4-byte clock skew compensation character SKP4B generation circuit and an analysis circuit, an encoder and a decoder supporting a data stream start character SDS, a 128b / 130b encoder and a decoder, a data stream start detection circuit, a 40: 1 parallel-serial conversion circuit, a 32: 1 parallel-serial conversion circuit, a multiplexer, a 1: 40 serial-parallel conversion circuit and a 1: 1 parallel-serial conversion circuit, the output end of the multiplexer is connected with the input end of the demultiplexer through a serial link, and the output end of the demultiplexer is connected with the input end of the demultiplexer through a serial link. The invention aims to enable the CXL protocol to extend and support PCIe Gen1 and Gen2 rates, so that the FPGA chip can use the CXL protocol, and the ASIC chip can use the CXL protocol at a low rate.

A video dynamic mesh coding (v-DMC) decoding system, includes a de-multiplexer that receives and demultiplexes an encoded v-DMC bitstream into: a parameter set and mesh data, geometry, atlas data, and attribute video substreams. The decoding system also includes: a mesh data substream decoder; a video decoder that decodes the geometry data substream; an atlas data substream decoder; a mesh subdivision component that subdivides the one or more base meshes into one or more resampled base meshes based upon the decoded atlas data; a displacement decoder that outputs one or more displacements to verticies of the one or more resampled base meshes; a mesh position refinement component that applies the one or more displacements to the one or more resampled base meshes and outputs one or more resultant meshes; and a video decoder that decodes the attribute video substream into one or more texture images.

The invention discloses a high-capacity optical communication adaptive damage compensation and demodulation system, which is applied to the technical field of optical communication. Comprising a beam splitter, an XFTC-Net model, a wavefront corrector and an OAM demultiplexer. The beam splitter divides the received distorted OAM light beam into transmission light and reflection light, the transmission light and the reflection light are distorted OAM information light beams, the transmission light is input to the wavefront corrector, the reflection light is input to the XFTC-Net model, the wavefront corrector completes distorted OAM light beam adaptive damage compensation by using a first output result of the XFTC-Net model, and the distorted OAM light beam adaptive damage compensation is realized by using a second output result of the XFTC-Net model. And the OAM demultiplexer completes OAM light beam demodulation by using the second output result of the XFTC-Net model. According to the invention, on the basis of completing atmospheric turbulence distortion phase reconstruction, the mode identification of the OAM light beam is realized, a probe light beam path does not need to be additionally arranged, and while the correction precision is ensured, the system complexity is effectively reduced, and the OAM integrating miniaturization and high precision is realized.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

A digital image transmitter includes a wavelength division multiplexer and demultiplexer, a printed circuit board (PCB) unit connected to the wavelength division multiplexer and demultiplexer, a first housing accommodating the wavelength division multiplexer and demultiplexer and the PCB unit, and a second housing covering the first housing, wherein a contact body is arranged between the wavelength division multiplexer and demultiplexer and the first housing, and each of the wavelength division multiplexer and demultiplexer and the first housing contacts the contact body.

Embodiments are directed to photonic integrated circuits that include a tunable echelle grating mux / demuxes. The tunable echelle grating mux / demuxes are configured to, during operation, selectively generate a monotonic refractive index gradient across a free propagation region in order to adjust the peak transmission wavelength(s) of one or more channels of the echelle grating mux / demux. The tunable echelle grating mux / demuxes described herein may tune these peak transmission wavelengths in a power efficient manner as compared to conventional tunable echelle grating mux / demuxes.

The invention discloses a signal transmission system, relates to the technical field of communication, and is used for improving the utilization rate of optical fiber resources. Comprising a first combiner / splitter, a second combiner / splitter, a time-frequency synchronization master station unit, a time-frequency synchronization slave station unit, a first light conversion unit and a second light conversion unit, a first input port of the first combiner / demultiplexer is connected with the time-frequency synchronization master station unit; a second input port of the first combiner / demultiplexer is connected with the first optical conversion unit; a first output port of the first combiner / demultiplexer is connected with a first input port of the second combiner / demultiplexer; a first output port of the second combiner / splitter is connected with the time-frequency synchronization slave station unit; and a second output port of the second combiner / demultiplexer is connected with the second optical conversion unit.

The present disclosure generally relates to improving the efficiency of a network switching fabric. Some aspects of the present disclosure relate to an apparatus that includes: multiple ports configured to interface with multiple hardware accelerators; multiple multiplexers configured to communicate with the ports via multiple input channels; multiple demultiplexers configured to communicate with the ports via multiple output channels; a first router coupled to the multiplexers and the demultiplexers via a set of header channels, the first router configured to route header portions of one or more messages; and a second router coupled to the multiplexers and the demultiplexers via a set of data channels, the second router configured to route data portions of the one or more messages.

In one embodiment, an optical transceiver includes a digital signal processor, a transmitter coupled to the digital signal processor, and a receiver coupled to the digital signal processor. The receiver is configured to receive an optical signal. The receiver includes a demultiplexer for optical demultiplexing of the optical signal into a plurality of channels, and a plurality of dispersion management devices. Each of the dispersion management devices is associated with a respective channel of the plurality of channels of the demultiplexer and is configured for dispersion compensation at the respective channel. Each of the dispersion management devices includes a thermal control component configured to thermally adjust the dispersion compensation by the dispersion management device based on an output of the digital signal processor.

Systems and methods are provided for implementing an ultra-scalable high-performance computing (“HPC”) network using dense wavelength-division multiplexing (“DWDM”). The HPC system includes an interconnection of GPU devices, multiplexer / demultiplexer (“mux / demux”) devices, amplifiers, wavelength selective switches (“WSSs”), and optical circuit switches (“OCSs”). Each OCS includes a plurality of micro-electromechanical systems (“MEMS”) mirrors and a plurality of input / output (“I / O”) ports each communicatively coupled to one WSS mux / demux device one WSS. Each WSS mux / demux device is either communicatively coupled to one of the I / O ports of an OCS or one of a plurality of GPU mux / demux devices via an amplifier. Each GPU mux / demux device is communicatively coupled to a number of GPU devices, each including another number GPUs and one or more optoelectronic devices. Selectively controlling the MEMS mirrors of the OCSs and the WSS mux / demux devices of the WSSs allows connecting the GPUs in a network topology for computing a series of computations.

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

To provide a display device with a narrow border. 【Solution means】A display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit. The second layer has a demultiplexer circuit. The third layer has a display portion. Pixels are arranged in a matrix in the display portion. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit, and the output terminals of the demultiplexer circuit are electrically connected to the pixels. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the pixels. Further, the gate driver circuit and the data driver circuit are not clearly separated and have an overlapping region. Five or more gate driver circuits and data driver circuits can be provided respectively.

This invention relates to a method for fabricating a low insertion loss spatial multiplexer / demultiplexer for multi-core optical fibers, belonging to the field of multi-core optical fiber communication technology. By using single-core fibers of different core diameters at the splice points, this invention effectively improves the fault tolerance of the multiplexer's core arrangement while reducing optical signal leakage at the splice points, thereby reducing insertion loss. This allows for the multiplexing of signals from single-core fibers into multi-core fibers at the input end and the demultiplexing of signals from multi-core fibers into single-core fibers at the output end. The spatial multiplexing / demultiplexer device prepared using this method exhibits lower insertion loss compared to the traditional bundled method, and is simpler and less expensive to operate than polymer waveguide and fused taper methods. The prepared spatial multiplexer / demultiplexer is small, flexible, durable, and suitable for mass production.

The invention provides a display device and an electronic device. The display device includes: a base layer; pixels, each including a sub-pixel; a demultiplexer; a drive circuit portion; a data line connecting the demultiplexer to the sub-pixel; a data base line connecting the demultiplexer to the driving circuit portion and including a first data base line and a second data base line; a data connection line connected to the data base line and including a first data connection line having a 1-1 data connection line and a 1-2 data connection line and a second data connection line having a 2-1 data connection line and a 2-2 data connection line; a bridge layer including a first bridge layer connected to the (1-1) th data connection line and the (1-2) th data connection line, and a second bridge layer connected to the (2-1) th data connection line and the (2-2) th data connection line; and an intermediate bridge pattern layer connecting the first data base line to the first bridge layer, overlapping the second bridge layer, and having a width greater than a width of the first data base line.

The present disclosure relates to the field of optical computing technologies, and particularly to an ultrafast all-optical intelligent sensing and computing chip system and architecture. The system includes an all-optical parallel computing array chip and a demultiplexing device. The chip includes a plurality of microlenses, a plurality of resonator rings, and a bus waveguide. The microlenses are configured to obtain natural light of a first image in a target area where the microlenses are located; the plurality of resonator rings are connected to the plurality of microlens arrays, configured to obtain the light focused by the corresponding microlenses, and perform coherent combination with the light propagating in the bus waveguide to modulate the light propagating in the bus waveguide and obtain a first modulation result; the bus waveguide serially connects the plurality of resonator rings, configured to obtain incident light and propagate the incident light in the plurality of resonator rings, and combine the first modulation results to obtain an output light result; the demultiplexing device is connected to the all-optical parallel computing array chip, configured to determine a classification result of the first image based on the output light result. The present disclosure realizes parallel processing of multiple features and improves the image recognition efficiency.

Methods, systems, and devices for wireless communication are described. A wireless device may generate a first set of bits and a second set of bits based on inputting information bits and cyclic redundancy check (CRC) bits into a demultiplexer; and performing a constellation shaping operation on the first set of bits. Performing the constellation operation may include: generating a first set of coded bits based on inputting the first set of bits into a polarization encoder; generating a set of shaped bits based on the second set of bits and the transmit power parameter; and generating a set of output bits based on the first set of coded bits and the set of shaped bits. Further, the wireless device may perform an error correction encoding (ECE) operation on the set of output bits and the second set of bits to generate encoded bits; and transmitting the encoded bits.

Disclosed herein are methods and systems for routing traffic. One exemplary system includes a muxponder module deployed in an optical network, the muxponder having an optical receiver, a first and second electrical port, a demultiplexer having a built-in digital cross-connect, and a processor accessing a first calculated carrier frequency to assign traffic streams associated with a first service identification code to a first and second host lane of the first electrical port, and a second calculated carrier frequency to assign traffic streams associated with a second service identification code to a third and fourth host lane of the second electrical port, and having logic to control the digital cross-connect to route a first and a second traffic stream to the first electrical port based on the first service identification code, and a third and a fourth traffic stream to the second electrical port based on the second service identification code.

The invention relates to configurable digital-to-analog converter calibration. A digital-to-analog converter includes an impedance network and a transfer function modification circuit. The transfer function modification circuit includes a DAC and a demultiplexer. A demultiplexer may be used to selectively connect the output of the DAC to different respective nodes of the impedance network, allowing positive or negative current to be injected into the nodes and modifying the transfer function. By selectively coupling to different nodes using a demultiplexer, the nodes of the injected current may be modified after fabrication, allowing for modification of the transfer function.

The present invention discloses a mode multiplexer / demultiplexer based on a trapezoidal subwavelength grating waveguide. The main structure thereof is two trapezoidal subwavelength gratings with relatively wide bottoms facing each other. By utilizing the characteristic of the trapezoidal subwavelength grating for mode field regulation, a mode multiplexer / demultiplexer with a constant bus waveguide width is realized. At the same time, the function of extracting the fundamental mode signal in a multimode waveguide is also realized, greatly improving the flexibility of mode signal processing and avoiding the transition taper required by a conventional mode multiplexer / demultiplexer. It has good application prospects in the fields of optical mode switching, optical interconnection, optical communication, optical computing, etc.

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

The invention provides a display device and a media data processing method. A media format detector and a demultiplexer are integrated into an automatic demultiplexer module, so that a media data reading module and the automatic demultiplexer module have a one-to-one correspondence relationship, and on the basis of the correspondence relationship, format detection is not needed after the media data reading module reads the media data, so that the media data reading efficiency is improved. Media data can be directly transmitted to the automatic demultiplexer module to be analyzed and processed. The media format detector and the demultiplexer are integrated in the automatic demultiplexer module, so that the media format detector and the demultiplexer can read the media data from the shared buffer area corresponding to the automatic demultiplexer module, and therefore, in the processing process of the media data, the number of independent modules is reduced, and the processing efficiency of the media data is improved. According to the embodiment of the invention, the running memory fixedly occupied by the independent module during running can be effectively reduced, and only one media data needs to be read once and only one piece of media data needs to be cached, so that the occupation of the running memory can be effectively reduced.

An optical integrated chip (70A,70B,70C) integrated with a silicon substrate(s) includes a wavelength multiplexer / demultiplexer (72A,72B,72C), a first light guiding element (74), and a plurality of second light guiding elements (76,78). The wavelength multiplexer / demultiplexer (72A,72B,72C) has a first and a second optical coupling regions (C1,C2) opposite to each other. The first light guiding element (74) is optically coupled to the wavelength multiplexer / demultiplexer (72A,72B,72C) through the first optical coupling region (C1) thereof. The plurality of second light guiding elements (76,78) optically coupled to the wavelength multiplexer / demultiplexer (72A,72B,72C) through the second optical coupling region (C2) thereof. In addition, a high resolution low-cost integrated handheld miniature spectrometer system is also provided.

The utility model discloses a multi-combination optical signal transmission device, through integrating two or more than two 100G-QSFP28 optical modules, the device significantly improves transmission bandwidth and capacity, adapts to large-scale data processing requirements, through arranging a wave combining and demultiplexing module, optical signals are flexibly combined or demultiplexed, transmission flexibility and adaptability are enhanced, each 100G-QSFP28 optical module performs high-speed photoelectric conversion, and the transmission efficiency is improved. By arranging the master control module, intelligent management is achieved, the state of the 100G-QSFP28 optical module is monitored in real time, operation is optimized, data are reported, system operation and maintenance are assisted, a parallel processing mechanism avoids single-point faults, reliability is improved, optical signals are processed in a centralized mode, physical dependence is reduced, wiring and maintenance are simplified, and operation and maintenance cost is reduced.

A data driver circuit and a display device are discussed, which are capable of reducing peak current and improving ground bouncing by optimizing a spread time of a MUX stage based on the counted bit toggle value of the image data. The display device can include a display panel in which a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a demultiplexer are disposed; a data driver circuit that supplies a data voltage corresponding to image data to a plurality of data channels; and a controller that controls the data driver circuit and supplies the image data to the data driver circuit. The demultiplexer includes a plurality of MUX stages and controls connection between the plurality of data channels and the plurality of data lines through switching operations of the plurality of MUX stages.

The embodiment of the invention provides a test method and device, electronic equipment and a readable storage medium, and the method comprises the steps: grouping at least one to-be-controlled clock gate, and determining the number of control registers in a control chain according to the number of groups of the clock gates; inserting the control chain into the scanning chain; determining a to-be-opened target clock gating group according to a clock signal required in the test circuit; and according to the target clock gating group, inputting a scanning enabling signal to the scanning enabling end of the scanning chain, and inputting a test vector to the scanning input end of the scanning chain, so as to control the target clock gating group through the enabling signal output by the demultiplexer. According to the embodiment of the invention, by controlling each group of clock gating in groups, the test power consumption is reduced, and the test time is shortened.