88 results about "Demultiplexer" patented technology

In one embodiment, an optical transceiver includes a digital signal processor, a transmitter coupled to the digital signal processor, and a receiver coupled to the digital signal processor. The receiver is configured to receive an optical signal. The receiver includes a demultiplexer for optical demultiplexing of the optical signal into a plurality of channels, and a plurality of dispersion management devices. Each of the dispersion management devices is associated with a respective channel of the plurality of channels of the demultiplexer and is configured for dispersion compensation at the respective channel. Each of the dispersion management devices includes a thermal control component configured to thermally adjust the dispersion compensation by the dispersion management device based on an output of the digital signal processor.

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

To provide a display device with a narrow border. 【Solution means】A display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit. The second layer has a demultiplexer circuit. The third layer has a display portion. Pixels are arranged in a matrix in the display portion. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit, and the output terminals of the demultiplexer circuit are electrically connected to the pixels. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the pixels. Further, the gate driver circuit and the data driver circuit are not clearly separated and have an overlapping region. Five or more gate driver circuits and data driver circuits can be provided respectively.

The invention provides a display device and an electronic device. The display device includes: a base layer; pixels, each including a sub-pixel; a demultiplexer; a drive circuit portion; a data line connecting the demultiplexer to the sub-pixel; a data base line connecting the demultiplexer to the driving circuit portion and including a first data base line and a second data base line; a data connection line connected to the data base line and including a first data connection line having a 1-1 data connection line and a 1-2 data connection line and a second data connection line having a 2-1 data connection line and a 2-2 data connection line; a bridge layer including a first bridge layer connected to the (1-1) th data connection line and the (1-2) th data connection line, and a second bridge layer connected to the (2-1) th data connection line and the (2-2) th data connection line; and an intermediate bridge pattern layer connecting the first data base line to the first bridge layer, overlapping the second bridge layer, and having a width greater than a width of the first data base line.

Methods, systems, and devices for wireless communication are described. A wireless device may generate a first set of bits and a second set of bits based on inputting information bits and cyclic redundancy check (CRC) bits into a demultiplexer; and performing a constellation shaping operation on the first set of bits. Performing the constellation operation may include: generating a first set of coded bits based on inputting the first set of bits into a polarization encoder; generating a set of shaped bits based on the second set of bits and the transmit power parameter; and generating a set of output bits based on the first set of coded bits and the set of shaped bits. Further, the wireless device may perform an error correction encoding (ECE) operation on the set of output bits and the second set of bits to generate encoded bits; and transmitting the encoded bits.

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

The invention provides a display device and a media data processing method. A media format detector and a demultiplexer are integrated into an automatic demultiplexer module, so that a media data reading module and the automatic demultiplexer module have a one-to-one correspondence relationship, and on the basis of the correspondence relationship, format detection is not needed after the media data reading module reads the media data, so that the media data reading efficiency is improved. Media data can be directly transmitted to the automatic demultiplexer module to be analyzed and processed. The media format detector and the demultiplexer are integrated in the automatic demultiplexer module, so that the media format detector and the demultiplexer can read the media data from the shared buffer area corresponding to the automatic demultiplexer module, and therefore, in the processing process of the media data, the number of independent modules is reduced, and the processing efficiency of the media data is improved. According to the embodiment of the invention, the running memory fixedly occupied by the independent module during running can be effectively reduced, and only one media data needs to be read once and only one piece of media data needs to be cached, so that the occupation of the running memory can be effectively reduced.

A data driver circuit and a display device are discussed, which are capable of reducing peak current and improving ground bouncing by optimizing a spread time of a MUX stage based on the counted bit toggle value of the image data. The display device can include a display panel in which a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a demultiplexer are disposed; a data driver circuit that supplies a data voltage corresponding to image data to a plurality of data channels; and a controller that controls the data driver circuit and supplies the image data to the data driver circuit. The demultiplexer includes a plurality of MUX stages and controls connection between the plurality of data channels and the plurality of data lines through switching operations of the plurality of MUX stages.

The invention provides an electronic device. The electronic device comprises a plurality of electronic elements. Each of the plurality of electronic components includes a pixel circuit and a plurality of tunable circuits. A plurality of tunable circuits are coupled to the pixel circuits. The pixel circuit comprises at least one scanning transistor, a plurality of demultiplexer transistors, a plurality of bias transistors and a storage capacitor. The plurality of demultiplexer transistors are coupled to the at least one scan transistor. The plurality of bias transistors are coupled to the plurality of demultiplexer transistors. The storage capacitor is coupled to the data line through at least one scanning transistor. The number of scanning lines of the electronic device can be effectively reduced.

The application discloses a multi-channel self-interference cancellation device combined with an optical domain and a digital domain, which comprises a signal branch module a, a reference branch module b and a signal post-processing module c. The signal branch module a comprises n signal processing channels with the same structure, a wavelength division multiplexer (3), a dispersion medium (4), a wavelength division demultiplexer (5) and a multi-wavelength light source (8); each signal processing channel comprises a low-noise amplifier (1), a double-parallel Mach-Zehnder modulator (2), an optical power amplifier (6) and an optical-electricity detector (7) which are all the same. The reference branch module b comprises a low-noise amplifier (1), a double-parallel Mach-Zehnder modulator (2), a tunable laser (12), an optical splitter (9) and a multi-channel analog matching detection branch. The signal post-processing module c comprises an electric coupler (13), an analog-digital converter (14) and a digital signal processing (15). The application also discloses a multi-channel self-interference cancellation method combined with an optical domain and a digital domain. The application realizes self-interference cancellation of an array multi-channel in-band full-duplex system and beam forming of multi-channel useful signals with small array element scale and low operation cost.

A non-degenerate mode few-mode multiplexer / demultiplexer based on a four-core transmission main channel is characterized in that a transmission channel of the mode division multiplexer / demultiplexer is composed of an elliptical four-core super-mode fiber core FEC-SFC and three single-mode fiber cores, the elliptical four-core super-mode fiber core at the coordinate center serves as the transmission main channel, and the single-mode fiber cores SMF1, SMF2 and SMF3 are transmission coupling channels; the length of the transmission main channel FEC-SFC is 3.588 mm, and the lengths of the SMF1, the SMF2 and the SMF3 are respectively 3.588 mm, 1.658 mm and 1.808 mm; the mode field characteristics in the optical fiber can be changed by reasonably setting parameters such as the position, the size and the refractive index distribution of the fiber core; according to the ultra-mode fiber core, the advantages of a pure silicon dioxide fiber core, an elliptical core and an ultra-mode fiber core are fused, the mode degeneracy of LP11a / LP11b is broken, four ultra-mode multiplexing and demultiplexing of LP01, LP11a, LP11b and LP21b are achieved, the refractive index fiber core made of pure silicon dioxide is adopted, and the low-loss performance is achieved; a transmission channel with a large effective refractive index difference is adopted, and the position and the length of the transmission channel are reasonably set, so that the low-crosstalk and high-extinction-ratio performance is realized, and the low-crosstalk and high-extinction-ratio optical fiber can be used for MIMO-FREE operation.

In one embodiment, an optical transceiver includes a digital signal processor, a transmitter coupled to the digital signal processor, and a receiver coupled to the digital signal processor, a method for dispersion compensation by the optical transceiver, a computer system, and a storage medium. The receiver is configured to receive an optical signal. The receiver includes a demultiplexer for demultiplexing an optical signal into a plurality of channels and a plurality of dispersion management devices. Each dispersion management device of the plurality of dispersion management devices is associated with a respective channel of the plurality of channels of the demultiplexer and is configured for dispersion compensation at the respective channel. Each dispersion management device includes a thermal control component configured to thermally adjust a dispersion compensation of the dispersion management device based on an output of the digital signal processor.

A system may include: a first electronic device that receives service classical data and key management system classical data from a first quantum layer, and classical data from a classical data layer, a first multiplexer / demultiplexer that multiplexes the service classical data, the key management system classical data, and the classical data into multiplexed classical data, and the first circulator receives the multiplexed classical data at a first port and routes the multiplexed classical data to a fiber optic channel via a second port. A second circulator at a second electronic device receives the multiplexed classical data from the fiber optic channel on a second port, and routes the multiplexed classical data to the second multiplexer / demultiplexer on a third port, and a second multiplexer / demultiplexer demultiplexes and outputs the service classical data, the key management system classical data, and the classical data.

The present disclosure relates to central units and remote units. One example central unit includes at least one digital-to-analog converter (DAC), at least one first electro-optical converter configured to convert an analog electrical signal output by the DAC into an analog optical signal, at least one first optical processor configured to process the analog optical signal output by the first electro-optical converter, where the first optical processor includes at least one of at least one first optical filter, at least one first optical phase shifter, and at least one first optical power amplifier, a first multiplexer configured to combine analog optical signals output by the first optical processor into one analog optical signal, and a first demultiplexer configured to decompose the one analog optical signal into multiple analog optical signals at different wavelengths.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The present disclosure relates to a digital-to-analog converter comprising an impedance network and a transfer function modification circuit. The transfer function modification circuit comprises a DAC and a demultiplexer. The demultiplexer may be used to selectively connect the output of the DAC to different respective nodes of the impedance network, allowing positive or negative currents to be injected into the node and modify the transfer function. By using a demultiplexer to selectively couple to different nodes, the node into which the current is injected may be modified post-manufacture, allowing transfer function modification.

The invention discloses a display panel, a driving method thereof and a display device. The display panel includes: a plurality of sub-pixels; the data lines are electrically connected with the sub-pixels; each demultiplexer comprises n transistors, first electrodes of the n transistors in the same demultiplexer are electrically connected with the same data signal end, second electrodes of the n transistors in the same demultiplexer are electrically connected with the n data lines in a one-to-one correspondence mode, and n is an integer larger than 1; in the first time period, the conduction sequence of the n transistors in the same demultiplexer is a first sequence, in the second time period, the conduction sequence of the n transistors in the same demultiplexer is a second sequence, and the first sequence is different from the second sequence. The embodiment of the invention provides a display panel, a driving method thereof and a display device. The problem of uneven display of the display panel can be solved.

In some embodiments, a method includes receiving, at a central processing unit (CPU)-based demultiplexer of a CPU, an input video data stream; performing, at the CPU, an accelerator decoding configuration assessment of an accelerator decoding configuration of an accelerator; and based upon the accelerator decoding configuration assessment, dynamically decoding CPU-based demultiplexer output from the CPU-based demultiplexer using a CPU-based decoding unit and an accelerator-based decoding unit. In some embodiments of the method, the accelerator decoding configuration assessment includes performing an accelerator-based decoding unit hardware configuration assessment of the accelerator-based decoding unit and a CPU-based decoding unit software configuration assessment of the CPU-based decoding unit software utilized for the CPU-based decoding unit.

The application provides a quantum encryption transmission method, system and computer readable storage medium, and the method comprises the following steps: a first network management module sends configuration management information to a first encryption module; the first encryption module forwards the configuration management information to a first QKD module; the first QKD module generates a quantum state optical signal according to the configuration management information; a first multiplexer / demultiplexer transmits the quantum state optical signal to a second multiplexer / demultiplexer, so that a second QKD module measures the quantum state optical signal, generates a quantum key agreement signal according to the quantum state measurement result obtained after the measurement, and makes a second encryption module encrypt and / or sign the quantum key agreement signal; and quantum encryption transmission is realized based on the processed quantum key agreement signal. The method, system and computer readable storage medium can solve the problem that the quantum encryption transmission corresponding to the classical transmission equipment, the QKD module and the encryption module in the prior art cannot be uniformly managed, thereby causing network management and maintenance difficulties.

The invention discloses a clock data recovery circuit applied to a multi-channel array high-speed SerDes receiver. A half-rate decision feedback equalizer carries out signal recovery processing on an original analog signal input in a current period according to a first target sampling clock output from a clock network in a previous period and outputs a digital serial signal; the target sampler carries out sampling processing on the digital serial signal according to a second target sampling clock output from the clock network in the previous period and outputs serial judgment data; the demultiplexer carries out parallel processing on the digital serial signals and the serial judgment data according to a third target sampling clock output from the clock network in the previous period and outputs multiple paths of parallel signals; the clock recovery module generates a target four-phase clock according to the local clock signal and the multi-path parallel signal; and the clock network generates a first target sampling clock, a second target sampling clock and a third target sampling clock of the next period according to the target four-phase clock. The clock data recovery circuit has the advantages of low power consumption and high speed.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The invention provides a cache updating method and device based on multi-level caches, equipment and a medium, and the method comprises the steps: if target cache data matched with target business data is found in a first-level cache, determining a first cache existence duration of the target cache data based on an asynchronous cache updating strategy; if the existence duration of the first cache meets the asynchronous cache updating strategy, determining the target cache data as valid to-be-updated cache data, generating an asynchronous refreshing task for the to-be-updated cache data, and submitting the asynchronous refreshing task to a second-level cache through a first task demultiplexer; the asynchronous refreshing task is used for indicating to return the cache updating data searched in the second-level cache to the first task de-weighting device; and receiving cache updating data returned by the first task de-weighting device, and updating the to-be-updated cache data into the cache updating data in the first-level cache. By adopting the method and the device, the timeliness and the reliability of cache updating can be improved.

A computer-implemented method performed at a processing server includes receiving, from a client device, a request to connect to an application server. The method further includes identifying a targeted application server from a set of application servers. The method further includes mapping a private internet protocol (IP) address for the targeted application server to a virtual IP (VIP) address associated with one or more demultiplexers. The method further includes generating a token based on a current secret key, wherein the token includes an indication of whether the token was generated using a static secret key or a particular dynamic secret key. The method further includes transmitting the VIP address, the private IP address, and the token to the client device.

A display device in some examples can include a display panel on which a plurality of sub-pixels are arranged, a data driver configured to provide a data voltage to the plurality of sub-pixels through a plurality of data lines, and a demultiplexer connected between the data driver and the plurality of data lines. The demultiplexer is configured with a plurality of switching elements controlled by a plurality of mux control signals.

A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

This invention provides a fault location method, apparatus, electronic device, and storage medium, relating to the field of optical communication technology, for accurately determining the fault location of a semi-active wavelength division multiplexing (SDM) system. The method includes: after a service anomaly occurs, detecting whether the received optical power of the headend optical module is abnormal; if the received optical power of the headend optical module is abnormal, detecting whether the optical power of a first optical signal output from a first optical multiplexer / demultiplexer to the headend optical module is abnormal; if the optical power of the first optical signal is abnormal, detecting whether the optical power of a second optical signal output from a first serial communication interface to the first optical multiplexer / demultiplexer is abnormal; and if the optical power of the second optical signal is normal, determining that the headend equipment has failed.

A system may include: a first electronic device that receives service classical data and key management system classical data from a first quantum layer, and classical data from a classical data layer, a first multiplexer / demultiplexer that multiplexes the service classical data, the key management system classical data, and the classical data into multiplexed classical data, and the first circulator receives the multiplexed classical data at a first port and routes the multiplexed classical data to a fiber optic channel via a second port. A second circulator at a second electronic device receives the multiplexed classical data from the fiber optic channel on a second port, and routes the multiplexed classical data to the second multiplexer / demultiplexer on a third port, and a second multiplexer / demultiplexer demultiplexes and outputs the service classical data, the key management system classical data, and the classical data.

A receive extender in an integrated circuit may include: N phase-adjustment circuits that adjust phases of N receive signals from N receive antennas; and an N:1 demultiplexer that coherently combines the N receive signals into an output signal, which is provided to the transceiver chip. Moreover, a transmit extender in the integrated circuit may include: a 1:M multiplexer that coherently separates a transmit signal from the transceiver chip into M transmit signals, where N and M are non-zero integers that may be different; and M phase-adjustment circuits that adjust phases of the M transmit signals, which are provided to M transmit antennas. Note that the integrated circuit may be coupled to a second integrated circuit that phase shifts the output signal and the transmit signal based at least in part on the oscillator signal. Moreover, control signals between the integrated circuit and the second integrated circuit may be synchronized.

The application discloses a kind of high-efficient global navigation satellite system signal GNSS correlation peak calculation methods, its implementation steps include: receiving GNSS satellite signal data stream;Code NCO module is generated by code clock and phase information, and the local pseudo code is generated by driving generation, and according to this, selection signal is generated;Corresponding pseudo code is selected according to selection signal using multiplexer, and after being related with input signal, the accumulated value is obtained;The value is stored in corresponding register temporary storage by demultiplexer;Finally, the stored correlation sequence is convolved with preset matching waveform by convolution module, and the final correlation peak is generated.The method greatly reduces the required (2M+1) ×S times multiplication and addition operation of tradition to S times multiplication and addition and M square times convolution.It saves hardware resources while supporting BPSK, BOC and other multiple signals and multipath suppression scenarios, and considers high precision and strong adaptability, and is suitable for lightweight GNSS receiver design.