1247 results about "Gate driver" patented technology

A control system for an AC-DC converter includes a mixed-signal power controller and first and second gate drivers. The controller has a digital module and an analog module. The analog module has a current sensor generating a current sense voltage based on a sensed switch current. The digital module has a DC voltage sensor generating a DC sense voltage based on a DC bus voltage, and an AC voltage sensor generating an AC sense voltage and a binary polarity signal based on the AC voltage. The digital module induces the first gate driver to output first and second control signals for controlling a high-side switch and a low-side switch of a current shaping half-bridge based on first and second clock signals and the comparator voltage, such that an inductor current flowing through an inductor is proportional to a current command value.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of clock signal lines and cascaded N driving units, and the nth-level driving unit further comprises a pre-charging module used for pre-charging the nth-level driving unit under the action of a level transmission signal of the (n-i) th-level driving unit, the driving control node is charged through a first driving signal of the (n-i) th-stage driving unit; the output module is used for outputting a first driving signal through the first driving output end and outputting a second driving signal through the second driving output end under the action of the control voltage on the driving control node; according to the gate driving circuit, the number of the driving units can be reduced by half on the premise that the number of the output signals is the same through the mode that the first-stage driving unit outputs the two driving signals, so that the number of transistors in the gate driving circuit is greatly reduced, a narrow-frame product can be achieved, meanwhile, the cost of a panel is reduced, and the stability of the panel is improved.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

The utility model provides a high-voltage pulse generating device and a test system. The high-voltage pulse generating device comprises a main control unit, a driving circuit, a pulse control circuit with a wide bandgap semiconductor power device, and an output circuit, the first end of the main control unit is coupled with the first end of the driving circuit, the second end of the driving circuit is coupled with the first end of the pulse control circuit, and the second end of the pulse control circuit is coupled with the output circuit; the main control unit is configured to generate two paths of first PWM (Pulse Width Modulation) signals with dead time control; the two paths of first PWM signals are sent to the driving circuit; and the driving circuit is configured to process the first PWM signal and then drive the pulse control circuit, so that the output circuit generates a high-voltage pulse signal. According to the utility model, the structure is simple, the cost can be greatly reduced, the output pulse speed can be flexibly set, and the CMTI test requirements of different isolated gate drivers can be met.

Embodiments relate to a level shifter including a first circuit unit configured to output a start signal, a reset signal, and a node charge signal to a gate driver in response to a start control signal and a node charge control signal that are input from a timing controller, a second circuit unit configured to output an output erase signal and a clock shift stop signal in response to the start signal and the reset signal, and a third circuit unit configured to generate a clock signal based on a clock control signal input from the timing controller and output the generated clock signal to the gate driver in response to the output erase signal and the clock shift stop signal that are output from the second circuit unit, a display device including the same, and a method of driving the display device.

In one aspect of the disclosure, a variable-current gate driver includes a plurality of inputs for receiving pulse-width-modulation (PWM) control signals transmitted from a processing system. Current sources controlled based on the pulse-width modulation (PWM) signals are coupled to respective gates of at least two transistors of a hybrid switch in the power module (PM) including different semiconductor technologies. The current sources are coupled respectively to at least one other non-gate terminal of the transistors. The current sources provide the slew rate control of the PM using variable current values to compensate for differences in the at least two semiconductor technologies in real-time to reduce switching losses and maximize efficiency.

A light-emitting diode (LED) control unit includes: a pulse generator configured to generate a pulse signal; a T-filter configured to convert the pulse signal into a triangular wave signal; a first gate driver configured to receive the triangular wave signal and output a first gate control signal; a second gate driver configured to receive the first gate control signal and output a second gate control signal; a first switch configured to turn on a first LED string corresponding to a first color temperature based on the first gate control signal; a second switch configured to turn on a second LED string corresponding to a second color temperature based on the second gate control signal; and a power supply circuit configured to supply a power supply voltage to the pulse generator, the first gate driver, and the second gate driver by stepping down an operating voltage of the LED driver.

Provided are a gate driver and a display device including the same. The display device may include a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel, a gate driver including a scan signal generation circuit configured to supply a scan signal to the display panel and a light-emitting signal generation circuit configured to supply a light-emitting signal to the display panel, and a clear signal line connected to the gate driver to deliver a clear signal in an alternating current form including a positive voltage and a negative voltage, wherein the gate driver initializes at least one of nodes of the scan signal generation circuit and nodes of the light-emitting signal generation circuit based on the clear signal.

The invention discloses a display driving circuit and a display device.The display driving circuit comprises a repairing unit, the repairing unit is connected with a clock signal line in series, a time schedule controller is connected with a grid driving circuit through the repairing unit and the clock signal line, the repairing unit comprises a first MOS transistor and a second MOS transistor, the first MOS transistor is an N-type MOS transistor, and the second MOS transistor is an N-type MOS transistor. The input end and the control end of the first MOS tube are electrically connected with the time schedule controller, and the output end of the first MOS tube is electrically connected with the gate drive circuit; the second MOS tube is a P-type MOS tube, the input end and the control end of the second MOS tube are both electrically connected with the time schedule controller, and the output end of the second MOS tube is electrically connected with the gate drive circuit. Through the design, the display problem caused by waveform distortion of the clock signal after the row overdrive technology is adopted is avoided.

A display device includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a data voltage to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate the common gate signal.

A gate driver includes a plurality of stages. Each of the stages comprises a control circuit configured to receive an input signal in response to a first clock signal and control a voltage of a control node and a voltage of an inverted control node based on the input signal, a carry output circuit configured to output a high gate voltage or a second clock signal as a carry signal in response to the voltage of the control node and the voltage of the inverted control node, and a gate output circuit configured to output the high gate voltage or a gate clock signal as a gate signal in response to the voltage of the control node and the voltage of the inverted control node.

A display device is disclosed that includes a display panel including pixels including first pixels having a first viewing angle and disposed in a first pixel row and second pixels having a second viewing angle and disposed in a second pixel row. The display panel includes a first display area where an image is displayed through the first pixels, and a second display area where an image is displayed through the second pixels. A gate driver provides gate voltages to a first gate line connected to the first pixel row and a second gate line connected to the second pixel row. A data driver provides data voltages to the pixels. A driving controller controls the gate driver and the data driver, and compensates for a grayscale value of at least one first pixel among the first pixels of the second display area.

The invention relates to power semiconductor device on-line monitoring and power electronic system control, in particular to a SiC MOSFET conduction current extraction circuit and method, high-frequency oscillation interference is effectively suppressed through a second-order passive RC filter circuit, a measurement error less than or equal to 1.5% is realized within a current range of 50A-300A in combination with an accurate mathematical model established by a depth symbol optimization algorithm, and the measurement accuracy is improved. The requirement of the intelligent gate driver on high-precision current feedback is met, and the measurement precision is remarkably improved; the pulse width direct analysis technology is adopted, a traditional active integrator and a digital decoding link are omitted, the system response delay is smaller than or equal to 500 ns, microsecond-level over-current protection can be supported, the response speed and the real-time performance are optimized, and the system safety in a high-frequency application scene is remarkably improved.

A gate driver includes a plurality of stages. Each of the plurality of stages includes a first transistor which transmits an input signal to a control node, a second transistor including a gate connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal connected to an output node from which a gate signal is output, a third transistor including a gate connected to the control node, a first terminal which receives a low gate voltage or a clock signal, and a second terminal connected to the output node, and a fourth transistor, which is an NMOS transistor, connected between a terminal of the first transistor and the gate of the sixth transistor, including a gate which receives a global signal having the high gate voltage in an address scan period and the low gate voltage in a self-scan period.

In one aspect, a display device includes a plurality of stage circuits configured to output gate signals to gate lines in response to a gate clock signal. Each stage circuit includes an output unit configured to output a first level voltage or a second level voltage to one of the gate lines according to a corresponding voltage at a Q node and a QB node; an input unit configured to control a voltage at a Q1 node according to a gate start signal or a carry signal output from a previous stage circuit in response to the gate clock signal; a Q node controller configured to control the voltage at the Q node according to the voltage at the Q1 node; and a QB node controller configured to control the voltage at the QB node according to the voltage at the Q1 node and the voltage at the Q node.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

A gate driver system for a multi-phase inverter includes a gate controller, a gate driver circuit, and a hybrid switch power module integrated into a phase leg of the multi-phase inverter. The hybrid switch power module includes a first semiconductor switch connected in parallel with a second semiconductor switch. The first semiconductor switch has first conduction characteristics, while the second semiconductor switch has second performance characteristics. The gate driver circuit includes a gate driver, a first variable resistance circuit, and a second variable resistance circuit. The first variable resistance circuit is powered by a first low-voltage DC power bus, while the second variable resistance circuit is powered by a second low-voltage DC power bus.The first variable resistance circuit is connected to a first gate of the first semiconductor switch, while the second variable resistance circuit is connected to a second gate of the second semiconductor switch.

An integrated circuit is provided for driving the gate of a GaN power switch transistor in a switching power converter. During a first portion of an on-time period for the GaN power switch transistor, the integrated circuit charges the gate through a relatively high pull-up resistance. During a second portion of the on-time period, the integrated circuit charges the gate through a relatively low pull-up resistance. During a first portion of an off-time period for the GaN power switch transistor, the integrated circuit discharges the gate through a relatively low pull-down resistance and then discharges the gate through a relatively high pull-down resistance in response a voltage of the gate falling below a threshold voltage.

A gate driver and a vehicle display are disclosed herein. The gate driver comprises a shift register module and a selection module. The shift register module includes first to fourth dummy shift register circuits and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal and one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

A display apparatus includes a display panel including first and second display areas, a first gate driver configured to output a first gate signal to the first display area, a first data driver configured to output a first data voltage to the first display area, a first driving controller configured to control the first gate driver and the first data driver, a second gate driver configured to output a second gate signal to the second display area, a second data driver configured to output a second data voltage to the second display area, and a second driving controller configured to control the second gate driver and the second data driver, wherein at least one of the first or second driving controllers is configured to compare input data and sensed data, and to generate a shutdown signal based on a comparison result of the input data and the sensed data.

A display device includes a display panel including a sub-pixel, a gate driver which provides a gate signal to the sub-pixel, a data driver which provides a data voltage to the sub-pixel, a driving voltage generator which provides a gamma reference voltage including a black data voltage to the data driver, and a driving controller which determines an offset voltage of the black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature.

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

Example implementations include a method, apparatus and integrated circuit (IC) for active pre-charging a battery system. The IC may include a pre-charging controller configured to manage pre-charging of a capacitive load. The IC may include a programmable current control module configured to maintain constant charging current based on one or more parameters from the pre-charging controller. The IC may include a smart gate driver configured to drive one or more high voltage field-effect transistors (FETs) based on one or more control signals from the pre-charging controller. The IC may include a boundary mode controller configured to configure inductor current to maintain constant charging current. The IC may include a safety monitoring module configured to detect an overvoltage or undervoltage state based on system voltage monitoring. The IC may include a timing module configured to indicate a charge completion following a defined charge time.

A display apparatus includes a substrate including a display area, a camera hole, and a non-display area, a light-emitting element disposed in the display area, a gate driver disposed in the non-display area, and an initialization signal line disposed in the display area, wherein the display area includes left and right display areas with respect to the camera hole, and an array pixel area, and the initialization signal line is disposed in each of the left display area and the right display area.

A gate driver circuit includes a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on-state and an off-state with an adaptive dead time; a capacitor cross-coupled to the high-side region and the low-side region; a logic circuit configured to use the capacitor to detect a voltage transient of the power switch based on a first crossing of a threshold, and detect an end of the voltage transient based on a second crossing of the threshold; and an active-passive discrimination circuit configured to indicate whether the voltage transient is active or passive. The logic circuit is configured to regulate the adaptive dead time based on the second crossing of the threshold and based on the voltage transient being passive.

A system for prognosis and control of a power module includes a gate driver circuit and a controller circuit. The gate driver circuit drives a target gate node of a target power transistor in response to a pulse width modulation signal, measures a target gate voltage, switches a desaturation signal in response to the target power transistor switching between an off state and an on state, measures a target transistor voltage, and measures a target transistor current. The controller circuit modulates the pulse width modulation signal to increase the target gate voltage, determines a target threshold voltage as the target gate voltage in response to the desaturation signal switching states, determines a target on-resistance based on the target transistor voltage and the target transistor current, and controls the target power transistor based on the target threshold voltage and the target on-resistance.

A gate driver includes a plurality of stages. A stage of the stages includes a pull-up circuit which applies a high voltage to an output node which outputs a gate signal, a pull-down circuit which applies a low voltage lower than the high voltage to the output node, a gate signal control circuit which controls the pull-up circuit and the pull-down circuit, and a stabilization transistor connected to the pull-down circuit. The stabilization transistor is turned off when the gate signal has the low voltage.