1713 results about "Gate driver" patented technology

A display apparatus includes a display panel, a driving controller, a gate driver, an emission driver and a data driver. The display panel includes a pixel including a driving switching element and a light emitting element. The driving controller is configured to determine a driving frequency varied according to input image data or a driving mode. The gate driver is configured to output a gate signal and a bias control signal to the pixel. The emission driver is configured to output an emission signal to the pixel. The data driver is configured to output a data voltage to the pixel. The bias control signal to apply a bias voltage to the driving switching element has a first width in a writing frame and a second width different from the first width in a holding frame.

A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode connected to a second node, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode connected to the second node, an electrode connected to the fifth node and another electrode receiving a power.

A gate driver may include signal transfer circuits, each signal transfer circuit receiving a carry signal from its preceding signal transfer circuit, and each signal transfer circuit operating dependently of its preceding signal transfer circuit. Each signal transfer circuit may include: a first output circuit for receiving the carry signal from its preceding signal transfer circuit and outputting a first gate signal according to voltages of first-1 and first-2 control nodes; a second output circuit for outputting a second gate signal according to voltages of second-1 and second-2 control nodes, in response to these second control nodes being connected to the first-2 and first-1 control nodes, respectively; and a third output circuit for outputting a third gate signal according to voltages of third-1 and third-2 control nodes, in response to these third control nodes being connected to the first-2 and first-1 control nodes, respectively. A display device is also disclosed.

Power switch device includes a wide-bandgap semiconductor switch, and a gate driver. The gate driver includes a driver circuit and a diagnostic circuit. The driver circuit is configured to provide a driver signal to control the wide-bandgap semiconductor switch. The diagnostic circuit is configured to sense an electrical characteristic of the wide-bandgap semiconductor switch, and perform a diagnostic test for the wide-bandgap semiconductor switch in response to the electrical characteristic of the wide-bandgap semiconductor switch.

A control system for an AC-DC converter includes a mixed-signal power controller and first and second gate drivers. The controller has a digital module and an analog module. The analog module has a current sensor generating a current sense voltage based on a sensed switch current. The digital module has a DC voltage sensor generating a DC sense voltage based on a DC bus voltage, and an AC voltage sensor generating an AC sense voltage and a binary polarity signal based on the AC voltage. The digital module induces the first gate driver to output first and second control signals for controlling a high-side switch and a low-side switch of a current shaping half-bridge based on first and second clock signals and the comparator voltage, such that an inductor current flowing through an inductor is proportional to a current command value.

A variable slew rate gate drive system for powering an electric machine. The system may include a gate driver operable for controlling each of a plurality of hybrid switch power modules between opened and closed states to facilitate powering the electric machine. The gate driver may be operable for selecting slew rates and controlling ON and OFF states of first and second semiconductor switches included as part of each power module to optimize powering of the electric machine by varying the slew rates as a function of performance characteristics of the first and second semiconductor switches.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

A display apparatus, a pixel circuit and a controlling method of pixel circuit are disclosed. The display apparatus includes a display panel with a plurality of data lines, a plurality of gate lines, and a plurality of pixels disposed thereon, the display panel being configured to operate in a display mode for displaying an image and a sensing mode for sensing degradation of the pixels, a gate driver configured to supply a scan signal and an emission control signal to the plurality of gate lines, a data driver configured to supply a data signal to the plurality of data lines, a power supply configured to apply an initialization voltage to the pixels in the sensing mode, and a sensing unit configure to sense degradation of the pixels in the sensing mode.

An electronic device includes a display and a sensor underneath the display. The display has a full pixel density region and a reduced pixel density region. Compared to pixels in the full pixel density region, pixels in the reduced pixel density region can be controlled using overdriven power supply voltages, overdriven scan control signals, different initialization and reset voltages, and can include capacitors and transistors with different physical and electrical characteristics. Gate drivers provide scan signals to pixels in the full pixel density region, whereas overdrive buffers provide overdrive scan signals to pixels in the reduced pixel density region. The pixels in the full pixel density region and the pixels in the reduced pixel density region can be controlled using different black level or gamma settings for each color channel and can be adjusted physically to match luminance, color, as well as to mitigate differences in temperature and aging impact.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of clock signal lines and cascaded N driving units, and the nth-level driving unit further comprises a pre-charging module used for pre-charging the nth-level driving unit under the action of a level transmission signal of the (n-i) th-level driving unit, the driving control node is charged through a first driving signal of the (n-i) th-stage driving unit; the output module is used for outputting a first driving signal through the first driving output end and outputting a second driving signal through the second driving output end under the action of the control voltage on the driving control node; according to the gate driving circuit, the number of the driving units can be reduced by half on the premise that the number of the output signals is the same through the mode that the first-stage driving unit outputs the two driving signals, so that the number of transistors in the gate driving circuit is greatly reduced, a narrow-frame product can be achieved, meanwhile, the cost of a panel is reduced, and the stability of the panel is improved.

The invention discloses a power device driver and a parameter correction method thereof, which are applied to the technical field of power device driving, and are characterized in that a data acquisition module acquires grid voltage and peak current of an IGBT (Insulated Gate Bipolar Translator) in the working process of the IGBT to obtain sampling data; the digital isolation chip realizes electrical isolation among the data acquisition module, the MCU and the grid voltage regulation module; the MCU calibrates the real-time junction temperature data based on the sampling data by using a preset junction temperature calibration formula and outputs calibrated junction temperature data; the gate driving chip outputs a gate voltage capable of driving the IGBT according to the control signal; the second-order short-circuit protection module sends an abnormal signal to the MCU when the IGBT is short-circuited, so that the MCU sends a grid voltage regulation trigger signal to the grid voltage regulation module; the grid voltage adjusting module responds to the grid voltage adjusting trigger signal and controls itself to reduce the grid voltage. Based on the power device driver and the parameter correction method thereof provided by the invention, the junction temperature monitoring precision and reliability are improved.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

The utility model provides a high-voltage pulse generating device and a test system. The high-voltage pulse generating device comprises a main control unit, a driving circuit, a pulse control circuit with a wide bandgap semiconductor power device, and an output circuit, the first end of the main control unit is coupled with the first end of the driving circuit, the second end of the driving circuit is coupled with the first end of the pulse control circuit, and the second end of the pulse control circuit is coupled with the output circuit; the main control unit is configured to generate two paths of first PWM (Pulse Width Modulation) signals with dead time control; the two paths of first PWM signals are sent to the driving circuit; and the driving circuit is configured to process the first PWM signal and then drive the pulse control circuit, so that the output circuit generates a high-voltage pulse signal. According to the utility model, the structure is simple, the cost can be greatly reduced, the output pulse speed can be flexibly set, and the CMTI test requirements of different isolated gate drivers can be met.

Embodiments relate to a level shifter including a first circuit unit configured to output a start signal, a reset signal, and a node charge signal to a gate driver in response to a start control signal and a node charge control signal that are input from a timing controller, a second circuit unit configured to output an output erase signal and a clock shift stop signal in response to the start signal and the reset signal, and a third circuit unit configured to generate a clock signal based on a clock control signal input from the timing controller and output the generated clock signal to the gate driver in response to the output erase signal and the clock shift stop signal that are output from the second circuit unit, a display device including the same, and a method of driving the display device.

A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

In one aspect of the disclosure, a variable-current gate driver includes a plurality of inputs for receiving pulse-width-modulation (PWM) control signals transmitted from a processing system. Current sources controlled based on the pulse-width modulation (PWM) signals are coupled to respective gates of at least two transistors of a hybrid switch in the power module (PM) including different semiconductor technologies. The current sources are coupled respectively to at least one other non-gate terminal of the transistors. The current sources provide the slew rate control of the PM using variable current values to compensate for differences in the at least two semiconductor technologies in real-time to reduce switching losses and maximize efficiency.

Power tool devices described herein include a motor, an actuator configured to be actuated by a user, a plurality of power switching elements configured to drive the motor, a gate driver coupled to the plurality of power switching elements and configured to control the plurality of power switching elements, a first printed circuit board (PCB), an antenna, and a combined chip. The combined chip is located on the first PCB and is coupled to the actuator, the antenna, and the gate driver. The combined chip includes a memory and an electronic processor configured to determine that the actuator has been actuated, and provide, in response to determining that the actuator has been actuated, a signal to the gate driver, control the signal based on the motor position information, wirelessly transmit power tool device information to an external device, and wirelessly receive configuration information from the external device via the antenna.

A gate driver according to an embodiment of the present disclosure may include a plurality of dependently connected stages; and at least one of gate incoming circuits configured to selectively output one of a first start pulse corresponding to a high-frequency operation and a second start pulse corresponding to a low-frequency operation, wherein at least one of the plurality of stages are connected to the gate incoming circuit and receive one of the first start pulse and the second start pulse outputted by the gate incoming circuit.

The present specification discloses a gate driver, a display device including the same, and a method of driving the display device. When a gate-on voltage of a Jth clock signal differs from a gate-on voltage of the first clock signal, the gate driver applies a compensation gate-on voltage that is a gate-on voltage at a changed voltage level to a gate-on voltage node. The display device includes a sensing unit for sensing a clock signal, and a compensation unit for applying the compensation gate-on voltage to the gate driver from the sensed clock signal. According to the present specification, a gate-source voltage of a transistor disposed on an output unit may be maintained at a previous voltage. In addition, it is possible to prevent driving failures caused by a load received by the clock signal supplied to a stage disposed relatively far away.

A gate driver including a plurality of stages. Each of the plurality of stages includes a first masking controlling circuit including a control circuit, a carry output circuit, a first enable node controlling circuit, a first masking circuit, a first gate output circuit, and a second masking controlling circuit including a second enable node controlling circuit, a second masking circuit and a second gate output circuit. The first masking controlling circuit and the second masking controlling circuit shares the control circuit and the carry output circuit.

A display device includes a display area including light emitting elements in a first pixel row, pixel circuits in a first circuit row and electrically connected to the first pixel row, light emitting elements in a second pixel row between the first pixel row and the first circuit row, pixel circuits in a second circuit row and electrically connected to the second pixel row, and a gate driver including a first stage disposed between the pixel circuits of the first circuit row and a second stage disposed between the pixel circuits of the second circuit row. A distance between adjacent pixel circuits with the first stage between the adjacent pixel circuits in the first circuit row is greater than a distance between other pixel circuits of the first circuit row.

A light-emitting diode (LED) control unit includes: a pulse generator configured to generate a pulse signal; a T-filter configured to convert the pulse signal into a triangular wave signal; a first gate driver configured to receive the triangular wave signal and output a first gate control signal; a second gate driver configured to receive the first gate control signal and output a second gate control signal; a first switch configured to turn on a first LED string corresponding to a first color temperature based on the first gate control signal; a second switch configured to turn on a second LED string corresponding to a second color temperature based on the second gate control signal; and a power supply circuit configured to supply a power supply voltage to the pulse generator, the first gate driver, and the second gate driver by stepping down an operating voltage of the LED driver.

A gate driver has a turn-on circuit and a turn-off circuit. The turn-on circuit pulls up a gate terminal of a wide bandgap (WBG) semiconductor transistor and turns on the WBG semiconductor transistor in response to a first status of an on-off control signal. The turn-off circuit pulls down the gate terminal of the WBG semiconductor transistor and turns off the WBG semiconductor transistor in response to a second status of the on-off control signal. When the on-off control signal transits to the first status, the turn-on circuit drives the gate terminal of the WBG semiconductor transistor at a first constant driving current, and later switches to a second constant driving current. The second constant driving current is lower than the first constant driving current.

A display device includes a display panel having a plurality of pixels connected to gate lines and data lines, and a plurality of fingerprint sensors connected to sensing lines and read-out lines. A gate driver provides gate signals to the gate lines and provides sensing signals to the sensing lines. The gate driver includes a first gate signal supply module providing a first gate signal to a first gate line among the gate lines. A first switching element is turned on by a reset enable signal to connect the first gate line and a first sensing line among the sensing lines.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k-1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

Disclosed is a device that decouples switching speed and gate delay time using an improved voltage-source gate driver. A shunt capacitor and a shunt resistor are connected in series to parallel across gate resistors of a voltage-source gate driver. The shunt capacitor and shunt resistor allow the gate delay and switching speed effect of the gate resistors to be decoupled. The shunt capacitor provides an initial high charge voltage and discharge gate current to reduce gate delay time. The shunt resistor modifies the effective gate resistance, which affects the gate current and the resulting switching speed. Shunt capacitor and shunt resistor values are determined to achieve the desired switching speed control with minimum gate delay time. When multiple power devices are paralleled, a common gate resistor, a shunt resistor and a capacitor combination is used. Each power device is also provided a respective split-gate resistor.

An isolated gate driver has: a register that stores the adjustment data read from a non-volatile memory; a gate driving circuit that drives the gate of a switching element with a characteristic set based on a value stored in the register; a fault detector that performs fault detection for other than the non-volatile memory; an error detection-correction circuit that performs error detection and error correction on the adjustment data written to the non-volatile memory; a first external terminal for output of the result of fault detection; a second external terminal for output of the result of error detection; and a fault controller that, if a one-bit error is detected in the adjustment data, brings the second external terminal into an error-indicating output state and continues with normal operation of the gate driving circuit and, if a two-or-more-bit error is detected in the adjustment data, forcibly stops the gate driving circuit.

An electronic device such as a head-mounted device may have displays. The display may have regions of lower and higher resolution to reduce data bandwidth and power consumption for the display while preserving satisfactory image quality. Data lines may be shared by lower and higher resolution portions of a display or different portions of a display with different resolutions may be supplied with different numbers of data lines. Data line length may be varied in transition regions between lower resolution and higher resolution portions of a display to reduce visible discontinuities between the lower and higher resolution portions. The lower and higher resolution portions of the display may be dynamically adjusted using dynamically adjustable gate driver circuitry and dynamically adjustable data line driver circuitry.