2341 results about "Gate driver" patented technology

A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a mix of silicon transistors, one or more semiconducting oxide transistors, and one or more capacitors. The semiconducting oxide transistors can each have a back gate terminal shorted to one of its source-drain terminals, shorted to its front gate terminal, or configured to receive a bias voltage. Configured in this way, the gate driver circuit can exhibit less threshold voltage drift and thus improved device reliability over time.

The invention relates to the technical field of gallium nitride gate drivers, and discloses a design method and system of a gallium nitride gate driver, and the method comprises the steps: carrying out the working signal collection of the gallium nitride gate driver, obtaining original waveform sampling data, and building a signal integrity model under the action of electromagnetic interference; separating the original waveform sampling data into an effective driving signal, a low-frequency interference signal and a high-frequency noise signal, and extracting characteristic parameters to obtain a signal characteristic parameter set; switching time and circuit power consumption are set as optimization variables, constraint conditions are set according to the signal integrity model, and an optimization objective function is obtained; performing online identification and optimization calculation on the driving parameters to obtain a driving control parameter sequence; according to the method, the adaptive capacity of the driver to the change of the working condition is improved, and meanwhile, the stability and the reliability of the driving waveform are ensured.

A display apparatus includes a display panel, a driving controller, a gate driver, an emission driver and a data driver. The display panel includes a pixel including a driving switching element and a light emitting element. The driving controller is configured to determine a driving frequency varied according to input image data or a driving mode. The gate driver is configured to output a gate signal and a bias control signal to the pixel. The emission driver is configured to output an emission signal to the pixel. The data driver is configured to output a data voltage to the pixel. The bias control signal to apply a bias voltage to the driving switching element has a first width in a writing frame and a second width different from the first width in a holding frame.

The invention relates to a load matching optimization method of a multi-channel gate driver and related equipment thereof. The method comprises the following steps of: acquiring grid current, grid voltage and switching frequency of the multi-channel parallel grid driver to obtain driver load operation data; performing region division processing on the operation space to obtain a safe operation region and a transition region; inputting a first adaptive prediction model for feature extraction to obtain a load balancing prediction result; parallel optimization calculation is carried out on the control strategy to obtain each driving channel control parameter, and each driving channel control parameter comprises a grid driving voltage regulating variable and a driving time sequence regulating variable; performing real-time adjustment on each driving channel control parameter to obtain a load balance adjustment instruction; and performing performance index evaluation calculation to obtain a performance optimization parameter, and updating the first adaptive prediction model to obtain a second adaptive prediction model. According to the invention, through cooperative control of voltage regulation and time sequence compensation, dynamic balance of each channel load is realized.

A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.

A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode connected to a second node, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode connected to the second node, an electrode connected to the fifth node and another electrode receiving a power.

A display panel and a display device including the same are disclosed. The display panel includes a pixel array on which an input image is displayed; and a bezel area outside the pixel array. The pixel array includes a pixel circuit area in which a plurality of pixel circuits connected to data lines, gate lines, and power lines are disposed; and a gate driving circuit area in which a gate driver supplying a gate signal to the gate line is disposed. A light emitting area of a light emitting element driven by the pixel circuits is disposed in the pixel circuit area and the gate driving circuit area. The power line is disposed below an anode electrode of the light emitting element.

A gate driver may include signal transfer circuits, each signal transfer circuit receiving a carry signal from its preceding signal transfer circuit, and each signal transfer circuit operating dependently of its preceding signal transfer circuit. Each signal transfer circuit may include: a first output circuit for receiving the carry signal from its preceding signal transfer circuit and outputting a first gate signal according to voltages of first-1 and first-2 control nodes; a second output circuit for outputting a second gate signal according to voltages of second-1 and second-2 control nodes, in response to these second control nodes being connected to the first-2 and first-1 control nodes, respectively; and a third output circuit for outputting a third gate signal according to voltages of third-1 and third-2 control nodes, in response to these third control nodes being connected to the first-2 and first-1 control nodes, respectively. A display device is also disclosed.

Power switch device includes a wide-bandgap semiconductor switch, and a gate driver. The gate driver includes a driver circuit and a diagnostic circuit. The driver circuit is configured to provide a driver signal to control the wide-bandgap semiconductor switch. The diagnostic circuit is configured to sense an electrical characteristic of the wide-bandgap semiconductor switch, and perform a diagnostic test for the wide-bandgap semiconductor switch in response to the electrical characteristic of the wide-bandgap semiconductor switch.

A gate signal masking circuit includes: a connection transistor connecting a first control node and a first transistor based on a connection signal; the first transistor connected to a masking node, the connection transistor and a second control node; a second transistor including a control electrode receiving a carry signal, a first electrode receiving a masking signal and a second electrode connected to a first node; a third transistor including a control electrode receiving an enable signal, a first electrode connected to the first node and a second electrode connected to the masking node; a fourth transistor including a control electrode receiving a second enable signal, a first electrode connected to the masking node and a second electrode connected to a second node; a fifth transistor including a control electrode receiving the carry signal, a first electrode connected to the second node and a second electrode receiving a power voltage.

A control system for an AC-DC converter includes a mixed-signal power controller and first and second gate drivers. The controller has a digital module and an analog module. The analog module has a current sensor generating a current sense voltage based on a sensed switch current. The digital module has a DC voltage sensor generating a DC sense voltage based on a DC bus voltage, and an AC voltage sensor generating an AC sense voltage and a binary polarity signal based on the AC voltage. The digital module induces the first gate driver to output first and second control signals for controlling a high-side switch and a low-side switch of a current shaping half-bridge based on first and second clock signals and the comparator voltage, such that an inductor current flowing through an inductor is proportional to a current command value.

A display device may include a display panel including a plurality of pixels; and a data driver circuit configured to supply a data signal to the plurality of the pixels through data lines. A gate driver circuit, configured to supply a gate signal to the plurality of the pixels through gate lines, is disposed in the display panel. The display panel includes a driving layer including a gate area having the gate driver circuit; and a pixel circuit layer including an active area having a pixel area in which each of the plurality of pixels is disposed and a non-active area around the active area. The pixel circuit layer includes a light emitting diode, a clock line configured to supply a clock signal to the gate driver circuit, and a shielding pattern between the light emitting diode and the clock line.

A variable slew rate gate drive system for powering an electric machine. The system may include a gate driver operable for controlling each of a plurality of hybrid switch power modules between opened and closed states to facilitate powering the electric machine. The gate driver may be operable for selecting slew rates and controlling ON and OFF states of first and second semiconductor switches included as part of each power module to optimize powering of the electric machine by varying the slew rates as a function of performance characteristics of the first and second semiconductor switches.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

The invention provides a display screen suitable for cholesterol liquid crystal and a driving method. The display screen comprises a time schedule controller, a source driver, a grid driver and a common voltage generating circuit. The time schedule controller obtains image data and output setting, and outputs a source electrode control signal, a grid electrode control signal and a common voltage control signal; the source electrode driver outputs a source electrode driving signal according to the source electrode control signal, the source electrode driving signal comprises a multi-frame first alternating current signal and a multi-frame first direct current signal, and then output is paused until a next image is displayed; the gate driver outputs a gate driving signal according to the gate control signal; the common voltage generation circuit outputs a common voltage signal according to the common voltage control signal, and the common voltage signal comprises a multi-frame second AC signal and a multi-frame second DC signal; the second AC signal and the first AC signal are synchronous and opposite in polarity, and the second DC signal and the first DC signal are synchronous. The image display requirement can be met, and power consumption is reduced.

A turn-on circuit is configured to supply a current as a source to the gate of a high-side transistor. A first current source supplies an output current that is switchable between a first current amount and a second current amount that is smaller than the first current amount. A first switch is coupled between a first output node of a first current mirror circuit and the gate of the high-side transistor. A second current source generates a second current. A second switch is coupled between a first output node of a second current mirror circuit and the gate of the high-side transistor.

A display apparatus, a pixel circuit and a controlling method of pixel circuit are disclosed. The display apparatus includes a display panel with a plurality of data lines, a plurality of gate lines, and a plurality of pixels disposed thereon, the display panel being configured to operate in a display mode for displaying an image and a sensing mode for sensing degradation of the pixels, a gate driver configured to supply a scan signal and an emission control signal to the plurality of gate lines, a data driver configured to supply a data signal to the plurality of data lines, a power supply configured to apply an initialization voltage to the pixels in the sensing mode, and a sensing unit configure to sense degradation of the pixels in the sensing mode.

The invention relates to the technical field of drivers, and discloses a low-delay control method, system, equipment and medium for a gallium nitride gate driver, and the method comprises the steps: carrying out the feature extraction and nonlinear mapping processing of the driving voltage, gate charge and switching time sequence parameters of the gate driver, and obtaining time domain characteristic data and a parameter distribution model; duty ratio modulation function calculation is carried out to obtain a rising edge duty ratio parameter and a falling edge duty ratio parameter; performing dynamic planning solution on the state transition equation to obtain an optimal control sequence; performing driving control on a gate driver according to the optimal control sequence, and acquiring running state data through a plurality of monitoring points to obtain an actual driving delay value and an actual switching loss value; the Gaussian process model is constructed based on the actual driving delay value and the actual switching loss value, the updated control parameters are obtained through iterative sampling calculation, the optimal control sequence considering multivariable constraints is obtained, and the accuracy of driving control is remarkably improved.

An electronic device includes a display and a sensor underneath the display. The display has a full pixel density region and a reduced pixel density region. Compared to pixels in the full pixel density region, pixels in the reduced pixel density region can be controlled using overdriven power supply voltages, overdriven scan control signals, different initialization and reset voltages, and can include capacitors and transistors with different physical and electrical characteristics. Gate drivers provide scan signals to pixels in the full pixel density region, whereas overdrive buffers provide overdrive scan signals to pixels in the reduced pixel density region. The pixels in the full pixel density region and the pixels in the reduced pixel density region can be controlled using different black level or gamma settings for each color channel and can be adjusted physically to match luminance, color, as well as to mitigate differences in temperature and aging impact.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of clock signal lines and cascaded N driving units, and the nth-level driving unit further comprises a pre-charging module used for pre-charging the nth-level driving unit under the action of a level transmission signal of the (n-i) th-level driving unit, the driving control node is charged through a first driving signal of the (n-i) th-stage driving unit; the output module is used for outputting a first driving signal through the first driving output end and outputting a second driving signal through the second driving output end under the action of the control voltage on the driving control node; according to the gate driving circuit, the number of the driving units can be reduced by half on the premise that the number of the output signals is the same through the mode that the first-stage driving unit outputs the two driving signals, so that the number of transistors in the gate driving circuit is greatly reduced, a narrow-frame product can be achieved, meanwhile, the cost of a panel is reduced, and the stability of the panel is improved.

The invention discloses a display device and a display driving chip and method thereof. A display area of the display panel comprises a high-refresh-rate display area and a low-refresh-rate display area which are adjacent to each other. And in the whole refresh frame period, the high-refresh-rate display area and the low-refresh-rate display area refresh data. In the local refresh frame period, the high-refresh-rate display area refreshes data, and the low-refresh-rate display area does not refresh data. The controller controls the gate driver such that a boundary of the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period is different from a boundary of the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period.

A gate driver includes a control circuit which controls a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, a the second control clock signal, a carry output circuit which generates a carry signal in response to voltages of the first control node and the second control node, an enable node control circuit controlling a voltage of an enable node in response to the carry signal, an enable signal, and an inverted enable signal, a masking circuit which controls a voltage of a first intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the enable node, and a gate output circuit which outputs a gate signal in response to the carry signal, the voltage of the first intermediate node, and an output clock signal.

The invention discloses a power device driver and a parameter correction method thereof, which are applied to the technical field of power device driving, and are characterized in that a data acquisition module acquires grid voltage and peak current of an IGBT (Insulated Gate Bipolar Translator) in the working process of the IGBT to obtain sampling data; the digital isolation chip realizes electrical isolation among the data acquisition module, the MCU and the grid voltage regulation module; the MCU calibrates the real-time junction temperature data based on the sampling data by using a preset junction temperature calibration formula and outputs calibrated junction temperature data; the gate driving chip outputs a gate voltage capable of driving the IGBT according to the control signal; the second-order short-circuit protection module sends an abnormal signal to the MCU when the IGBT is short-circuited, so that the MCU sends a grid voltage regulation trigger signal to the grid voltage regulation module; the grid voltage adjusting module responds to the grid voltage adjusting trigger signal and controls itself to reduce the grid voltage. Based on the power device driver and the parameter correction method thereof provided by the invention, the junction temperature monitoring precision and reliability are improved.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

Gate control of power semiconductor devices using reduced gate drivers is disclosed. A circuit breaker may include a multitude of transistors, such as insulated gate bipolar transistors (IGBTs), connected in series with one another. Each transistor may be connected to a respective gate resistor. Diodes may be connected between various gate resistors. One or more resistor-capacitor (RC) snubber circuits may be provided in parallel with one or more of the transistors. Likewise, one or more metal-oxide varistors (MOVs) may be connected in parallel to one or more of the transistors. A gate driver (e.g., a single gate drive) may be connected to the one or more diodes and an emitter of at least one of transistors.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

A gate driver includes a stage configured to output a gate signal, the stage including an input part configured to control a voltage of a first node and a voltage of a second node based on signals supplied to a first input terminal and a second input terminal, an output part configured to supply a voltage of a first power source or a voltage of a second power source as the gate signal to an output terminal based on a voltage of a third node and a voltage of a fourth node, a first signal processing part configured to supply the voltage of the second power source to the fourth node based on the voltage of the first node, or to electrically connect the second node and the fourth node through a fifth node based on a signal supplied to a third input terminal, and a second signal processing part including a first transistor connected between the third node and a sixth node to control the voltage of the third node based on an operation of the first transistor.

The utility model provides a high-voltage pulse generating device and a test system. The high-voltage pulse generating device comprises a main control unit, a driving circuit, a pulse control circuit with a wide bandgap semiconductor power device, and an output circuit, the first end of the main control unit is coupled with the first end of the driving circuit, the second end of the driving circuit is coupled with the first end of the pulse control circuit, and the second end of the pulse control circuit is coupled with the output circuit; the main control unit is configured to generate two paths of first PWM (Pulse Width Modulation) signals with dead time control; the two paths of first PWM signals are sent to the driving circuit; and the driving circuit is configured to process the first PWM signal and then drive the pulse control circuit, so that the output circuit generates a high-voltage pulse signal. According to the utility model, the structure is simple, the cost can be greatly reduced, the output pulse speed can be flexibly set, and the CMTI test requirements of different isolated gate drivers can be met.

Embodiments relate to a level shifter including a first circuit unit configured to output a start signal, a reset signal, and a node charge signal to a gate driver in response to a start control signal and a node charge control signal that are input from a timing controller, a second circuit unit configured to output an output erase signal and a clock shift stop signal in response to the start signal and the reset signal, and a third circuit unit configured to generate a clock signal based on a clock control signal input from the timing controller and output the generated clock signal to the gate driver in response to the output erase signal and the clock shift stop signal that are output from the second circuit unit, a display device including the same, and a method of driving the display device.