738 results about "Gate driver" patented technology

A display device includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a data voltage to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate the common gate signal.

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

An integrated circuit is provided for driving the gate of a GaN power switch transistor in a switching power converter. During a first portion of an on-time period for the GaN power switch transistor, the integrated circuit charges the gate through a relatively high pull-up resistance. During a second portion of the on-time period, the integrated circuit charges the gate through a relatively low pull-up resistance. During a first portion of an off-time period for the GaN power switch transistor, the integrated circuit discharges the gate through a relatively low pull-down resistance and then discharges the gate through a relatively high pull-down resistance in response a voltage of the gate falling below a threshold voltage.

A gate driver and a vehicle display are disclosed herein. The gate driver comprises a shift register module and a selection module. The shift register module includes first to fourth dummy shift register circuits and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal and one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

A display apparatus includes a substrate including a display area, a camera hole, and a non-display area, a light-emitting element disposed in the display area, a gate driver disposed in the non-display area, and an initialization signal line disposed in the display area, wherein the display area includes left and right display areas with respect to the camera hole, and an array pixel area, and the initialization signal line is disposed in each of the left display area and the right display area.

A method of generating driving patterns for an active gate driver, AGD, the method comprising controlling a power semiconductor, at a plurality of operating conditions, with the AGD. For each operating condition, one or more electrical signals of the power semiconductor are obtained, a variation in one or more key parameters of the power semiconductor is detected from the one or more electrical signals, and a driving pattern, corresponding to the variation in the one or more key parameters, is generated based on a pre-determined relationship between the variation in the one or more the key parameters and one or more driving parameters of the driving pattern. The generated driving patterns for each operating condition, and the corresponding variation in the one or more key parameters, are stored in a memory.

Provided are a display device and a method of driving the same that prevent an operation of an NIR proximity sensor from affecting luminance change, and the display device includes a display panel including a plurality of pixels, and a gate driver including first to fourth scan drivers and a light emission control signal driver, wherein each of the pixels includes a driving transistor configured to control a driving current of a light-emitting element, and a compensation transistor configured to compensate for a threshold voltage of the driving transistor, each of the pixels is sequentially driven in a first bias section, an initialization section, a sampling section, a second bias section, and a light emission section during one frame, and a first scan signal is output so that the compensation transistor is turned on before the sampling section.

A display device includes a base layer including a display area in which a plurality of pixels is disposed and a non-display area disposed adjacent to the display area, a gate driver disposed in the non-display area and configured to output a write scan signal, a scan line, and a shield pattern. The scan line includes a vertical line extending from the gate driver in a first direction and configured to apply the write scan signal to the plurality of pixels, and a horizontal line extending in a second direction crossing the first direction and electrically connected to the vertical line. The shield pattern overlaps the vertical line.

Each of stages of a gate driver includes a first pull-up control circuit applying a previous carry signal to a first control node, a buffer circuit outputting a gate clock signal, and a pull-down circuit outputting a second low voltage. The first pull-up control circuit includes a fourth-first transistor including a control electrode connected to a previous carry input node, a first electrode connected to the previous carry input node, and a second electrode connected to a second control node, a fourth-second transistor including a control electrode connected to the previous carry input node, a first electrode connected to the second control node, and a second electrode connected to the first control node, a first inter-node capacitor connected between the previous carry input node and the second control node, and a second inter-node capacitor connected between the second control node and the first control node.

A gate driver includes a switching circuit outputting a gate driving voltage to a gate of a semiconductor power switching device (IGBT) via a series gate resistor. The gate driver further includes an external controllable capacitor circuit that is coupled at the gate of the semiconductor power switching device to provide an adjustable external gate capacitance in parallel with a parasitic gate or input capacitance of the IGBT. The capacitor circuit may be controlled by one or more electrical signals to vary the external gate capacitance and thereby the characteristics of a switching operation.

A shift register, includes a shift register unit and a first detection circuit electrically connected to the shift register unit. The shift register unit includes an input sub-circuit and an output sub-circuit. The input sub-circuit is configured to transmit a signal of an input signal terminal to a pull-up node under control of an input control terminal. The output sub-circuit is configured to receive a clock signal from a clock signal terminal, and provide an output signal to an output signal terminal based on the clock signal under control of a voltage at the pull-up node. The first detection circuit is electrically connected to the pull-up node and the clock signal terminal and is configured to obtain a voltage difference at the pull-up node within a first interval time, and perform compensation on a voltage of the clock signal based on the voltage difference at the pull-up node.

A display device includes a display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines, wherein the plurality of pixels include: a first transistor connected between a driving voltage line and a second node; a sixth transistor connected between the second node and a common voltage line; a light emitting element connected between the sixth transistor and the common voltage line; and a fourth transistor connected between the second node and an initialization voltage line, and the gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels.

A masking circuit includes a ninth transistor including a control electrode connected to a second masking control node, a first electrode receiving a first clock signal, and a second electrode, a tenth transistor including a control electrode receiving a carry signal, a first electrode receiving a high gate voltage, and a second electrode connected to a first node, an eleventh transistor including a control electrode receiving a second enable signal, a first electrode connected to the first node, and a second electrode connected to the second masking control node, a twelfth transistor including a control electrode receiving a first enable signal, a first electrode connected to the second masking control node, and a second electrode connected to a second node, and a thirteenth transistor including a control electrode receiving the carry signal, a first electrode connected to the second node, and a second electrode receiving a low gate voltage.

An inverter driving apparatus is capable of resolving current imbalance of power modules having different threshold voltages for an inverter including a plurality of power modules connected in parallel. The inverter driving apparatus includes a gate driver configured to output a gate voltage to the plurality of power modules and monitor threshold voltages of the plurality of power modules, and a controller configured to output a PWM (Pulse Width Modulation) signal to the gate driver in response to a command input from the outside and output a voltage control signal to the gate driver, based on the threshold voltages. The gate driver may be configured to output the gate voltage, based on a feedback gate voltage that includes feedback regarding the gate voltage, the PWM signal, and the voltage control signal.

A display device includes: a display panel including a pixel connected to a first gate line, a second gate line, a third gate line, and a light emission control line; a gate driver; and a timing controller. The gate driver is to: output a first gate signal, a second gate signal, a third gate signal, and an emission control signal, each having a pulse, during an active period; and output the emission control signal having a pulse, while maintaining the first and second gate signals at a constant voltage, during a blank period. The timing controller is to: provide, to the gate driver during the active period, first to fourth clock signals that toggle between a logic high level and a logic low level; and maintain the first and second clock signals at a constant voltage during the blank period.

A drive circuit includes first gate driver on array (GOA) circuits and p first partition control signal lines, p is an integer greater than or equal to 2, the first GOA circuits are sequentially cascaded, the first GOA circuits include n first GOA circuit combinations, n is an integer greater than or equal to p, and first GOA circuits in each first GOA circuit combination are sequentially cascaded; and a partition control end of each first GOA circuit in a (px+y)th first GOA circuit combination in the n first GOA circuit combinations is coupled to a yth first partition control signal line in the p first partition control signal lines, x is an integer greater than or equal to 0 and less than or equal to (n−y) / p, and y is an integer greater than or equal to 1 and less than or equal to p.

Various techniques are described to control the rate of change of current (di / dt) and the rate of change of voltage (dV / dt) for power electronic switches with conventional gate drivers and a few additional components. By implementing these techniques, designers may achieve better control over the switching behavior, reduce losses, and improve the overall reliability and efficiency of their circuits. This is particularly important in applications such as power inverters, where high performance and reliability are important.

A motor driving device and a home appliance according to one embodiment disclosed herein comprises: a converter for converting input alternating current power into direct current power to output the direct current power; a direct current terminal capacitor for storing the direct current power; an inverter which includes a plurality of upper arm switching elements and lower arm switching elements connected in series, and converts the direct current power from the direct current terminal capacitor into alternating current power to drive a motor; a current detection unit disposed between the direct current terminal capacitor and the inverter; gate drivers for driving the switching elements included in the inverter; bootstrap capacitors which are charged in response to the lower arm switching elements being turned on and supply a driving voltage to the gate drivers of the upper arm switching elements; and a control unit for controlling the inverter on the basis of the current detected by the current detection unit, wherein the control unit first turns some of the plurality of lower arm switching elements on and off and then turns the other lower arm switching elements on and off before driving the motor.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

To provide a display device with a narrow border. 【Solution means】A display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit. The second layer has a demultiplexer circuit. The third layer has a display portion. Pixels are arranged in a matrix in the display portion. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit, and the output terminals of the demultiplexer circuit are electrically connected to the pixels. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the pixels. Further, the gate driver circuit and the data driver circuit are not clearly separated and have an overlapping region. Five or more gate driver circuits and data driver circuits can be provided respectively.

A display device includes a display panel including a pixel, a gate driver which provides a plurality of gate signals to the pixel, a data driver which provides a data voltage to the pixel in an address scan period and does not provide the data voltage to the pixel in a self-scan period, and a power management circuit which provides high gate voltages of the gate signals to the gate driver. A level of a high gate voltage which is one of the high gate voltages in the self-scan period may be different from a level of the high gate voltage in the address scan period.

A gate driver includes an input circuit transmitting an input signal to a Q-node in response to a first clock signal, a first A-node control circuit controlling an A-node in response to the first clock signal or the Q-node, a second A-node control circuit controlling the A-node in response to a second clock signal, a B-node control circuit controlling a B-node in response to the first clock signal and the Q-node, a C-node control circuit controlling a C-node in response to the B-node, a first QB-node control circuit controlling a QB-node in response to the second clock signal, a second QB-node control circuit controlling the QB-node in response to the Q-node, a pull-up circuit pulling up a gate output signal to a high power voltage in response to the QB-node and a pull-down circuit pulling down the gate output signal to a low power voltage in response to the Q-node.

High-voltage (HV) semiconductor switches are used in various applications. On-impedance (Ron) of the HV switches is prone to process, voltage, and temperature (PVT) variations. The present invention discloses system and method embodiments to calibrate a gate-to-source voltage (Vgs) of the switch based on a low temperature coefficient resistor and current references. The Ron of a replica switch transistor is matched to a reference resistor using a feedback to generate the required Vgs voltage. The calibrated Vgs is enforced to the floating HV switch transistor via controlling the bias current of a replica gate driver by feedback. With this approach, a desired input current to the gate driver may be obtained and applied to a main gate driver to control the Ron of the floating HV switches. Simulation results demonstrate a significant improvement in Ron variation.

The invention relates to a display device and an electronic device. The display device includes: a display panel including a plurality of pixels; a gate driver that outputs a gate signal to the display panel; a data driver that generates a data voltage applied to the display panel; and a multiplexer block that outputs the data voltage to the display panel. The multiplexer block includes: an output control transistor including: a control electrode receiving an output control signal; a first electrode connected to the first data line; and a second electrode connected to the second data line.

Discussed are a display device and a driving method thereof. The display device includes a display panel having data lines, gate lines, and pixel lines with pixels, a data driver connected to the data lines, a gate driver connected to the gate lines, and a timing controller configured to receive first pixel data of an input video or second pixel data of the input video from a set and control the data driver and the gate driver based on the received pixel data. The timing controller is configured to write, when the second pixel data is received from the set at a transmission speed faster than the first pixel data, the second pixel data to the pixels during a writing period in one frame. Then the timing controller is configured to write black data having a black grayscale value to the pixels during a vertical blank period.

An electronic device may include display and touch sensor circuitry. The display circuitry may include gate driver circuitry that provides anode reset control signals to display pixels. If desired, the gate driver circuitry may include per-row gate drivers and per-row pull-down circuits in an interlaced configuration on opposing sides of the display pixel array. If desired, the gate driver circuitry may include gate drivers configured with dynamic knee voltage control on their driver outputs.

A display device and an electronic device including the same are disclosed. The display device includes: a display panel including sub-pixels connected to first sub-gate lines and second sub-gate lines; a gate driver configured to supply a first sub-gate signal to the sub-pixel through the first sub-gate line and a second sub-gate signal to the sub-pixel through the second sub-gate line during a display scan period; and a voltage generator configured to supply an offset signal to the first sub-gate line during a self-scanning period in which the supply of the second sub-gate signal is stopped.

A gate driver includes a pull-up control circuit configured to apply a previous carry signal to a pull-up control node in response to the previous carry signal among carry signals of previous gate drivers, a buffer transistor configured to output a gate clock signal as a gate output signal in response to a signal of the pull-up control node, and including an upper gate electrode connected to the pull-up control node and a lower gate electrode connected to a stabilization node, a first stabilization transistor including a gate electrode connected to the pull-up control node and a first electrode connected to the stabilization node, and a second stabilization transistor including a gate electrode connected to a pull-down control node and a first electrode connected to the stabilization node.

A power module comprises: an upper arm structure that includes a first semiconductor switch, a second semiconductor switch and a first diode; a lower arm structure that includes a third semiconductor switch, a fourth semiconductor switch and a second diode; a first gate driving board, attached with the upper arm, wherein the first gate driving board includes a first gate driver connected to a first gate of the first semiconductor switch and a second gate driver connected to a second gate of the second semiconductor switch; a second gate driving board, attached with the lower arm, wherein the second gate driving board includes a third gate driver connected to a third gate of the third semiconductor switch and a fourth gate driver connected to a fourth gate of the fourth semiconductor switch; etc.

An electronic device includes an array substrate. The array substrate includes a first gate line, a second gate line, a third gate line, a first pixel unit, a second pixel unit, a third pixel unit, and a gate driver circuit. The third gate line is disposed between the first gate line and the second gate line. The first pixel unit is electrically connected to the first gate line and a data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driver circuit is electrically connected to the first gate line, the second gate line, and the third gate line. The gate driver circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.