10 results about "Boost power converter" patented technology

An apparatus includes: a clock generator configured to generate a set signal fed to a set input of a latch; an error amplifier configured to generate a COMP signal; an offset generator configured to generate different offset voltages; and a comparator configured to generate a reset signal fed to a reset input of the latch, wherein the non-inverting input of the comparator is configured to receive a signal equal to the sum of a current sensing signal and a slope compensation signal, wherein the current sensing signal is equal to the current flowing through a power converter multiplied by an adjustable gain, and the inverting input of the comparator is configured to receive an error signal, wherein the error signal is equal to the COMP signal minus the offset voltage generated by the offset generator.

The present document describes a control circuit for controlling a buck-boost power converter, which is configured to provide at an output node of the power converter an output current at an output voltage based on electrical power at an input voltage which is provided at an input node of the power converter. The control circuit is configured to determine an operation mode that the power converter is operated in; to determine an error voltage signal based on the output voltage, based on a reference voltage for the output voltage and based on the determined operation mode of the power converter; and to determine a control signal for controlling one or more power switches of the power converter in dependence of the error voltage signal.

This application discloses start-up of a boost power converter having a switched capacitor network. The boost power converter has stacked nodes, each of the stacked nodes connected to a stacked switch and a pump capacitor to form the switched capacitor network. There are first and second of the stacked nodes. The second stacked node drives a particular stacked switch of a plurality of stacked switches. When all of the stacked switches are off, a first voltage causes the first stacked node to have a first stacked node voltage and causes the second stacked node to have a second stacked node voltage that is less than the first stacked node voltage. During a first state, the second stacked node voltage is insufficient to drive the particular stacked switch. During a second state, the second stacked node voltage is sufficient to drive the particular stacked switch. Transitioning the switched capacitor network from the first state to the second state includes, among other things, causing the second stacked node voltage to become sufficient to drive the particular stacked switch.

An apparatus includes a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.

Techniques associated with a circuit, in particular a zero current detection circuit, are disclosed. The disclosed zero current detection circuit includes a plurality of dynamic comparators. The operating clocks of the dynamic comparators are generated by a plurality of flip-flops, each flip-flop being configured to latch an output of one dynamic comparator corresponding thereto and then provide the latched output as a clock of another dynamic comparator downstream of the previous dynamic comparator. The dynamic comparator is activated when power is supplied to the dynamic comparator only in a required period of a charge / discharge cycle of the boost-type power converter.

A multi-level boost power converter circuit includes: at least two high-side switches; at least two low-side switches; a first capacitor; an inductor; and a control circuit configured to generate plural operation signals. The first end of the first capacitor is coupled between the at least two high-side switches, and the second end of the first capacitor is coupled between the at least two low-side switches. One end of the inductor is coupled to the input voltage, and the other end of the inductor is coupled to an inductor switching node, which is connected to either the first or second end of the first capacitor. The plural operation signals are configured to control the at least two high-side switches and the at least two low-side switches, thereby switching the voltage at the inductor switching node between a first divided voltage of the output voltage and the output voltage, or between the first divided voltage of the output voltage and a reference level.

Disclosed are a buck-boost power converter and an electronic device including same. The power converter is a buck-boost power converter and may include a power switching circuit and a control circuit. The power switching circuit includes a plurality of switches and an inductor, and can supply a load with an output voltage boosted or bucked from an input voltage. The control circuit may generate switching signals on the basis of node signals corresponding to the input voltage, the output voltage, and an inductor current. The control circuit may control to make the operating mode one of a buck mode, a buck-boost mode, or a boost mode by outputting switching signals to the plurality of switches. The control circuit may output switching signals for controlling so that the inductor current has three different slopes in a first section, a second section, and a third section of one switching cycle operating in the buck-boost mode. Various other embodiments that can be understood through the present document are also possible.

An apparatus includes a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.

An apparatus as discussed herein can be configured to include a first circuit operative to receive an input voltage supplied by an input voltage source. A series circuit path including an inductor and a second circuit also receives the input voltage. The first circuit may be coupled to the second circuit. The series circuit path including the inductor and the second circuit produces a respective output voltage to power load based at least in part on input from the first circuit.

An apparatus as discussed herein can be configured to include a first bridge circuit operative to receive an input voltage supplied by an input voltage source. An inductor in the apparatus also receives the input voltage. The apparatus can be configured to include a second bridge circuit. The inductor provides coupling of the input voltage source to the second bridge circuit. The second bridge circuit produces an output voltage to power a load.