The invention belongs to the technical field of power sources and relates to a self-
adaptation voltage regulator circuit. The self-
adaptation voltage regulator circuit comprises a power tube MP, a power tube MN, an
inductor L, a
capacitor C, a first
resistor RF1, a second
resistor RF2, a
simulation phase lead compensation module, a
delay phase
lag compensation module, a critical path duplication module, a
sawtooth wave generating module, a
comparator and a power tube driver. The output
voltage Vout is partitioned by the first
resistor RF1 and the second resistor RF2.
Simulation phase lead compensation is achieved through an
operational amplifier, the resistor R1, the resistor R2 and the
capacitor C. A load of an
operational transconductance amplifier GM is RGM1 and provides the
loop gain of APD compensation. The
delay of the duplication of the critical path is compared with a
system clock CLK through phase detection. Then,
delay error signals are integrated through a
charge pump. The output voltage VPD of the
charge pump is connected to the positive going input end of the
operational transconductance amplifier GM. PWM waveforms can be obtained by comparing the
sawtooth wave current generated by an oscillator OSC and the output current of the GM. By means of the self-
adaptation voltage regulator circuit, the
power loss of a digital circuit is greatly reduced.