169 results about "Turn off time" patented technology

The present invention provides a DCDC converter using a dual-mode adaptive off-time timer, comprising: a PWM comparator, an on-time timer, a current detection module, an off-time timer logic control circuit, a drive control circuit, a dual-mode adaptive off-time timer, an inductor LOUT, an NMOS transistor MH, an NMOS transistor ML, a resistor RFB2, a resistor RFB1, and a capacitor COUT. The present invention is implemented by means of the PWM comparator, the on-time timer, the current detection module, the off-time timer logic control circuit, the drive control circuit, and the dual-mode adaptive off-time timer. The off-time of the internal dual-mode adaptive off-time timer has the function of adaptively adjusting an input signal and an output feedback signal, and a minimum off-time timer and an overcurrent off-time timer are simultaneously implemented by using one off-time timer.

The invention provides an IGBT (Insulated Gate Bipolar Translator) turn-off time measuring method, system, equipment and medium, and belongs to the field of power semiconductor device testing technology and state monitoring, and the method comprises the following steps: firstly, selecting 20% Vdc and 80% Vdc as turn-off initial measuring points, secondly, carrying out first error correction by adopting a linear estimation method, and finally, carrying out second error correction by adopting a linear estimation method; performing linear fitting on the voltage difference Vce data through a least square method to obtain initial turn-off time; and finally, aiming at systematic deviation caused by inherent concavity and convexity characteristics of the voltage curve, performing secondary error correction by adopting a convex hull algorithm, acquiring a lower envelope line of the ic-tOFF relation curve through an Andriw algorithm, and identifying and eliminating the problem of Overestimation of the turn-off time based on a convex hull accurate point set. According to the invention, accurate measurement of the turn-off time of the IGBT under the condition of low sampling rate is realized, the hardware cost is significantly reduced, and a reliable technical basis is provided for IGBT state monitoring and life prediction.

The invention discloses a power modulation method and system for an all-solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and segmenting the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments, obtaining a time-level number corresponding relation, and generating a corresponding switching action time sequence matrix; the row index of the switching action time sequence matrix corresponds to the level number, the odd-numbered columns store the turn-on time parameters of the switching devices under the corresponding level number, and the even-numbered columns store the turn-off time parameters of the corresponding switching devices; and converting the switching action time sequence matrix into period counting based on an FPGA main clock, and generating a corresponding driving pulse signal by the FPGA according to time sequence data so as to control a switching device in the all-solid-state power supply and carry out power modulation. High-real-time and high-precision control on the switch of the solid-state power supply is realized, and the effect of arbitrary waveform power modulation is realized.

A rectifier includes digital timers to control FET switching rather than direct measurement of current and / or voltage. The digital timers control turn-off time to compensate for a delay produced by comparators in the rectifier. The digital timers are adjusted over multiple cycles to arrive at a turn-off time that produces zero current turn-off. The digital timers may be periodically or continuously readjusted based on a preceding set of cycles. Adaptive turn-off via digital timers is useful for discontinuous conduction mode suppression.

The invention discloses an anti-saturation equivalent virtual impedance grid-forming type SVG fault current-limiting control method, which comprises the following steps of: inverting a direct current into an alternating current through an inverter, and filtering high-frequency harmonics through a filter to obtain a sine wave alternating current meeting a grid-connected requirement. A three-phase alternating current signal is collected in real time, coordinate transformation is carried out through a Park transformation module, and a modulation signal is obtained. The modulation signal is compared with a triangular carrier signal, a driving signal is generated, the on-off time of a power switching device of the inverter is controlled, the amplitude and phase of output voltage and current are adjusted, accurate control over the output power of the grid-connected inverter is achieved, and the power grid access requirement is met. According to the method, the limitation of traditional fixed parameters is broken through, and the robustness of the system to a complex fault scene is improved. In addition, manual intervention or a complex mode switching program is not needed, automatic smooth transition between different working conditions can be achieved, and powerful technical guarantee is provided for stable operation of a power grid.

The invention discloses a load transient detection circuit of a COT Buck, a corresponding COT Buck and a switching power supply. The load transient detection circuit comprises an input end, three resistors connected in series, two comparators and a switched capacitor sampling hold circuit, wherein the input end is grounded after passing through the three resistors in sequence. A node between the input end and the first resistor and a node between the second resistor and the third resistor are connected to the input ends of the first comparator and the second comparator through a switched capacitor sampling hold circuit structure. Valley voltage information and peak voltage information of inductive current are obtained through the switched capacitor sampling hold circuit, whether a load is transiently changed or not is judged by comparing inductive current ripples with a valley value and a peak value, and it is guaranteed that the switching power supply has appropriate transient detection trigger threshold voltage under any load. According to an output signal of the load transient detection circuit, the COT Buck can increase the turn-on or turn-off time so as to enhance the transient response speed.

The invention relates to the technical field of output control, in particular to a COT-based constant voltage control method, device and equipment and a storage medium, and the method achieves the precise control of the total duration of a target period through the dynamic adjustment of the turn-off time on the basis of the fixed turn-on time, can quickly respond to the sudden change of a load, and improves the stability of the load. The overshoot or undershoot phenomenon of the output voltage is reduced; specifically, voltage information is sampled in real time within the period conduction time, and the turn-off time of the next period is immediately adjusted after the period is ended, so that error accumulation caused by delayed adjustment in a traditional control mode is avoided, the dynamic response capability to battery voltage fluctuation is enhanced, and the output precision is improved; besides, a strategy of synchronous opening and unified adjustment of turn-off time is adopted, so that the consistency of the turn-off time of multi-path output in a starting stage and a subsequent period is ensured, load change disturbance caused by asynchronous turn-off is avoided, and voltage rise deviation of a later turn-off channel is reduced.

The application discloses an energy-saving control method of a CSR high-frequency PWM rectifier circuit. According to the value change of each line voltage of three-phase alternating current in a rectifier circuit and the characteristic that the rectifier circuit works at a high frequency, the two pulse wave edges of two phases of the three-phase alternating current are overlapped. The overlapping time of the overlapping of the two pulse wave edges is equal to the sum of the turn-on time and the turn-off time of a switching tube, so that the front edge or the rear edge of a pulse of a switching signal is in a soft switching state or in a cut-off low voltage state, thereby reducing the switching process loss of the switching tube. The application provides the energy-saving control method of the CSR high-frequency PWM rectifier circuit, which can reduce switching loss, reduce cost, save energy, prolong service life and is safe and reliable.

An apparatus includes a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer, and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.

The invention relates to the technical field of output control, in particular to a constant power control method, device and equipment based on COT and a storage medium, according to the method, fixed turn-on time is combined with dynamic turn-off time adjustment, the conciseness of COT control is reserved, accurate control over output power is achieved, and the control efficiency is improved. The influence of interference factors such as battery voltage drop and load abrupt change on constant power output can be effectively counteracted; specifically, a multi-path output synchronous opening design is adopted, and unified turn-off time adjustment logic is combined, namely, the turn-off time of a (k + 1) th period is calculated according to the total duration of a target period, so that an asynchronous turn-off condition caused by parameter differences of all channels is avoided, and the voltage rise deviation generated by load changes of a later turn-off channel is reduced; real-time output voltage and load resistance are respectively sampled in one period, battery voltage fluctuation and load change are monitored in real time, and error accumulation caused by the fact that a measured value in the current period is extended to the next period to be adjusted is avoided.

The present invention relates to the technical field of SiC power devices, and more specifically, to a multi-layer circuit protection structure for SiC power devices. The structure comprises at least two SiC power devices, each of which is connected in parallel; and a drive circuit, wherein each gate of each SiC power device is connected to a turn-on path and a turn-off path. By improving the drive circuit, the present invention achieves a structure in which the drive circuit differentially adjusts the gate resistance of each device to offset the switching time difference caused by Vgs-th differences, thereby reducing or compensating for the turn-on and turn-off time differences caused by Vgs-th differences, and solving the problem of thermal runaway caused by large Vgs-th differences.

The application relates to a critical conduction mode control method of a totem-pole PFC converter, which utilizes energy equivalence to determine the resonance process of inductor current at switching commutation, carries out totem-pole Boost inductor current value estimation, and on this basis, utilizes a current zero-crossing point prediction algorithm to calculate the turn-on and turn-off time to generate corresponding active tube-synchronous rectifier tube commutation dead time T d,f , synchronous rectification conduction time T SR , rectifier tube-active tube commutation dead time T d,r ; the PWM drive signals of high-speed switching tubes Q1 and Q2 are generated by T on , T d,f , T SR , T d,r ; the power frequency drive signals of low-speed switching tubes Q3 and Q4 are generated by comparing the input alternating voltage v ac with a hysteresis comparison loop and 0. The method can effectively get rid of the dependence on a current zero-crossing detection circuit and a current sensor, reduces the cost and improves the system stability.

This invention discloses a load transient detection circuit for a COT Buck converter, along with a corresponding COT Buck and a switching power supply. The load transient detection circuit includes an input terminal, three resistors connected in series, two comparators, and a switched-capacitor sample-and-hold circuit. The input terminal is grounded after passing through the three resistors. The nodes between the input terminal and the first resistor, and between the second and third resistors, are connected to the input terminals of the first and second comparators via the switched-capacitor sample-and-hold circuit. The valley and peak voltage information of the inductor current is obtained through the switched-capacitor sample-and-hold circuit. By comparing the inductor current ripple with the valley and peak values, a transient change in the load is determined, ensuring that the switching power supply has a suitable transient detection trigger threshold voltage under any load. The COT Buck of this invention increases the on or off time based on the output signal of the load transient detection circuit to enhance the transient response speed.

The utility model belongs to the field of static change-over switches, and provides a static change-over switch, which comprises a machine body provided with an external power supply connecting end, a load connecting end and a standby power supply connecting end, and the standby power supply connecting end is electrically connected with the load connecting end; and the mainboard and relay integration is arranged in the machine body and is electrically connected with the mainboard, the external power supply connecting end, the load connecting end and the standby power supply connecting end. Compared with the prior art, the static change-over switch has the advantages that the relay is integrally arranged in the machine body and matched with the main board, the relay is adopted as a turn-off element of the static change-over switch, the turn-off time can be shortened to about 10ms, the defect that a thyristor does not conform to safety regulations is overcome, and the defects that a contactor is low in turn-off speed and high in cost are overcome. According to the technical scheme, the static change-over switch is economical and low in manufacturing cost, the stability and reliability of the whole system are guaranteed, and rapid switching of the static change-over switch between the grid-connected mode and the off-grid mode can be achieved.

The application discloses a power modulation method and system of a full solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and dividing the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments to obtain a time-level number corresponding relationship, and generating a corresponding switch action time sequence matrix; the row index of the switch action time sequence matrix corresponds to the level number, and the odd columns store the turn-on time parameters of the corresponding switch devices under the corresponding level number, and the even columns store the turn-off time parameters of the corresponding switch devices; the switch action time sequence matrix is converted into period counting based on the main clock of the FPGA, and the FPGA generates corresponding driving pulse signals according to the time sequence data, so as to control the switch devices in the full solid-state power supply and perform power modulation. The switch of the solid-state power supply is controlled with high real-time performance and high precision, and the effect of arbitrary waveform power modulation is realized.

The application discloses a dead time control circuit and electronic equipment, and belongs to the technical field of electronics. The dead time control circuit comprises an inductive element, a first field effect tube connected with the inductive element, a second field effect tube connected with the inductive element and the first field effect tube, a detection circuit for detecting a first switching state of the first field effect tube, a second switching state of the second field effect tube and a current flow direction of the inductive element, a logic judgment circuit for outputting an adjustment mode signal of a dead time, a first off time and a second off time according to the first switching state, the second switching state and the current flow direction, an operation circuit for outputting a dead time control signal according to the first off time and the second off time in an adjustment direction indicated by the adjustment mode signal, and a time delay circuit, wherein the dead time control signal is used for adjusting a time delay value of the time delay circuit to adjust the dead time of the first field effect tube and the second field effect tube.

The invention discloses a self-adaptive direct connection prevention double-N-type output driving circuit which comprises a first control circuit, a second control circuit, an output driving stage upper tube, an output driving stage lower tube, a diode D1, a resistor R1 and a resistor R2. The output driving stage upper tube MN1 and the output driving stage lower tube MN2 are NMOS (N-channel metal oxide semiconductor) tubes; the first control circuit is used for controlling the output driving stage upper tube to be conducted when a first time sequence signal CLK is valid; and the second control circuit is used for controlling the output driving stage lower tube to be switched on in a time delay manner when the first time sequence signal CLK is invalid. In the invention, the switch-on time and the switch-off time of the two channels can be respectively controlled by adjusting the resistor R1 and the resistor R2, and an NMOS tube with higher carrier mobility is used as a pull-up tube, so that the current pull-up capability is stronger; and self-adaptive conduction of the output driving stage upper tube and the output driving stage lower tube is formed, so that the high-speed GaN power tube driver can be suitable for a high-speed GaN power tube driver.

The circuits and methods of the present disclosure control the active off-time (high side switch on-time) to ensure the magnetization energy release and resonant capacitor energy release in an asymmetrical half-bridge (AHB) converter finish at the same time and all the stored energy is delivered to the output in each switching cycle. Multiple, parallel, techniques to control the high side switch on-time are illustrated. One is to track the volt-seconds applied during the storage cycle and allow the active release off-time to be limited to the same volt-seconds. A second option is to provide a high side switch on-time that is proportional to the on-time of the low side switch in that switching cycle. A third option is to provide a maximum high side switch on-time that can be programmed to ensure the high side on-time is equal to or smaller than half of the resonant period.

The objective is to provide a control device for a rotating electric machine that can prevent the generation of gate command signals that attempt to perform synchronous rectification during an abnormal period, even when the diode on-timing or diode off-timing cannot be correctly detected. [Solution] The control device 100 includes a synchronous rectification permission signal generation unit that generates synchronous rectification permission signals Swp and Swn based on the conduction state of the diodes; a switching signal generation unit 54 that generates switching signals Qp and Qn by setting the ON interval of the switching element within the range of the synchronous rectification permission intervals Tp and Tn indicated by the corresponding synchronous rectification permission signals Swp and Swn; an assumed permission interval setting unit that sets assumed permission intervals Tp* and Tn* of the synchronous rectification permission signals Swp and Swn based on the operating state of the rotating electric machine 1; and an abnormality determination unit 56 that determines whether or not there is an abnormality by comparing the synchronous rectification permission intervals Tp and Tn with the assumed permission intervals Tp* and Tn*.

A charging system includes a charging input interface, an inductor, a first switch, a second switch, a first voltage acquisition circuit, and a control circuit. The charging input interface is connected to the inductor, which is connected to the first switch and the second switch. The second switch is configured for electrical connection with an energy storage power supply. The first voltage acquisition circuit is connected to the second switch and configured to detect the first voltage output by the charging system in real time. The control circuit cyclically controls the switch on / off time of the first switch based on the first voltage. During the charging process of the charging system, when the first voltage is less than the first preset voltage value, the control circuit controls the first switch to conduct and starts cyclic control. The state of the first switch is opposite to that of the second switch.

A power switching circuit includes a driving signal part, a first switch element, a second switch element, a first driving circuit and a second driving circuit. The first driving circuit includes a first resistor and a first connection branch, which are connected between a positive driving signal terminal of the driving signal part and a first driving terminal of the first switch element, respectively. The second driving circuit includes a third resistor and a second connection branch, which are connected between the positive driving signal terminal and the second driving terminal of the second switch element, respectively. In a same switching cycle, the turn-on time of the first switch element is earlier than the turn-on time of the second switch element and the turn-off time of the first switch element is earlier than the turn-off time of the second switch element.

A lighting circuit and a control method thereof are provided. The lighting circuit includes a triac dimmer connected between an alternating current (AC) input power supply and a rectifier circuit, where the rectifier circuit is configured to output a bus voltage after phase cutting, and further includes a turn-on angle detection circuit configured to detect a turn-on state of the triac dimmer and output a first detection signal that represents a relationship between a turn-on angle of the triac dimmer and a first angle, and a bleeder circuit connected to the rectifier circuit and configured to control turn-off time of the bleeder circuit based on the first detection signal and a sampling signal representing a current of a light-emitting diode (LED) load.

The application discloses a pumped storage full-power frequency converter power unit variable frequency control method and device, N power units are cascaded at an AC end to form a test valve, and M power units are cascaded at the AC end to form a test valve; the method is used for controlling the test valve to output several AC frequency target values, and the method comprises the following steps: pre-charging DC capacitors in the test valve and the test valve to target values; determining corresponding output current / power target values according to the AC frequency target values to be output; controlling the turn-on and turn-off time of the turn-off semiconductor of each power unit in the test valve and the test valve, so that the actual output current / power of the test valve is the output current / power target value, and the actual output frequency of the test valve is the AC frequency target value. The application can simulate the continuous speed regulation operation condition of the pumped storage full-power frequency converter power unit on the pumped storage unit.

The utility model discloses an ultra-low frequency switching circuit capable of suppressing burrs, which comprises a switching buffer circuit, the signal input end of the switching buffer circuit receives a PWM (Pulse Width Modulation) signal, and the signal output end of the switching buffer circuit is connected with the grid electrode of any MOS (Metal Oxide Semiconductor) tube of an H-bridge inverter circuit; and the switch buffer circuit is used for prolonging the turn-on and turn-off time of an MOS (Metal Oxide Semiconductor) tube of the H-bridge inverter circuit. According to the utility model, by prolonging the turn-on and turn-off time of the MOS tube, burr signals caused by transient voltage and current changes are suppressed, and drain electrode current signals are innovatively subjected to electromagnetic coupling to form negative feedback on the grid electrode, so that transient changes are suppressed, the safety of devices is guaranteed, the service life of equipment is prolonged, and the failure rate is reduced.

This invention discloses an automatic switching system, method, and drive circuit for an uninterruptible power supply (UPS) in the field of power electronics. It includes a power module for providing electrical energy to the system; a relay switch unit for controlling the switching of mains power input; an accelerated turn-off unit for accelerating the turn-off of the relay switch unit; a circuit switching unit for switching a high-current drive circuit to a low-current drive circuit after a predetermined delay; and a control module for outputting a high-level signal to control the circuit switching unit to switch the high-current drive circuit to accelerate the closing of the relay switch unit, and outputting a low-level signal to control the accelerated turn-off unit to accelerate the turn-off of the relay switch unit. This invention employs a delayed switching drive design and an accelerated turn-off unit, which significantly simplifies the power supply hardware design, reduces the power requirements of the auxiliary power module, and significantly shortens the relay turn-off time, ensuring the stability and reliability of the UPS during the switching process.

Power conversion device (1) with a high-potential line (11H) and a low-potential line (11L), an upper branch semiconductor device (2H) connected to the high potential line, a sub-branch semiconductor device (2L) connected in series with the upper-branch semiconductor device (2H) and connected to the low-potential line, and a capacitor (3) which is connected between the high potential line and the low potential line, wherein from the upper branch semiconductor device and the lower branch semiconductor device connected in series, the upper branch semiconductor device forms a parallel circuit body (20) configured from two or more switching elements (2) connected in parallel to each other, and / or the lower branch semiconductor device forms a parallel circuit body (20) configured from two or more switching elements (2) connected in parallel to each other, in the upper branch semiconductor device and the Sub-branch semiconductor device connected in series, a return flow element (21) in the parallel circuit body is provided to allow current flow from a low-potential line side to a high-potential line side, The switching elements that form the parallel circuit body are controlled in such a way that the switching-off times are different from each other. a last-off element (22) that switches off last, and a non-last-off element (23) as the other element among the switching elements that form the parallel circuit body, an inductance of a closed last-off circuit (101) in which current flows through the last-off element, the return element in an opposite branch opposite to the last-off element, and the capacitor, is smaller than the inductance of a closed non-last-off circuit (102) in which current flows through the non-last-off element connected in parallel to the last-off element, the return element in an opposite branch opposite to the last-off element, and the capacitor, wherein the parallel body of the upper branch semiconductor device comprises the last-off element, the non-last-off element and the return element, and the parallel body of the lower branch semiconductor device comprises the last-off element, the non-last-off element and the return element, the last-off element, the non-last-off element and the reflux element in the upper-branch semiconductor device are mounted on a common upper-branch module (50H) as a single common semiconductor device, and the last-off element, the non-last-off element and the reflux element in the sub-branch semiconductor device are mounted on a common sub-branch module (50L) as a single common semiconductor device, the common upper branch module and the common lower branch module are each configured such that two power connections (551, 552) project from a module body (550), and the inductance of a wiring path in the module body that connects the power terminals via the last-off element is smaller than the inductance of a wiring path in the module body that connects the power terminals via the non-last-off element, wherein the common upper branch module and the common lower branch module are configured such that the two power terminals project from the module body in the same direction, and a center position (C) in a base section of the two power terminals is closer to the last-off element than to the non-last-off element in a direction in which the last-off element and the non-last-off element are arranged.

The present disclosure relates to a power conversion device. A power conversion device according to an embodiment of the present disclosure comprises: a transformer; a first switching element and a second switching element disposed on an input side of the transformer and connected in series with each other; an inductor connected to one end of the input side of the transformer; a third switching element and a fourth switching element respectively connected to the other end of the input side of the transformer; and a clamp capacitor connected between the fourth switching element and the third switching element, wherein, while the second switching element and the fourth switching element are turned on, the turn-off timing of the fourth switching element is delayed relative to that of the second switching element. Accordingly, switching loss can be reduced.

The invention discloses a vector switching method of a converter, which comprises the steps of detecting voltage values of a current voltage vector and a voltage vector to be switched, and executing voltage vector switching according to the voltage value of the current voltage vector and the voltage value of the voltage vector to be switched. The switching time sequence of the switching tube of the converter bridge arm is as follows: t Soff1 < = t Son2; when the target voltage vector is switched from the low voltage phase to the high voltage phase, the switching time sequence of the switching tube of the converter bridge arm is as follows: t Soff2 is less than or equal to t Son1; t Soff1 is the turn-off time of the switch tube, needing to be turned off, of the converter bridge arm, the source electrode of the switch tube faces the bridge arm intersection point, t Son2 is the turn-on time of the switch tube, needing to be turned on, of the converter bridge arm, the drain electrode of the switch tube faces the bridge arm intersection point, and t Soff2 is the turn-off time of the switch tube, needing to be turned off, of the drain electrode of the switch tube faces the bridge arm intersection point; t Son1 is the turn-on time of the switch tube, which needs to be turned on, of the converter bridge arm and of which the source electrode faces the bridge arm intersection point.

Provided is a power transistor control method belonging to the field of switching power supplies. The method includes: obtaining a feedback voltage of a load corresponding to a power transistor, and obtaining at least one valley signal and a valley latching signal when the power transistor is turned off; determining, based on the feedback voltage, a corresponding off-time signal of the power transistor; when the feedback voltage decreases, determining a target valley position based on the off-time signal and the valley latching signal; when the feedback voltage increases, determining the target valley position based on the off-time signal and the at least one valley signal; and controlling the power transistor to be turned on at the target valley position.

The invention discloses a method, a device and equipment for testing the turn-off performance of a photovoltaic system, and a medium, and relates to the technical field of photovoltaic system testing. Before practical application, by testing turn-off and turn-on operations of a component control component and a power supply of a photovoltaic system, turn-off output voltage parameters and turn-on output voltage parameters, corresponding to turn-off operations and turn-on operations, of output voltages of photovoltaic component arrays within and outside a preset limit range are acquired, and the turn-off output voltage parameters and the turn-on output voltage parameters reach respective stable states respectively through the turn-off operations and the turn-on operations; and recording turn-off time parameters when the photovoltaic module arrays within and outside the preset limit range correspondingly reach the first preset voltage and the second preset voltage during turn-off operation. The test result of the photovoltaic system is screened and determined in advance through the test process so as to avoid the problem that a photovoltaic rapid turn-off assembly or a certain control device goes wrong due to direct application, the fault maintenance cost is saved, and the work progress of the photovoltaic system is improved. And through unification of the turn-off performance test method, the reliability of the photovoltaic system is improved.