The invention discloses a half-bridge
driving circuit and method in a multi-level topology based on an FPGA (
Field Programmable Gate Array), the half-bridge
driving circuit comprises an MCU (Microprogrammed
Control Unit), an FPGA logic circuit and a
signal isolation circuit, the FPGA logic circuit gathers fault signals of other circuits in a complete
machine, when other circuits fail, the circuit is notified to carry out shutdown operation, and when the other circuits fail, the FPGA logic circuit does not fail, the
signal isolation circuit does not fail. In the process of switching on to switching off and the process of switching off to switching on, a
transition state that switching-on
voltage and switching-off
voltage are invalid exists in a period of time,
impact in the
state switching process is solved,
soft switching-off of an outer tube and an inner tube of a power main device in the multi-level topology from outside to inside is achieved in case of a fault, and
soft switching-off of the outer tube and the inner tube of the power main device in the multi-level topology is achieved. The
gate driver has the advantages that the
gate driver is simple in structure,
combinational logic and complex
sequential logic functions can be realized at low cost, the
signal isolation circuit is used for controlling conversion and isolation of PWM (pulse-width modulation) pulse to
voltage required by
gate control signals of a power device of a main circuit, peak voltage limitation and inner and outer tube
switching time sequences are realized, various faults can be monitored, and fault protection can be safely implemented.