The invention relates to a cascaded SiC power device, and relates to the field of
semiconductor power devices. According to the technical scheme, through the innovative structure that the first
capacitor is arranged between the gate and the drain of the Si MOS tube and the second
capacitor is arranged between the gate and the source, the switching speed of the cascaded SiC power device can be accurately regulated and controlled. Specifically, compared with a traditional scheme of increasing switch
delay by adjusting grid resistance and introducing extra loss by adding an external RC buffer circuit, the scheme can avoid extra
energy loss and realize consideration of performance and energy efficiency while ensuring low switch
delay; moreover, the scheme can effectively suppress the undesirable phenomena of
voltage overshoot,
ringing,
electromagnetic interference and the like, remarkably reduces the
voltage stress of the power device, improves the working stability of the device, prolongs the service life of the device, and enhances the overall reliability of a power electronic
system. In addition, according to the scheme, the implementation mode of switching speed regulation and control is simplified, convenience is provided for designers to carry out
device type selection and
circuit design, and the design efficiency of a power electronic
system is improved.