The invention belongs to the field of power
semiconductor devices, and discloses a dynamic current-sharing
layout design method and
system for a multi-
chip parallel
power module, and the method comprises two aspects of main power loop
layout and wiring and driving loop
layout and wiring. A main power loop is designed in a vertical commutation manner, and parallel
chip source electrodes and drain electrodes are designed in an integrated manner, so that quasi-common-source-
electrode inductors of the chips are consistent and integrated, and parallel dynamic
current sharing of multiple
gallium nitride chips is facilitated; wiring of the driving loop is in vertical commutation and is vertical to the main power loop, mutual
inductance of the power loop to the driving loop is basically zero, and parallel dynamic
current sharing of
gallium nitride chips is facilitated; when the design is met and grid leading-out ends and
Kelvin source leading-out ends of the four chips are symmetrical about the symmetry axis of the main power loop, the mutual
inductance of the main power loop to a part of wiring from a drive to each
chip grid is equal, and the mutual
inductance of the main power loop to a wiring from a
Kelvin source to a drive ground of each chip is also equal. And an excellent
gallium nitride multi-chip parallel dynamic
current sharing effect can be realized.