19 results about "Loop inductance" patented technology

The application relates to the technical field of fault prediction, and specifically discloses a gate loop inductance detection method for fault prediction, which comprises the following steps: collecting voltage signals of a gate drive node in continuous multiple switching cycles, converting the voltage signals into voltage values, and drawing a voltage waveform according to the voltage values; counting the number of times that a preset stable high level is greater than in the rising edge Si, and counting the number of times CS in all switching cycles; counting the number of times that a preset stable low level is less than in the falling edge Xi, and counting the number of times CX in all switching cycles; calculating the rising time and the falling time based on the voltage waveform, and averaging the rising slope and the falling slope; calculating the rising index and the falling index; and judging the fault cause based on the rising index, the falling index, the number of times CS and the number of times CX. The application realizes early fault identification and root cause differentiation by counting the gate waveform features of multiple switching cycles, and improves the diagnostic accuracy and the system reliability.

The invention provides a control device and method of a pulse power supply system, electronic equipment and a medium. The control device comprises a load coil (1), a loop inductor (2), a switch assembly (3), a follow current assembly (4), a loop resistor (5), a capacitor bank protection assembly (9), a charging protection assembly (10), a charging control switch (11), a direct current charging power supply (12) and a plurality of capacitor banks. A load coil (1), a loop inductor (2), a switch assembly (3), a follow current assembly (4) and a loop resistor (5) are sequentially connected, a plurality of capacitor banks are respectively connected with a capacitor bank protection assembly (9), a charging protection assembly (10) and a charging control switch (11) which are in one-to-one correspondence, and a direct current charging power supply (12) is respectively connected with the load coil (1), the loop resistor (5), the plurality of capacitor banks and the charging control switch (11). Wherein the load coil (1) comprises a positive wave load coil and a negative wave load coil.

A multi-phase power converter includes a printed circuit board having a plurality of conductive layers in a spaced apart and parallel relationship. The plurality of conductive layers includes a plurality of power planes in an interleaved configuration with alternating positive and negative voltages and configured to conduct a relatively high current for supplying to a load. The multi-phase power converter also includes a plurality of switching transistors disposed on an upper surface of the printed circuit board and configured to selectively conduct the relatively high current. The conductive layers include at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting signals for controlling operation of the plurality of switching transistors. A power converter phase includes a high-side transistor, a low-side transistor, and a driver circuit disposed adjacent to the transistors.

The application discloses a high-heat-dissipation high-frequency power module and a manufacturing method thereof. The high-heat-dissipation high-frequency power module comprises an embedded circuit board, at least one high-frequency capacitor and insulating heat-conducting material, and power electrodes of at least two semiconductor power devices are connected in series to form at least one power conversion bridge arm. The area ratio of the power electrode wiring of the semiconductor power device projected on the surface of the embedded circuit board to the area of the semiconductor power device is more than 60%. The power conversion bridge arm is connected in parallel with the high-frequency capacitor to realize low-loop inductance interconnection. The application can realize high-frequency and large-current characteristics, has single-face high-heat-dissipation capacity and nearly ideal double-face high-heat-dissipation capacity. Due to excellent loop processing, the loop inductance of the bridge arm formed by two semiconductor power devices per 10 square millimeters is less than 2nH or even less than 1nH, which is suitable for MHz frequency requirement and is much higher than the current mainstream frequency of less than 100KHz.

The invention relates to the technical field of chip series welding, and discloses a three-phase power bridge preparation process based on a multi-row chip series welding technology, and the preparation process comprises the following steps: S1, design and layout, S2, multi-beat chip mounting, S3, reflow soldering and silver sintering, S4, housing assembly and potting, and S5, testing and screening. A wiring pattern of a copper-clad ceramic substrate is designed, then a current path is optimized, loop inductance is minimized, the current distribution uniformity between parallel chips is ensured, enough safe creepage distances and electrical gaps between different potentials are ensured, and the electrical gaps comprise DC +, DC-and output U / V / W of each phase. Optimizing chip arrangement and copper layer thickness to facilitate conduction of heat to a radiator, balancing thermal coupling, space utilization rate and process feasibility, designing low-inductance routing for a gate drive signal, and forming a required copper circuit pattern through active metal brazing; and cleaning and surface treatment are carried out to improve the reliability of subsequent welding and bonding.

The invention relates to the technical field of fault prediction, and particularly discloses a grid loop inductance detection method for fault prediction, which comprises the following steps of: acquiring voltage signals of a grid driving node in a plurality of continuous switching periods, converting the voltage signals into voltage values, and drawing a voltage waveform according to the voltage values; counting the number of times in the rising edge Si which is greater than a preset stable high level, and counting the number of times CS in all switching periods; counting the number of times smaller than a preset stable low level in the falling edge Xi, and counting the number of times CX in the whole switching period; calculating a rise time and a fall time based on the voltage waveform, and averaging a rise slope and a fall slope; calculating a rising index and a falling index; and determining a fault cause based on the rising index, the falling index, the number of times CS and the number of times CX. According to the invention, by counting the grid waveform characteristics of a plurality of switching periods, early fault identification and root cause distinguishing are realized, and the diagnosis accuracy and the system reliability are improved.

The application provides a low-voltage electrical product large-current synthesis test system and method, which comprises: a current source system comprising a first switching valve connected in series with a low-voltage electrical product, a first loop inductor, a first charging capacitor, a first charging system connected in parallel with the first charging capacitor, a first discharging component, a first loop voltage measuring device and a first grounding switch; a voltage source system comprising a second loop inductor connected in series with the low-voltage electrical product, a second switching valve, a second charging capacitor, a second charging system connected in parallel with the second charging capacitor, a second discharging component, a second loop voltage measuring device and a second grounding switch; the first switching valve and the second switching valve are reverse-parallel thyristor valves; the current source system, the voltage source system and a third loop current measuring device are grounded through a common point. The application can perform a low-voltage electrical product large-current synthesis test with low risk.

A silicon substrate providing wafer-scale routing and power distribution includes a redistribution layer structure patterned across substantially the entire wafer. The redistribution structure contains signal paths and power meshes with co-planar return conductors that reduce loop inductance and voltage droop during high-speed switching. Multiple device-mount regions distributed over the wafer connect through these paths to support direct chip-to-chip communication without an organic interposer. Reticle-stitch redundancy, embedded decoupling, and isolation trenches improve continuity and reliability. The architecture enables large-scale multi-chip assemblies with uniform impedance, reduced parasitics, and efficient power delivery across the silicon plane.

The invention discloses a power module with variable parasitic parameters, which belongs to the technical field of power electronic devices and comprises a ceramic substrate, a circuit copper layer covering the ceramic substrate, a quick release base and a chip mounted on the circuit copper layer, and a power source electrode, a power drain electrode, a signal grid electrode and a signal source electrode which are welded on the circuit copper layer. A gate-source capacitor, a gate resistor and a drain-source capacitor are inserted into the quick-release base, so that parasitic parameters are quickly adjusted; the length of the inductance adjusting bonding wire is changed through the inductance adjusting bonding wire bonded on the circuit copper layer so as to adjust the parasitic inductance of the gate source driving loop. According to the power module provided by the invention, rapid replacement of a capacitor between a gate and a source, a gate resistor, a capacitor between a source and a drain and a gate-source driving loop inductor can be realized, rapid optimization of a plurality of numerical values is realized based on the same module, oscillation of driving voltage in a switching process is effectively relieved, and the speed of design iteration is greatly improved.

The invention relates to an output inductance balancing method of a multi-half-bridge module parallel system, in particular to a multi-half-bridge module parallel system with balanced output inductance and an output inductance balancing method. The half-bridge IGBT module mainly solves the technical problem that current sharing cannot be achieved due to the fact that direct current sides are asymmetrical and solidified when existing half-bridge IGBT modules are connected in parallel. According to the system, a high-inductance output path is designed for a half-bridge IGBT module connected to a low-direct-current inductance busbar, and a low-inductance output path is designed for a half-bridge IGBT module connected to a high-direct-current inductance busbar, so that accurate compensation for asymmetry of a direct-current side is realized, and main switch loop inductance of each parallel branch tends to be consistent. According to the invention, a complex active circuit does not need to be added, dynamic current unevenness between modules can be effectively suppressed in a compact space only by optimizing the mechanical structure of the output busbar, the reliability and the output capability of a system are remarkably improved, and the device is particularly suitable for high-power density application occasions such as locomotive traction, compact frequency converters and power supplies.

The utility model discloses a novel glue filling power module structure, and signal terminal installation arrangement is in the middle part of power module and extends upward, and power terminal arrangement is in the both sides of power module and extends outward, the root of signal terminal is connected on the insulating substrate of power module and drive board through pressure equipment and interference fit, the arrangement of signal terminal in the middle part of power module corresponds with drive board, and the arrangement of signal terminal is according to: there is shortening circuit loop between drive board and corresponding signal terminal, and the arrangement position of power terminal is flexibly laid out according to application demand. Through the application, built-in integrated drive board is at signal terminal, shortens circuit loop, reduces loop inductance, solves the cooperation problem of product and terminal drive board, and improves production efficiency.

A power electronic building block is provided, including capacitors, switch modules, a busbar arrangement, and at least one AC busbar. Connection points of the at least one AC busbar are arranged symmetrically along a first direction with respect to a plane perpendicularly intersecting the first direction, and the at least one AC busbar includes a hole elongated along the first direction and configured to balance one or more loop inductances between at least one AC external terminal point and the connection points. A modular multilevel converter (MMC) is also provided, including a plurality of converter arms each including at least one sub module formed by the PEBB.

The invention discloses a high-speed transmission cable and a production process thereof, the high-speed transmission cable comprises at least two signal core wires, a first shielding layer, at least one ground wire, a second shielding layer and an insulating layer, and the at least two signal core wires are arranged in parallel; the first shielding layer wraps the at least two signal core wires; the ground wire is flat and is attached to the first shielding layer; the second shielding layer wraps the ground wire and the first shielding layer; the insulating layer wraps the second shielding layer. According to the technical scheme, the coupling area of the ground wire and the shielding layer can be remarkably increased, an electromagnetic field is more uniformly distributed along the circumferential direction of the cable, loop inductance and a common-mode radiation peak value are reduced, the shielding efficiency is improved under the high-frequency condition, the integrity of differential signals is kept, and meanwhile a geometric stability reference is provided for a continuous production process.

The invention provides a three-level embedded module, and relates to the technical field of power electronics, the three-level embedded module comprises a circuit board, the front surface of the circuit board is provided with signal pins and power terminals; and the plurality of chip units are embedded and integrated in the circuit board and are connected with the signal pins and the power terminal wires to form a three-level topological structure. The beneficial effects of the invention are that copper cladding in the PCB is adopted to replace tedious wiring and dispersed layout in a traditional scheme, the wiring path is shortened and optimized, stray and loop inductance are greatly reduced, and the circuit control precision and the whole machine efficiency are improved; the chip is embedded in the PCB, traditional shell packaging is omitted, the size of the whole machine is remarkably reduced, the PCB substrate has an insulation function, an insulation structure does not need to be additionally arranged, heat dissipation and safety regulation troubles are avoided, and the junction temperature of the chip is improved; the integrated design avoids uneven current caused by layout difference of discrete devices, the assembly process is simplified, compared with a traditional plastic shell module, the manufacturing cost is reduced, and reliability and economical efficiency are both considered.

The application relates to an embedded power module, which comprises a substrate, a power device, a power copper layer and a signal copper layer. The substrate comprises a circuit layer, the circuit layer is provided with a containing space, the power device is embedded in the containing space, the power copper layer is attached to one side of the substrate close to the power device, the power copper layer is connected with the circuit layer and the power device through first connecting through holes to form interconnection, the signal copper layer is attached to the power copper layer, the signal copper layer is connected with the circuit layer and the power device through second connecting through holes to form interconnection, and the circuit layer, the power copper layer and the signal copper layer are arranged in a laminated mode in the thickness direction of the substrate, so that the positive and negative loop currents are laminated, the loop inductance and the stray inductance are reduced, and the performance of the power module is improved.

The invention discloses a voltage harmonic distortion rate estimation method and system for a transformer full-voltage no-load test. Relates to the technical field of electrical engineering. Collecting system parameters of the full-voltage no-load test system and basic parameters of the target transformer; air-rising harmonic voltage of the full-voltage no-load test system is tested; obtaining the inductance of a test loop based on the system parameters and the basic parameters, and calculating the harmonic voltage drop of the full-voltage no-load test system; under the target test voltage, the voltage harmonic distortion rate is calculated according to the air-rising harmonic voltage and the harmonic voltage drop; guiding the full-voltage no-load test system to perform equipment type selection based on the voltage harmonic distortion rate; according to the scheme, on the basis of the full-voltage no-load test system and the target transformer, the harmonic distortion rate when the test system outputs the target voltage under the specific equipment parameters is quantitatively and accurately predicted; according to the invention, guess based on experience is converted into model selection based on calculation, unnecessary margin is avoided, and the portability of a test system and the convenience of field deployment are improved.

The embodiment of the invention discloses a method for forming a capacitor in a packaging substrate, the packaging substrate and a packaging chip. According to the embodiment of the invention, at least one opening structure is formed on a provided core plate, then a first electrode layer and a second electrode layer which cover part of the side wall of each opening structure are formed, and further a dielectric material layer located between the first electrode layer and the second electrode layer is formed, the opening structure comprises a groove partially penetrating through the core plate and / or a through hole penetrating through the core plate, the first electrode layer and the second electrode layer are electrically isolated from each other and are opposite in position, the first electrode layer and the second electrode layer are used as polar plates of the capacitor, and the dielectric material layer is used as a dielectric layer of the capacitor. According to the embodiment of the invention, the capacitor can be directly formed in the packaging substrate, so that the packaging size can be reduced, the loop inductance of the power distribution network is reduced, and the link parasitism is improved.

The application provides a method, system, device and medium for impedance optimization of complex single-ended TSV, comprising: performing quasi-static three-dimensional electromagnetic simulation on a target TSV loop to obtain total loop inductance and total capacitance of a TSV structure; constructing a transmission line profile model connected at both ends of the TSV to obtain unit length capacitance and unit length inductance of a transmission line at both ends of the TSV; based on the total loop inductance and the total capacitance of the TSV structure and the unit length capacitance and the unit length inductance of the transmission line at both ends of the TSV, obtaining loop inductance and capacitance of an intermediate TSV part, and calculating characteristic impedance of the target TSV loop based on the loop inductance and the capacitance of the intermediate TSV part; comparing the characteristic impedance of the target TSV loop with target characteristic impedance, and performing impedance matching optimization on an existing structure to obtain a new structure after optimization; the application can greatly reduce the optimization design time of complex single-ended TSV in 2.5D and 3D packaging products, and improve product design efficiency.

The invention provides an adjustable inductance loop suitable for a multi-port electric energy router. The adjustable inductance loop comprises two high-frequency busbars, N groups of lifting mechanisms, M ports and M-1 electric reactors, wherein N is a positive integer, and M is a positive integer greater than 1; the two high-frequency busbars have the same width and thickness and are arranged in parallel along the thickness direction; the ports are connected through two high-frequency busbars; the reactors are connected in series between every two ports; the lifting mechanism comprises an insulating screw rod, a fixed seat, a lifting seat and a fixed plate; one end of the insulating screw rod is connected with one high-frequency busbar through the fixing seat, and the other end of the insulating screw rod is connected with the fixing plate; the lifting seat is sleeved on the insulating screw rod, and the lifting seat is connected with the other high-frequency busbar; and the lifting seat and the insulating screw rod can move relatively, so that the distance between the two high-frequency busbars can be adjusted. According to the invention, the distance between the two high-frequency busbars is adjusted by arranging the lifting mechanism, and the loop inductance can be adjusted, so that the stability and range of power transmission are improved.