61 results about "Loop inductance" patented technology

A bulk capacitor assembly for an inverter includes a stacked busbar, the stacked busbar including a first direct current (DC) busbar and a second DC busbar; one or more first capacitors on a first side of the stacked busbar, the one or more first capacitors electrically connected to the first DC busbar and the second DC busbar; and one or more second capacitors on a second side of the stacked busbar, the first side being opposite to the second side, the one or more second capacitors electrically connected to the first DC busbar and the second DC busbar.

A high-heat-dissipation high-frequency power module including an embedded circuit board, at least two semiconductor power devices, at least one high-frequency capacitor, and an insulating heat-conducting material is provided. Power electrodes of the at least two semiconductor power devices are connected in series to form at least one power conversion bridge arm. A ratio of the area of the overlapping projections of the power electrodes' wiring of the semiconductor power devices led out from the surface of the embedded circuit board, and the area of the semiconductor power devices is 60% or more. A power conversion bridge arm is connected in parallel to the high-frequency capacitor nearby so as to realize a low-loop inductance interconnection.

The invention discloses a loop inductance-based multi-chip parallel current rising process modeling method and system, and the method comprises the steps: writing a current rising process equation through a loop inductance method of a multi-chip parallel double-pulse test circuit, and accurately describing the current rising behavior in the multi-chip parallel double-pulse test circuit. By calculating the terminal voltage of each chip, the method can determine a key factor for achieving a complete current sharing condition, in a parallel circuit, current sharing is the key for ensuring that all components uniformly share loads and avoid overheating and damage, and the established simulation circuit model is based on an actual current rising process equation and the current sharing condition. And the behavior of an actual circuit can be accurately reflected. Based on circuit topology described by a graph theory, Kelvin sources, non-Kelvin sources and other connection modes are unified, most (all) electromagnetic induction effects are described with least inductance parameters, a simple and effective equation is obtained, and analysis and expansion are facilitated.

The invention discloses a short-circuit gas metal arc welding current waveform control method and system, a medium and a product, and belongs to the technical field of welding. The method comprises the steps that a current signal and a voltage signal in a welding loop are obtained in real time; calculating a loop inductance value according to the current signal and the voltage signal; the loop inductance value is compared with a first preset threshold value and a second preset threshold value, an inductance compensation strategy is dynamically generated, and preset welding current waveform parameters are adjusted according to the inductance compensation strategy; and the welding power source outputs a welding current waveform matched with the adjusted welding current waveform parameter, and the arc stability is improved by controlling molten drop stable transition. According to the method, the problems that in the welding process in the prior art, parameter matching is difficult, dynamic compensation is insufficient, and the technology applicability is poor are solved, and the molten drop transition consistency and the electric arc stability in the welding process are improved.

A multi-phase power converter includes a printed circuit board having a plurality of conductive layers in spaced apart and parallel relationship. The plurality of conductive layers includes a plurality of power planes in an interleaved configuration with alternating positive and negative voltages and configured to conduct a relatively high current for supply to a load. The multiphase power converter also includes a plurality of switching transistors disposed on the upper surface of the printed circuit board and configured to selectively conduct a relatively high current. The conductive layer includes at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting a signal for controlling operation of the plurality of switching transistors. The power converter phase includes a high-side transistor, a low-side transistor, and a driver circuit disposed adjacent the transistors.

The present invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for preparing a high-frequency response power transistor. First, an N-drift layer is grown on an N+ silicon substrate with a resistivity of >1000Ω·cm. An isolation trench with a depth of 12μm and a depth-to-width ratio of 5.9:1 is etched by ICP, and a SiO2 / Si3N4 composite dielectric layer is filled to expand the depletion layer to 18.5μm, thereby reducing the collector junction capacitance to 68pF and the breakdown voltage to 205V. Secondly, an interdigitated emitter is formed on the front side, and the back side is thinned to 100±2μm and then laser drilled. The through-holes are filled with pulse electroplated copper, and the copper pillar array compresses the loop inductance to 2.7nH. Finally, a Ti / Ni / Au transition layer is sputtered, and a diamond-copper composite substrate is hot-pressed and bonded. An 80nm TiC phase is formed at the interface, with a thermal conductivity of 635W / m·K and a thermal resistance reduced to 0.61K / W. The present invention optimizes capacitance, inductance, and thermal resistance, reducing switching losses by 57.8% and increasing power density to 51.2W / cm 2 , suitable for MHz-level high-frequency power systems.

The application relates to the technical field of fault prediction, and specifically discloses a gate loop inductance detection method for fault prediction, which comprises the following steps: collecting voltage signals of a gate drive node in continuous multiple switching cycles, converting the voltage signals into voltage values, and drawing a voltage waveform according to the voltage values; counting the number of times that a preset stable high level is greater than in the rising edge Si, and counting the number of times CS in all switching cycles; counting the number of times that a preset stable low level is less than in the falling edge Xi, and counting the number of times CX in all switching cycles; calculating the rising time and the falling time based on the voltage waveform, and averaging the rising slope and the falling slope; calculating the rising index and the falling index; and judging the fault cause based on the rising index, the falling index, the number of times CS and the number of times CX. The application realizes early fault identification and root cause differentiation by counting the gate waveform features of multiple switching cycles, and improves the diagnostic accuracy and the system reliability.

The invention relates to a system and a method for a lower commutated loop inductance bulk capacitor, in particular to a bulk capacitor assembly for an inverter, comprising: a stacked bus comprising a first direct current (DC) bus and a second DC bus; one or more first capacitors on a first side of the stacked bus bar, the one or more first capacitors electrically connected to the first DC bus bar and the second DC bus bar; and one or more second capacitors on a second side of the stacked bus, the first side being opposite the second side, the one or more second capacitors electrically connected to the first DC bus and the second DC bus.

The application discloses a Marx generator inductance acquisition method, comprising the following steps: outputting single-stage area inductance according to the length and radius of the single-stage area in the single FMG discharge main circuit of the Marx generator; the single-stage area inductance comprises switch section inductance, high-voltage plate section inductance, capacitor section inductance and output section inductance; outputting backflow area inductance according to the distance between backflow plates, the width of the backflow area and the length of the backflow area in the single FMG discharge main circuit of the Marx generator; outputting output area inductance according to the length and radius of the output area in the single FMG discharge main circuit of the Marx generator; and outputting the total inductance of the Marx generator according to the single-stage area inductance, the backflow area inductance and the output area inductance and the number of the single-stage area, the backflow area and the output area in the single FMG discharge main circuit of the Marx generator. The method can more accurately acquire the Marx generator loop inductance.

The invention discloses a device and method for measuring the temperature characteristic of a resistor disc, and belongs to the technical field of lightning arrester resistor disc testing. The device comprises a loop inductor, a loop resistor, an ignition sphere gap, a temperature simulation box and a parallel capacitor which are sequentially connected in series, the temperature simulation box can adjust the temperature, and a to-be-tested resistor disc sample is placed and connected in the temperature simulation box; the two ends of the resistor disc test object are connected in parallel with an adjustable resistance box; the two ends of the resistor disc sample are connected in parallel with a voltage divider used for voltage measurement. The lower end of the resistor disc sample is connected in series with a current collector for current measurement. According to the invention, the resistor disc test object is placed in the temperature simulation box so as to obtain different temperatures, the adjustable resistor box is additionally arranged so as to obtain the voltage under the current from dozens of milliamperes to dozens of amperes, and the resistance change trend and the positive and negative temperature coefficient turning point of the test object at different temperatures are further obtained; and an important basis is provided for selection of lightning arrester parameters.

The present invention discloses a double-sided heat dissipation power module with high short-circuit current tolerance, belonging to the technical field of power electronic devices. It includes two AC power terminals, DC positive / negative power terminals, a number of power semiconductor chips, two DBC substrates and a number of metal gaskets. The power module of the half-bridge structure is internally divided into a first / second commutation loop and decoupling is achieved, and the short-circuit current adopts a winding current path and a narrow conductive metal copper layer. By replacing the bonding wire with a metal gasket that realizes double-sided heat dissipation, the purpose of electrical connection between the upper and lower DBC substrates is achieved at the same time, thereby reducing the parasitic inductance of the commutation loop and suppressing voltage overshoot. The short-circuit current path adopts a narrow copper layer, and is laid out using the principle of increasing the mutual inductance of the same-direction current, which greatly increases the inductance of the short-circuit loop and suppresses the rise rate and peak value of the short-circuit current. The module can greatly improve the short-circuit current tolerance without affecting the normal operation of the power device, and ensure the reliability and stability of the device.

The utility model relates to a stacked optical module packaging device, which is based on an organic substrate (2) with multiple layers of built-in wires (1), carries out system packaging design on an optical module circuit for transmitting or receiving light, and realizes stacking arrangement of devices in the optical module circuit through the internal position and the surface position of the organic substrate (2). It is guaranteed that the glazing working face of the optical working device (6) is exposed out of the external space, and the light emitting efficiency or the light receiving efficiency of the optical working device (6) to the external environment is guaranteed; a transparent material (9) is designed to cover and wrap a window (8) formed in the surface of the organic substrate (2) and an arranged device, the device is prevented from being directly exposed, the working reliability of the device is greatly improved, when the designed packaging device is started, a loop path formed by current working forms a ring, loop inductances are mutually counteracted, and the reliability of the device is improved. The loop inductance is greatly reduced, and the working performance of the packaging device can be effectively improved.

The invention relates to a pulse power primary pulse generation assembly, in particular to a double-stacked type high-voltage large-energy-storage-density fast-discharging Marx movement, and solves the problems that an S-shaped generator of an existing primary pulse generation assembly in the technical field of pulse power is loose in structure, low in energy storage density and high in discharge efficiency. The technical problems that cascade triggering is difficult to achieve, and the difficulty of insulation and mechanical structure design is large exist in an in-line generator. The double-stacked high-voltage large-energy-storage-density fast-discharging Marx movement has the advantages that the structure is compact, the energy storage density can reach 16J / L, the working voltage can reach 3MV, the loop inductance is as small as 2.3 uH, the setting time jitter is less than 6ns, cascade expansion is facilitated, the reliability is high, triggering / charging introduction is convenient, and the service life is long (gt; 10000), which is provided by the invention.

The invention provides a control device and method of a pulse power supply system, electronic equipment and a medium. The control device comprises a load coil (1), a loop inductor (2), a switch assembly (3), a follow current assembly (4), a loop resistor (5), a capacitor bank protection assembly (9), a charging protection assembly (10), a charging control switch (11), a direct current charging power supply (12) and a plurality of capacitor banks. A load coil (1), a loop inductor (2), a switch assembly (3), a follow current assembly (4) and a loop resistor (5) are sequentially connected, a plurality of capacitor banks are respectively connected with a capacitor bank protection assembly (9), a charging protection assembly (10) and a charging control switch (11) which are in one-to-one correspondence, and a direct current charging power supply (12) is respectively connected with the load coil (1), the loop resistor (5), the plurality of capacitor banks and the charging control switch (11). Wherein the load coil (1) comprises a positive wave load coil and a negative wave load coil.

A multi-phase power converter includes a printed circuit board having a plurality of conductive layers in a spaced apart and parallel relationship. The plurality of conductive layers includes a plurality of power planes in an interleaved configuration with alternating positive and negative voltages and configured to conduct a relatively high current for supplying to a load. The multi-phase power converter also includes a plurality of switching transistors disposed on an upper surface of the printed circuit board and configured to selectively conduct the relatively high current. The conductive layers include at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting signals for controlling operation of the plurality of switching transistors. A power converter phase includes a high-side transistor, a low-side transistor, and a driver circuit disposed adjacent to the transistors.

Systems and methods relate to accounting for insertion losses and / or loop inductance during the design and layout phase of a PCB. Insertion losses are measured along signal paths, and / or loop inductance is measured along current loops, and if measured values are above predefined maximums, a PCB designer is prompted to redesign the PCB layout.

The application discloses a high-heat-dissipation high-frequency power module and a manufacturing method thereof. The high-heat-dissipation high-frequency power module comprises an embedded circuit board, at least one high-frequency capacitor and insulating heat-conducting material, and power electrodes of at least two semiconductor power devices are connected in series to form at least one power conversion bridge arm. The area ratio of the power electrode wiring of the semiconductor power device projected on the surface of the embedded circuit board to the area of the semiconductor power device is more than 60%. The power conversion bridge arm is connected in parallel with the high-frequency capacitor to realize low-loop inductance interconnection. The application can realize high-frequency and large-current characteristics, has single-face high-heat-dissipation capacity and nearly ideal double-face high-heat-dissipation capacity. Due to excellent loop processing, the loop inductance of the bridge arm formed by two semiconductor power devices per 10 square millimeters is less than 2nH or even less than 1nH, which is suitable for MHz frequency requirement and is much higher than the current mainstream frequency of less than 100KHz.

Systems and methods involve considering insertion loss and / or loop inductance during design and layout phases of a PCB. The insertion loss is measured along the signal path and / or the loop inductance is measured along the current loop, and if the measured value is above a predefined maximum value, the PCB designer is prompted to redesign the PCB layout.

The invention relates to the technical field of chip series welding, and discloses a three-phase power bridge preparation process based on a multi-row chip series welding technology, and the preparation process comprises the following steps: S1, design and layout, S2, multi-beat chip mounting, S3, reflow soldering and silver sintering, S4, housing assembly and potting, and S5, testing and screening. A wiring pattern of a copper-clad ceramic substrate is designed, then a current path is optimized, loop inductance is minimized, the current distribution uniformity between parallel chips is ensured, enough safe creepage distances and electrical gaps between different potentials are ensured, and the electrical gaps comprise DC +, DC-and output U / V / W of each phase. Optimizing chip arrangement and copper layer thickness to facilitate conduction of heat to a radiator, balancing thermal coupling, space utilization rate and process feasibility, designing low-inductance routing for a gate drive signal, and forming a required copper circuit pattern through active metal brazing; and cleaning and surface treatment are carried out to improve the reliability of subsequent welding and bonding.

The utility model provides a device for testing the characteristics of a magnetic core inductor with superposed direct-current components. The device comprises an alternating-current bridge loop and a direct-current loop, the direct current loop comprises a direct current constant current source and an inductor; the alternating current bridge loop comprises a blocking capacitor, an adjustable resistor, an adjustable capacitor and an adjustable alternating current source; the direct-current loop and the alternating-current bridge loop are connected with two ends of the magnetic core inductor to be tested to form a loop; the inductor is used for isolating the interference of the AC bridge loop on the DC loop, and the blocking capacitor is used for isolating the interference of the DC constant current source on the AC bridge loop; the direct current loop is used for providing adjustable direct current for the magnetic core inductor to be tested; the alternating current bridge loop is used for providing adjustable alternating current for the magnetic core inductor to be tested. According to the utility model, the performance of the magnetic core inductor can be tested under the superposition of different alternating-current and direct-current voltages, the test result is accurate and comprehensive, and the operation reliability and stability of the magnetic core inductor under the actual working condition are improved.

The embodiment of the utility model discloses a packaging substrate and a packaging chip. The packaging substrate comprises a core plate, at least one opening structure formed on the core plate, first electrode layers, second electrode layers and dielectric material layers, wherein the first electrode layers and the second electrode layers cover part of side walls of the opening structures, and the dielectric material layers are formed between the first electrode layers and the second electrode layers. Wherein the opening structure comprises a groove partially penetrating through the core plate and / or a through hole penetrating through the core plate, the first electrode layer and the second electrode layer are electrically isolated from each other and are opposite in position, the first electrode layer and the second electrode layer are used as polar plates of a capacitor, the dielectric material layer is used as a dielectric layer of the capacitor, and the packaging substrate can reduce the packaging size and improve the packaging efficiency. Meanwhile, loop inductance of the power distribution network is reduced, and link parasitism is improved.

The low-stray-inductance and low-thermal-resistance power module comprises a first-layer DBC structure, a second-layer DBC structure, a third-layer DBC structure and a fourth-layer DBC structure which are sequentially stacked from top to bottom and comprise the micro-channels, and chip layers are arranged between the DBC structures respectively. A heat dissipation module integrated with a micro-channel is arranged between the second-layer DBC structure and the third-layer DBC structure, and a PCB containing a decoupling capacitor is further connected between the first-layer DBC structure and the second-layer DBC structure or between the third-layer DBC structure and the fourth-layer DBC structure in an integrated mode. The power module can obviously improve the thermal performance, reduce the thermal resistance, optimize the electrical performance, reduce the loop inductance and improve the power density in unit volume; through the arrangement of the structure, the volume power density of the power module is improved by more than 35%, real three-dimensional integrated heat dissipation is realized, the system reliability is improved, and the fault-free working time is obviously prolonged.

The invention relates to the technical field of fault prediction, and particularly discloses a grid loop inductance detection method for fault prediction, which comprises the following steps of: acquiring voltage signals of a grid driving node in a plurality of continuous switching periods, converting the voltage signals into voltage values, and drawing a voltage waveform according to the voltage values; counting the number of times in the rising edge Si which is greater than a preset stable high level, and counting the number of times CS in all switching periods; counting the number of times smaller than a preset stable low level in the falling edge Xi, and counting the number of times CX in the whole switching period; calculating a rise time and a fall time based on the voltage waveform, and averaging a rise slope and a fall slope; calculating a rising index and a falling index; and determining a fault cause based on the rising index, the falling index, the number of times CS and the number of times CX. According to the invention, by counting the grid waveform characteristics of a plurality of switching periods, early fault identification and root cause distinguishing are realized, and the diagnosis accuracy and the system reliability are improved.

The application provides a low-voltage electrical product large-current synthesis test system and method, which comprises: a current source system comprising a first switching valve connected in series with a low-voltage electrical product, a first loop inductor, a first charging capacitor, a first charging system connected in parallel with the first charging capacitor, a first discharging component, a first loop voltage measuring device and a first grounding switch; a voltage source system comprising a second loop inductor connected in series with the low-voltage electrical product, a second switching valve, a second charging capacitor, a second charging system connected in parallel with the second charging capacitor, a second discharging component, a second loop voltage measuring device and a second grounding switch; the first switching valve and the second switching valve are reverse-parallel thyristor valves; the current source system, the voltage source system and a third loop current measuring device are grounded through a common point. The application can perform a low-voltage electrical product large-current synthesis test with low risk.

This invention discloses a low-inductance power module substrate terminal structure. The structure includes a first connection terminal, a second connection terminal, and at least one double-layer power module substrate. Partial areas of the first and second connection terminals are arranged with vertical overlap and form a wiring end at their front ends. The first and second connection terminals each have an extension and a connection portion at their rear ends. The double-layer power module substrate includes a first substrate connection area and a second substrate connection area. The connection portion of the first connection terminal is integrally connected to the first substrate connection area, and the connection portion of the second connection terminal is integrally connected to the second substrate connection area. This structure reduces system loop inductance, effectively reduces voltage spikes during IGBT module turn-off, reduces switching losses, avoids electromagnetic interference, and ensures the performance of the three-phase inverter drive system.

The present invention provides a PCB circuit board and diode characteristic testing system and method, comprising: a power switch tube, an adjustable loop resistor, an adjustable main loop inductor, an adjustable power supply module, a drive signal generating module, a diode to be tested, and an adjustable diode junction capacitance; one end of the power switch tube is connected to the positive electrode of the power supply module via the loop resistor and the main loop inductor, and the other end is connected to the negative electrode of the power supply module; the drive signal generating module is connected to the drive end of the power switch tube to provide a drive signal for the power switch tube; the cathode of the diode to be tested is connected to the positive electrode of the power supply module, and the anode is the connection node of the loop resistor and the main loop inductor; the diode junction capacitance is connected in parallel to both ends of the diode to be tested for adjusting the size of the diode junction capacitance. The present invention saves testing time and cost, has a simple and easy operation process, highly accurate test results, a wider range of applications, and strong practicality.

A silicon substrate providing wafer-scale routing and power distribution includes a redistribution layer structure patterned across substantially the entire wafer. The redistribution structure contains signal paths and power meshes with co-planar return conductors that reduce loop inductance and voltage droop during high-speed switching. Multiple device-mount regions distributed over the wafer connect through these paths to support direct chip-to-chip communication without an organic interposer. Reticle-stitch redundancy, embedded decoupling, and isolation trenches improve continuity and reliability. The architecture enables large-scale multi-chip assemblies with uniform impedance, reduced parasitics, and efficient power delivery across the silicon plane.

The invention relates to a primary pulse source of pulse power, in particular to a high-voltage low-inductance pulse discharge module, and solves the problems that an existing single capacitor mode is loose in structure, low in energy storage density, complex in switch structure, insufficient in multi-channel discharge stability, limited by a capacitor charging threshold value under the same load condition, low in power consumption and the like. The technical problems that the peak value of the output voltage of a single discharge unit is relatively low due to the fact that the discharge unit in a double-capacitor mode is loose in structure, low in energy storage density, large in discharge loop inductance and low in discharge speed, the discharge peak value time generally reaches hundreds of nanoseconds or even several microseconds, and a trigger system for controlling discharge of the unit is complex and high in peak value exist in the discharge unit in the double-capacitor mode. The device comprises N discharge units, each discharge unit is of a cuboid structure and comprises a closed switch, two high-voltage connecting plates, four capacitor banks and four loop connecting plates, and each capacitor bank comprises M capacitors connected in parallel.

The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a high-frequency response power triode. Firstly, the resistivity gt is adopted; the method comprises the following steps: growing an N-drift layer on an N + silicon substrate with the thickness of 1000 omega.cm, etching an isolation groove with the depth of 12 microns and the depth-to-width ratio of 5.9: 1 through ICP (Inductively Coupled Plasma), and filling a SiO2 / Si3N4 composite dielectric layer to expand a depletion layer to 18.5 microns, so that the capacitance of a collector junction is reduced to 68pF and the breakdown voltage reaches 205V. Secondly, forming an interdigital emitter on the front surface, thinning the back surface to 100 + / -2 microns, then performing laser drilling, filling through holes with pulse electroplating copper, and compressing loop inductance to 2.7 nH by a copper column array; and finally, a Ti / Ni / Au transition layer is sputtered, a diamond-copper composite substrate is subjected to hot pressing bonding, a TiC phase of 80 nm is formed on an interface, the heat conductivity reaches 635 W / m.K, and the heat resistance is reduced to 0.61 K / W. According to the invention, capacitance, inductance and thermal resistance are optimized, switching loss is reduced by 57.8%, power density is increased to 51.2 W / cm < 2 >, and the device is suitable for a MHz-level high-frequency power system.