5 results about "Loop inductance" patented technology

The application discloses a high-heat-dissipation high-frequency power module and a manufacturing method thereof. The high-heat-dissipation high-frequency power module comprises an embedded circuit board, at least one high-frequency capacitor and insulating heat-conducting material, and power electrodes of at least two semiconductor power devices are connected in series to form at least one power conversion bridge arm. The area ratio of the power electrode wiring of the semiconductor power device projected on the surface of the embedded circuit board to the area of the semiconductor power device is more than 60%. The power conversion bridge arm is connected in parallel with the high-frequency capacitor to realize low-loop inductance interconnection. The application can realize high-frequency and large-current characteristics, has single-face high-heat-dissipation capacity and nearly ideal double-face high-heat-dissipation capacity. Due to excellent loop processing, the loop inductance of the bridge arm formed by two semiconductor power devices per 10 square millimeters is less than 2nH or even less than 1nH, which is suitable for MHz frequency requirement and is much higher than the current mainstream frequency of less than 100KHz.

A silicon substrate providing wafer-scale routing and power distribution includes a redistribution layer structure patterned across substantially the entire wafer. The redistribution structure contains signal paths and power meshes with co-planar return conductors that reduce loop inductance and voltage droop during high-speed switching. Multiple device-mount regions distributed over the wafer connect through these paths to support direct chip-to-chip communication without an organic interposer. Reticle-stitch redundancy, embedded decoupling, and isolation trenches improve continuity and reliability. The architecture enables large-scale multi-chip assemblies with uniform impedance, reduced parasitics, and efficient power delivery across the silicon plane.

The utility model discloses a novel glue filling power module structure, and signal terminal installation arrangement is in the middle part of power module and extends upward, and power terminal arrangement is in the both sides of power module and extends outward, the root of signal terminal is connected on the insulating substrate of power module and drive board through pressure equipment and interference fit, the arrangement of signal terminal in the middle part of power module corresponds with drive board, and the arrangement of signal terminal is according to: there is shortening circuit loop between drive board and corresponding signal terminal, and the arrangement position of power terminal is flexibly laid out according to application demand. Through the application, built-in integrated drive board is at signal terminal, shortens circuit loop, reduces loop inductance, solves the cooperation problem of product and terminal drive board, and improves production efficiency.

A power electronic building block is provided, including capacitors, switch modules, a busbar arrangement, and at least one AC busbar. Connection points of the at least one AC busbar are arranged symmetrically along a first direction with respect to a plane perpendicularly intersecting the first direction, and the at least one AC busbar includes a hole elongated along the first direction and configured to balance one or more loop inductances between at least one AC external terminal point and the connection points. A modular multilevel converter (MMC) is also provided, including a plurality of converter arms each including at least one sub module formed by the PEBB.

The application provides a method, system, device and medium for impedance optimization of complex single-ended TSV, comprising: performing quasi-static three-dimensional electromagnetic simulation on a target TSV loop to obtain total loop inductance and total capacitance of a TSV structure; constructing a transmission line profile model connected at both ends of the TSV to obtain unit length capacitance and unit length inductance of a transmission line at both ends of the TSV; based on the total loop inductance and the total capacitance of the TSV structure and the unit length capacitance and the unit length inductance of the transmission line at both ends of the TSV, obtaining loop inductance and capacitance of an intermediate TSV part, and calculating characteristic impedance of the target TSV loop based on the loop inductance and the capacitance of the intermediate TSV part; comparing the characteristic impedance of the target TSV loop with target characteristic impedance, and performing impedance matching optimization on an existing structure to obtain a new structure after optimization; the application can greatly reduce the optimization design time of complex single-ended TSV in 2.5D and 3D packaging products, and improve product design efficiency.