6366 results about "Inverter" patented technology

A static random access memory (SRAM) device and a method for manufacturing the same are disclosed. In the SRAM device including a flip-flop circuit including two access transistors and a pair of inverters, connection lines for connecting the inputs and outputs of the inverters, and a word line, power supply lines and bit lines are formed of a metal interconnection. The resistance of interconnection can be reduced and the SRAM device manufacturing process can be performed along with CMOS standard logic manufacturing process.

A motor driving apparatus has a loss-of-synchronism monitoring circuit that monitors the rotation of a rotary machine such as a brushless DC motor to detect a sign of transition to a state of loss of synchronism. When the sign is detected, an energization control circuit temporarily stops driving of the rotary machine to bring it into a free running state, and thereafter carries out control so as to resume driving of the rotary machine. Further, the motor driving apparatus has an inverter and a drive control circuit that controls switching operation of the inverter based on rotation of the rotary machine.

A method and apparatus for converting DC input power to AC output power. The apparatus comprises an input capacitor, a DC-AC inverter, a burst mode controller for causing energy to be stored in the input capacitor during at least one storage period and the energy to be drawn from the input capacitor during at least one burst period, wherein the AC output power is greater than the DC input power during the at least one burst period; a first feedback loop for determining a maximum power point (MPP) and operating the DC-AC inverter proximate the MPP; and a second feedback loop for determining a difference in a first power measurement and a second power measurement, producing an error signal indicative of the difference, and coupling the error signal to the first feedback loop to adjust at least one operating parameter of the DC-AC inverter to drive toward the MPP.

A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feed back loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

Each of three-phase arm of an inverter has first and second switching elements connected in series together at a connection point to the corresponding phase coil of the three-phase motor. Control device turns on the first switching element of the i-th (i is a natural number smaller than four) for a predetermined time period, and determines that the second switching element of the i-th arm has a short fault, when an overcurrent exceeding a predetermined threshold is detected within the predetermined time period. The predetermined time period is shorter than a time period from a time point of turning on the first switching element of the i-th arm to a time point of attaining the predetermined threshold by a current flowing through a path extending from a power supply line through the second switching element of the remaining arm other than the i-th arm to a ground line.

The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.

The invention relates to a pulse-width modulation (PWM) output method for solving the problem of nonuniform heating of a bridge arm switch of a single-phase full-bridge inverter circuit. The PWM output method is characterized in that two bridge arms use the modulation wave period T as an interval for alternately outputting PWM waves and square wave voltage. The problem of nonuniform heating caused by great work frequency differences of two bridge arm switches is solved, the temperature of an overheat switch is obviously reduced, insulated gate bipolar translator (IGBT) power switch device faults caused by overheat is effectively overcome, the reliability of a switch device is favorably improved, and the service life is prolonged.

When a rectangular wave voltage control mode is selected, a control apparatus estimates the output torque of an alternating-current motor based on the outputs of a current sensor and a rotation angle sensor, and executes torque feedback control by adjusting the phase of rectangular wave voltage based on the difference between the torque estimated value and a torque command value. The control apparatus executes a switching interruption that outputs a control command to a switching element of an inverter every 60 degrees of electrical angle, and executes an angle interruption that samples the phase currents of the alternating-current motor based on the output of the current sensor and converts those phase currents into a d-axis current and a q-axis current every predetermined electrical angle that is set beforehand. The control apparatus for the alternating-current motor then sets the predetermined electrical angle such that the number of angle interruptions between switching interruptions varies according to the rotation speed of the alternating-current motor.

An inductance parameter identification method of a synchronous motor and an implementation system thereof are provided. The method comprises: applying a three-phase balance high frequency voltage or current signal to the synchronous motor; sampling a feedback high frequency current or voltage of the synchronous motor; extracting positive sequence and negative sequence component amplitude of the feedback high frequency current or voltage which has the same frequency of the injecting voltage or current; and calculating to get d-axis inductance Ld and q-axis inductance Lq of the synchronous motor. Identification of the d-axis inductance and q-axis inductance of the synchronous motor can be implemented more accurately on a general inverter on the basis of non-increase of hardware cost. The method and system have the following advantages of implementing easily, not high demand for the motor feedback current sampling accuracy, and controlling easily for the frequency and amplitude of the high frequency voltage signal injected into the motor, and identifying to get the d-axis inductance and q-axis inductance of the motor directly no matter the motor shaft is in a free state, or in a hold tight stage, which do not affect accuracy of identification.

A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.

The subject matter of the invention is an inverter with a housing (1) having a cooling unit (2) for cooling the electronic and/or electric components (4, 5, 5a) of the inverter, the housing (1) of the inverter comprising at least two chambers, said two chambers (7, 8) being separated by a wall (6) for receiving the lossy components (4, 5, 5a), said components (5), if they comprise cooling bodies (4), being located on the one side of the wall in the one chamber (7) with the cooling bodies (4) being located on the other side of the wall (6) in the other chamber (5) and, if the very electric or electronic component to be cooled (5a) has a high protection grade, said component (5a) being located in the other chamber (8), preferably on the wall side of the wall (6) of the other chamber (8), said other chamber (8) comprising the cooling unit (2).

The invention discloses a resolution method and a resolver for signals of a rotating transformer. The method comprises the steps of: acquiring a rotating angle signal of a motor and establishing a sine table, sampling a current low-frequency sinusoidal signal and a current low-frequency cosine signal, dividing the angle position of a rotor into four quadrants, and determining the quadrant which the position of the rotor belongs to; and performing the lookup of the sine table according to the low-frequency sinusoidal signal and the position of the rotor, and judging the rotation direction of the rotor. A sinusoidal excitation signal generator is connected with the rotating transformer and differential signal converters, and a sinusoidal differential signal feedback by the rotating transformer passes through the differential signal converter, then is input into a precision absolute value adder along with a reference signal, passes through a low-pass filter and then is input into a digital signal processor; and a cosinoidal differential signal feedback by the rotating transformer passes through another differential signal converter, then is input into the precision absolute value adder along with the sinusoidal excitation signal which passes through a phase inverter, passes through the low-pass filter and then is input into the digital signal processor. The resolution method and the resolver greatly reduce the cost, and can perform accurate sampling and conversion on input signals.

The invention relates to a master-slave control strategy microgrid-based main power supply double-mode running control method which belongs to the technical field of distributed power generation. The method comprises the following steps of: when switching from an independent running mode to a grid-connected running mode, switching a control manner from voltage and current double-ring control intocurrent closed ring control and memorizing a voltage ring output result before switching as switched current ring reference input; memorizing a current ring output result before switch as an initial value of a switched current ring output result; when switching from the grid-connected running mode into the independent running mode, switching the control manner from current closed ring control into voltage and current double-ring control and memorizing a current ring reference input command before switch as an initial value of a switched voltage ring output result; and memorizing the current ring output result before switch as the initial value of the switched current ring output result. The control method provided by the invention can ensure that all output quantities of a two-way inverter can not be mutated, and the microgrid system transient process is smoother.

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

A high-speed sense amplifier includes a pair of cross-coupled inverters coupled to intermediate nodes and then to differential inputs nodes by a control circuit. The intermediate nodes are coupled together by a accelerator transistor that forms a current path when the sense amplifier is placed in a sensing state to provide parallel discharge paths for one or the other of output nodes. During precharge, the accelerator transistor operates to equalize the intermediate nodes to ready them for the next sense phase.

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a “standard” triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10–50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Proposed is a parallel inverter drive system including includes a plurality of inverter drives connected in parallel with each other, in which each inverter drive includes a switch; a PWM controller connected to the switch for controlling switching operations of the switch device according to a duty cycle signal; and a circulating current suppressor for collecting current information associated with the current of each inverter drive and a summation current, and generating an index according to the collected current information and the desired circulating current quantity. A zero-sequence voltage is generated for each phase of a three-phase voltage command according to the index and the voltage command and the operating mode of the inverter drive, thereby injecting the zero-sequence voltage into the voltage command with a feed-forward configuration so as to fix the voltage command. The PWM controller can generate the duty cycle signal according to the fixed voltage command.

The invention discloses a single event radiation effect resistant reinforced latch circuit. The single event radiation effect resistant reinforced latch circuit comprises a first transmission gate unit, a second transmission gate unit, a Schmitt inverter, a conventional input separation inverter, a first input separation clock-controlled inverter, a second input separation clock-controlled inverter, a delay circuit and a MullerC unit circuit. When the single event radiation effect resistant reinforced latch circuit operates under a transparent mode, a hysteresis effect of the Schmitt inverter and a delay difference of a latch interior unit are effectively used and SET pulses from a combinational logic unit are shielded through the MullerC unit; when the single event radiation effect resistant reinforced latch circuit operates under a latch mode, any interior node generating SEU due to the irradiation effect can be recovered through states of other nodes through a DIC unit structure having a self-recovery capability and correct output of the latch is guaranteed; accordingly the single event radiation effect resistant reinforced latch circuit has the advantages of effectively eliminating the radiation effect influences and being applicable to a clock gating circuit and small in power consumption and area costs.

In an inverter circuit, more particularly in a single-phase inverter, soft switching is performed with a simple configuration to prevent switching loss of a switching element. A resonance circuit is configured by a resonant capacitor provided on the power supply side of a bridge circuit constituting a single phase inverter, a resonant inductor provided on the output side of the bridge circuit, and the bridge circuit. A resonance current passing through the resonance circuit allows zero voltage switching (ZVS) and zero current switching (ZCS) to be implemented at the rising time of main switching elements constituting the bridge circuit, and the zero voltage switching is implemented by means of zero voltage of the resonant capacitor at the falling time of the main switching elements constituting the bridge circuit.

The invention provides a shift register, a grid driving device and a display device. The shift register comprises a latch, a transmission gate, a first thin film transistor, a second thin film transistor, a third thin film transistor and a first inverter, wherein a grid of the first thin film transistor is connected with a reset terminal of the shift register, a drain of the first thin film transistor is respectively connected with a drain of the second thin film transistor and an input terminal of the latch, a grid of the second thin film transistor is connected with an input terminal of theshift register, a grid of the third thin film transistor is connected with an inverted output terminal of the latch, a drain of the third thin film transistor is connected with an input terminal of the first inverter, an output terminal of the transmission gate is connected with the drain of the third thin film transistor, an input terminal of the transmission gate is connected with a clock signal input terminal, the drain of the third thin film transistor is connected with a normal phase output terminal of the shift register, and an output terminal of the first inverter is connected with an inverted output terminal of the shift register. The shift register can realize signal shift by the aid of one latch.

The invention discloses a fixed-gain self-excited non-contact resonant converter and a control method thereof, belonging to the field of electric energy conversion. The fixed-gain self-excited non-contact resonant converter comprises a self-excited non-contact resonant converter main circuit, a secondary side current detection circuit and a driving signal generation circuit. Detected current is set according to the compensation method of a resonant converter: for series/series and parallel/series compensation circuits, the secondary side current of a non-contact transformer is detected, and for series/parallel compensation circuits, the input current of a secondary side rectifier bridge is detected. The detected current is detected by the secondary side current detection circuit, a detection signal is isolated and fed back to a primary side through the driving signal generation circuit, and phase compensation is conducted to accurately detect the phase information of the secondary side detected current. According to a found characteristic that the phase of the secondary side detected current at the fixed gain position of the non-contact resonant converter is the same as the phase of square wave signals at the middle point of an inverter bridge arm in the main circuit (1), the detected secondary side current signals are converted into the driving signals of the main circuit to realize self-excitation control. On one hand, a real-time response can be made to the parameter change of the non-contact transformer; and on the other hand, the output of the non-contact resonant converter can be ensured to be stable when a load is changed.

The invention relates to an inverter and a startup method thereof. The inverter comprises a direct-current side switch (20), a bus capacitor assembly (30), a power module (40), an output filter assembly (50), a grid-connected contactor (60) and an alternating-current breaker (70) which are connected in sequence in a cascaded manner, wherein the direct-current side switch (20) is connected to a direct-current side input (10), and the alternating-current breaker (70) is connected to a power grid (80); and the inverter further comprises a soft startup device (110), wherein the input side and the output side of the soft startup device (110) are respectively connected with the direct-current side input (10) and the power module (4). According to the startup method of the inverter, because direct-current side soft startup is adopted, the startup logic can be simplified, redundancy can be reduced, current impact on a bus capacitor and an alternating-current output filter capacitor, and impact on the power grid are reduced, and thus all pieces of equipment of the inverter system can be protected.