29 results about "Microelectronic circuits" patented technology

The invention discloses a current-steering DAC (Digital-to-Analog Converter) architecture, which relates to a microelectronic circuit technology and comprises a differential dual decoding module, a multiplexer network, a switch driving circuit array and a current source array, the differential dual decoding module comprises two decoding units with consistent structures, namely a decoding unit I and a decoding unit II; the decoding unit I is provided with an input signal input end, the decoding unit II is provided with an inverted input signal input end, the decoding unit is provided with a low-order decoding signal output end, a second decoding signal output end and a third decoding signal output end, the low-order decoding signal output end is connected with the input end of the switch driving circuit array, and the third decoding signal output end is connected with the input end of the switch driving circuit array. The second decoding signal output end and the third decoding signal output end are respectively connected with the input end of the switch driving circuit array through the multiplexer network, and the multiplexer network is also provided with a shift control signal input end. According to the invention, the problems of transmission delay and large loss of high-voltage transmission under high frequency are reduced, and the conversion rate is improved.

The invention discloses a movable package, a testing device and a testing method. The movable package includes: a movable package body including a first part and a second part for holding a substrate therebetween, the substrate carrying a microelectronic circuit and having a plurality of substrate terminals connected to the microelectronic circuit; a plurality of movable packaging contacts, the contacts are arranged on the second part, and the movable packaging contacts are matched with the substrate terminals so as to be in contact with the substrate terminals; a fixing system; and a first electrical interface on the movable package and connected to the movable package contact for connecting to a second electrical interface on the frame when the movable package is removably held by the frame.

The performance of an adaptive microelectronic circuit is at least partly configurable by selecting a value of an operating parameter. On processing paths, data inputs of register units are coupled to outputs of respective logic units for temporarily storing output values of said logic units. A plurality of timing event monitors respond to a digital value at a data input of a monitored register unit changing later than an allowable time limit by generating a timing event observation signal. The plurality of timing event monitors form a plurality of monitor groups, each monitor group being coupled to a branch of a triggering signal tree for coupling a monitor-group-specific triggering signal to the monitor group independently of other monitor groups. A control unit selectively allows or disables the propagation of the respective triggering signals into said branches of the triggering signal tree.

The application provides a manufacturing method of glass direct copper clad circuit, relates to the technical field of microelectronic circuit manufacturing, and comprises the following steps: S01, copper foil surface planarization: the copper foil is adhered to a UV photosensitive adhesive film, and the surface of the adhered copper foil is ground; after the surface of the copper foil is ground to reach a target roughness, the copper foil is cleaned and dried; S02, laminated static pressure: a glass substrate, the UV photosensitive adhesive film with the adhered copper foil and a carrier plate are sequentially laminated and fixed, vacuum is drawn and sealed, static pressure is applied to the formed sealed body, and a structure to be welded is obtained; and S03, laser selective welding: an ultrashort pulse laser and a short pulse are combined, and multiple compound scans are performed by using an energy gradient, so that the problem that an interface gap cannot be effectively reduced and the interface is easy to be ablated when a laser is used for welding to manufacture a glass copper clad circuit is solved, and the interface fusion capacity between the copper foil and the glass is improved.

The utility model discloses a laser device with a spraying function. The laser device comprises a base assembly, a first power supply assembly, a second power supply assembly, a laser assembly and a spraying assembly. The laser assemblies are installed on the spraying assembly to form laser spraying units, and at least two laser spraying units are installed in the base assembly. The first power supply assembly and the second power supply assembly are both arranged in the base assembly, the first power supply assembly is used for supplying power to the laser assembly, and the second power supply assembly is used for supplying power to the spraying assembly. According to the utility model, the delicate miniaturization, microminiaturization and electronization technology and the safe microelectronic circuit control unit are adopted, and laser and spray are superposed together, so that laser illumination can be applied to common life, especially birthday and wedding festive activities, and the festive atmosphere of the application scene is increased.

A quantum technological, micro-optical, micro-electronic or photonic system, includes a planar substrate, a microelectronic circuit which is part of the substrate; at least one electrical component comprised within the microelectronic circuit, a micro-optical subdevice which is part of the planar substrate, one or more nanoparticles being diamonds; and a colloidal film, wherein the one or more nanoparticles are comprised within the first portion of the colloidal film. The colloidal film includes the one or more nanoparticles. The system further comprises at least one light-emitting electro-optical component. The light-emitting electro-optical component interacts with the electrical component via the micro-optical subdevice. The one or more nanoparticles include two NV centers. The at least two NV centers interact with one another in a physically observable manner. The interaction between the light-emitting component and the electrical component takes place with involvement of the at least two NV centers.

A method of making a universal implantable integrated circuit medical device platform having integral and monolithic circuit traces. The platform allows for implanting into a mammalian body single and multi-functional interface devices for sensing, monitoring stimulating and / or modulating physiological conditions within the body. Microelectronic circuitry may be integrated onto the platform or may be joined as modular components to the platform.

The invention relates to the technical field of microelectronic circuits, in particular to an intelligent information processing system and method of a microelectronic circuit. The method comprises the following steps: acquiring an electronic device information set, and based on the electronic device information set, analyzing the position deviation influence of a thermal-electric multi-physical coupling effect on the position of a microbubble in a middle layer of the multilayer circuit board to obtain dynamic thermoelectric coupling characteristic information; based on the dynamic thermoelectric coupling characteristic information, analyzing the evolution stage of the microbubble under the dynamic multi-field coupling influence to obtain a multi-stage evolution result; and based on the multi-stage evolution result, evaluating the micro-bubble potential hazard degree corresponding to each evolution stage, and outputting a micro-bubble risk report. Errors caused by a single physical field or neglecting interaction are avoided, reliability of circuit risk assessment is guaranteed, service life and stability of a microelectronic circuit are enhanced, preventive maintenance is assisted, adverse effects of microbubbles on the circuit are reduced, and maintenance cost and fault probability are reduced.

Embodiments of the present application provide an integrated circuit, chip, and electronic device, relating to the field of microelectronic circuit technology, and capable of improving integrated circuit failures caused by electrostatic discharge. The integrated circuit includes a substrate and a transistor disposed on the substrate; the gate of the transistor is coupled to a first terminal of a switching device, and the second terminal of the switching device is coupled to a ground terminal; the switching device is configured to be in an on state or an off state under the control of a control signal received at a control terminal; in the on state, the switching device transmits the electrostatic voltage of the gate of the transistor to the ground terminal; or, in the off state, the switching device disconnects the gate of the transistor from the ground terminal.

This invention provides a solvent-free method for preparing nonlinear optical micro-crystal arrays. A substrate is placed on top of a silicon pillar template. A raw material tank is positioned on one side of the upper part of the silicon pillar template, and a through-hole is positioned on one side of the substrate, with the raw material tank and through-hole corresponding in position. Powdered organic small molecules are added to the raw material tank through the through-hole. The temperature is increased; when the temperature exceeds the melting point of the organic small molecules, a sandwich structure is formed consisting of the substrate, the melt of the organic small molecules, and the upper surface of the silicon pillar. Driven by capillary force, the melt flows along the top of the silicon pillar until it covers the entire surface of the silicon pillar template. The temperature is then decreased; when the temperature falls below the solidification point of the organic small molecules, it is further cooled to room temperature, opening the sandwich structure and obtaining a nonlinear optical micro-crystal array on the substrate. The processing precision of the micro-crystal array in this invention is controlled by the size of the silicon pillar, achieving a precision of 1 μm. This provides a new approach for the array-based preparation of nonlinear organic microcrystals and their application in nonlinear optics and microelectronic circuits.

A microelectronic circuit includes a plurality of logic cells and register circuits arranged in a plurality of processing paths, and a plurality of monitoring cells associated with individual ones of the processing paths. Each monitoring cell is configured to generate an observation signal in response to abnormal operation of the individual processing path. Each of the plurality of logic cells belongs to one of a plurality of delay levels, depending on the amount of delay that may be generated. The delay levels include first, second, and third levels, wherein the first level covers logic cells that may generate the longest delay, the second level covers logic cells that may generate shorter delays than the first level, and the third level covers logic cells that may generate shorter delays than the second level. At least some of the plurality of processing paths include logic cells that belong to the second level but do not have monitoring cells. At least some of the plurality of processing paths include logic cells that belong to the third level but have monitoring cells associated with them.

The invention belongs to the technical field of hardware security and microelectronic circuits, and particularly discloses a concealable PUF (Physical Unclonable Function) device based on a memristor array and an operation method of the concealable PUF device. In the first aspect, the memristor array is completely kept in a high-resistance state as a hidden state, and part of units are activated in a short time under the challenge effect, so that a hidden / activatable working mode is realized, the static power consumption is effectively reduced, and the resistance to side channel detection and physical analysis is remarkably improved; on the second aspect, a memristor SET voltage threshold value is used as an entropy source, so that a selected unit generates different switching results in a probabilistic mode under a fixed write pulse, high-randomness response from device microstructure difference is formed, and unpredictability and modeling attack resistance are improved; and thirdly, a digital reading structure formed by the reference current source and the current comparator is introduced, so that stable and low-power-consumption logic response can be obtained without a complex analog circuit.

The utility model relates to an integrated circuit burn-in board of a Darlington transistor array series. The integrated circuit burn-in board comprises a chip, a filter capacitor, a plurality of input resistors, a plurality of output resistors, a plurality of digital signal inputs, a grounding end and a direct-current stabilized power supply, the device is matched with an integrated circuit high-temperature dynamic aging system for use, is suitable for high-temperature dynamic aging tests of microelectronic circuits such as various digital, analog and digital-analog hybrid integrated circuits, SOC circuits, microprocessors, memories and the like, and provides a direct-current stabilized power supply, 64-path digital signals, 4-path analog signals and an environment required by the aging test for the aging test of semiconductor components.

The activation of processing paths in a microelectronic circuit is achieved by providing one or more input messages (101, 102, 103) to decision software (104) and executing the decision software (104) to determine whether one or more of the processing paths of the microelectronic circuit will be activated with a test signal (112). The decision to activate the processing path with the test signal results in continued activation of one or more of the processing paths with the test signal, and the monitoring of whether a timing event occurs on the one or more activated processing paths. A timing event is a change in the digital value at the input of the corresponding register circuit on the activated processing path, occurring after an allowable time limit defined by the trigger signal of the corresponding register circuit.

The application discloses a current steering DAC architecture, and relates to microelectronic circuit technology, comprising a differential pair decoding module, a multiplexer network, a switch driving circuit array and a current source array; the differential pair decoding module comprises two decoding units with consistent structures, which are decoding unit one and decoding unit two; the decoding unit one is provided with an input signal input end, the decoding unit two is provided with an inverted input signal input end, the decoding unit is provided with a low bit decoding signal output end, a second decoding signal output end and a third decoding signal output end, the low bit decoding signal output end is connected with the input end of the switch driving circuit array, the second decoding signal output end and the third decoding signal output end are respectively connected with the input end of the switch driving circuit array through the multiplexer network, and the multiplexer network is further provided with a shift control signal input end. The application reduces transmission delay and high voltage transmission loss under high frequency, and improves conversion rate.

An apparatus is described for burn-in and / or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

The invention relates to the field of flexible microelectronic circuits, and provides a temperature compensation type anti-crosstalk piezoresistive sensor array acquisition circuit and a control system. The acquisition circuit comprises a row driving circuit which is connected with a driving voltage and gates a specific row; the piezoresistive sensing array is used for performing temperature compensation on the output voltage of the row driving circuit; the resistive sensing unit detection circuit is used for keeping the output non-gating column line voltage at zero; the temperature compensation voltage adder is used for summing a temperature compensation voltage signal output by the piezoresistive sensing array and an output voltage signal of the resistive sensing unit detection circuit; the multipath selection circuit is respectively connected with the temperature compensation voltage adders and the voltage follower, and the multipath selection circuit is used for gating output voltage signals of the output temperature compensation voltage adders of a specific column and carrying out front and back stage isolation through the voltage follower; and the phase inverter is used for converting the output voltage signal of the voltage follower into positive voltage and outputting the positive voltage to the singlechip ADC acquisition module.

The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.

The microelectronic circuit may include at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window. The microelectronic circuit may also include a control input for adjusting at least a duration of the timed event monitoring window.

The embodiment of the application provides an integrated circuit, a chip and an electronic device, relates to the technical field of microelectronic circuits, and can improve the failure of the integrated circuit caused by electrostatic discharge. The integrated circuit comprises a substrate and a transistor arranged on the substrate; the gate of the transistor is coupled with the first end of an electrostatic discharge wire, and the first active electrode of the transistor is coupled with the second end of the electrostatic discharge wire, wherein the first active electrode of the transistor is also coupled with a ground terminal; wherein the electrostatic discharge wire is used for outputting the electrostatic voltage of the gate of the transistor to the ground terminal; or when the integrated circuit is located on a chip, the electrostatic discharge wire is disconnected.

A microelectronic circuit package may include one or more operative channels, each of the one or more operative channels containing a reactive material, and a seal covering at least a portion of the one or more operative channels. At least one of the one or more operative channels has a maximum width of less than about 100 microns. The seal is non-reactive with the reactive material. Also disclosed are methods of manufacturing a microelectronic circuit package comprising at least one operative channel containing a reactive material.

The invention belongs to the field of flexible microelectronic circuits, and provides a temperature compensation type anti-crosstalk capacitive sensing array acquisition circuit and a control method, and the circuit comprises an excitation signal driving source and a signal detection module. The excitation signal driving source comprises a main control unit, and the main control unit generates row gating signals and column gating signals; the capacitive sensing array performs temperature compensation based on the row gating signal to obtain a temperature compensation voltage signal; the signal detection module obtains capacitance signals of capacitance sensing units in columns in the capacitance type sensing array and converts the capacitance signals into modulation capacitance voltage signals. The temperature signal modulation module converts the temperature compensation voltage signal of the corresponding column into a modulation temperature voltage signal according to the column gating signal of the main control unit; the modulation capacitor voltage signal and the modulation temperature voltage signal are combined into a multiplexing signal through an analog adder, the multiplexing signal is transmitted to an upper computer through a main control unit for demodulation, and a compensated pressure signal is obtained; accurate temperature compensation and signal crosstalk suppression can be realized.

The invention relates to quantum technology, micro electro-optical or photonic systems, methods of production and uses. The quantum technology, micro electro-optical or photonic system comprises: a planar substrate (Sub), where the planar substrate (Sub) is a semiconductor crystal comprising a microelectronic circuit; wherein the system further comprises: a partial region of a colloidal film (FM), the partial region of the colloidal film (FM) having at least one further crystal, the further crystal comprising a color center (FZ), and wherein the further crystal is mechanically connected to the planar substrate (Sub) by means of the colloidal film (FM).

This application discloses a movable package, a testing apparatus, and a testing method. The movable package includes: a movable package body comprising a first component and a second component for holding a substrate therebetween, the substrate carrying microelectronic circuitry and having a plurality of substrate terminals connected to the microelectronic circuitry; a plurality of movable package contacts on the second component, the movable package contacts mating with the substrate terminals to contact the substrate terminals; a fixing system; and a first electrical interface on the movable package body and connected to the movable package contacts, for connecting to a second electrical interface on the frame when the movable package body is removably held by a frame.

Integrated Circuit (IC) wherein the integrated circuit (IC) includes a one-wire test interface for testing this integrated circuit (IC), wherein the single-wire test interface has exactly one test data bus connection (TEST) for one data line (TOW) and wherein the integrated circuit (IC) has a positive supply voltage connection (VDD) and wherein the integrated circuit (IC) has a negative supply voltage terminal (GND) as a reference potential terminal for a reference potential line (GND) at a reference potential (V DIS ) exhibits and where, in the following, the term data line level refers to the data bus voltage between the potential of the data line (TOW) minus the reference potential (V). DIS ) the reference potential line (GND), wherein the integrated circuit (IC) is configured to be connected to a power source via a positive supply voltage terminal (VDD) and a reference potential line (GND), and wherein the integrated circuit (IC) is configured to be supplied with electrical energy via the positive supply voltage terminal (VDD) and the reference potential line (GND), and wherein the integrated circuit (IC) is configured to detect data line levels that are in a first voltage range (V B1 ) or in a second voltage range (V B2 ) or in a third voltage range (V B3 ) or in a fourth voltage range (V B4 ) relative to the reference potential (V DIS ) of the reference potential line (GND) and where a total voltage range constitutes the first voltage range (V B1 ) and the second voltage range (V B2) and the third voltage range (V B3 ) includes and where the fourth voltage range (V B4 ) differs from the total voltage range and where the first voltage range (V B1 ) and the second voltage range (V B2 ) and the third voltage range (V B3 ) do not overlap and wherein the integrated circuit (IC) is configured such that a data line level in the total voltage range activates a test state of the microelectronic circuit, and wherein the integrated circuit (IC) is configured to provide a data line level in the fourth voltage range (V B4 ) deactivated the test state of the microelectronic circuit, and wherein the integrated circuit (IC) is configured to provide a data line level in the first voltage range (V B1) signals a first logical value to the microelectronic circuit (IC), and the integrated circuit (IC) is configured to provide a data line level in the second voltage range (V B2 ) signals a second logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is configured to provide a data line level in the third voltage range (V B3 ) signals a third logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is configured such that a temporal sequence of first logic values ​​and / or second logic values ​​and / or third logic values ​​represents a test signal sequence for the integrated circuit (IC), and wherein the integrated circuit (IC) is configured so that this test signal sequence controls a test of the microelectronic circuit (IC) when the microelectronic circuit (IC) is in a test state.

The invention discloses a method for enhancing domain wall current in a ferroelectric film, which comprises the following steps: preparing a BiFeO3 film containing oxygen vacancies through a pulsed laser deposition method; a lattice structure of the film is obtained through an X-ray diffraction method; pFM is utilized to characterize the thin film, and the morphology and spontaneous domain structure of the thin film are obtained; characterizing the thin film by means of CAFM, and observing whether domain wall current exists or not; applying a direct-current voltage to the PFM probe, scanning the film from two sides to the middle in opposite directions, and forming a head-to-head domain wall in the middle area by using an electric field at the tail part of a needle tip; domain wall current is obtained through CAFM characterization, and it is proved that construction of the head-to-head domain wall is an effective method for enhancing the domain wall current. A head-to-head charged domain wall is constructed by using a needle point electric field, the method is simple and effective, and the conductive channel can be used for wiring in a microelectronic circuit and ferroelectric memory devices such as a memristor.

The invention relates to the technical field of electronic circuit boards, and discloses a device for double-sided welding of a microelectronic circuit board, which comprises a working table, a groove is formed in the top of the working table, support legs are fixedly connected to the bottom of the working table, and a transmission part is arranged on the surface of the working table; and the conveying part comprises a groove frame, the bottom of the groove frame is fixedly connected with the top of the working table, a driving rod is rotationally connected to the top of the inner wall of the groove frame, a groove belt is meshed with the surface of the driving rod, and a conveying belt is fixedly connected to the surface of the groove belt. The groove belt drives the conveying belt to rotate when rotating, the conveying belt pushes the electronic circuit board to slide in the groove frame when rotating, the conveying belt can convey the electronic circuit board into the stabilizing component to be extruded and fixed, and after the electronic circuit board is placed in the groove frame, the conveying belt can convey the electronic circuit board. And the convenience of the electronic circuit board during welding and feeding is improved.

A microelectronic circuit may comprise at least one timing event detector circuit configured to generate a timing event observation signal as a response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window. The microelectronic circuit may further comprise a control input for adjusting at least a duration of the timing event monitoring window.

Methods, systems, and apparatus, including microelectronic circuits and processors are described for estimating energy consumption during a sampling window. The processor is divided into multiple processor cores, which are each sub-divided into processor units. The units can perform operations from a set of operations. Based on the number of times each unit has performed a particular operation during a sampling window, an estimate of the energy consumed by that unit for that sampling window is calculated. By summing the estimated energy consumption of many units on a core and many cores of the entire system, an energy consumption estimate is prepared for the sampling window. Other power parameters may be calculated from a sampling window duration and the energy consumption estimate. If a power parameter exceeds a threshold, action may be taken to alter operation of the microelectronic circuit.