4665 results about "Ion implantation" patented technology

The invention relates to a backside illuminated image sensor and a preparation method thereof, and electronic equipment, and relates to the technical field of integrated circuits, the backside illuminated image sensor comprises a substrate, and photodiodes and laminated target isolation structures which are located on a first surface of the substrate, are alternately arranged along a first direction parallel to the first surface, and extend towards the substrate; the substrate internally comprises a plurality of trench isolation structures which extend into the substrate through the first surface and are arranged at intervals in the first direction; the trench isolation structures and the laminated target isolation structures right above the trench isolation structures are arranged in a one-to-one manner; the laminated target isolation structure comprises isolation parts and insulation parts which are sequentially and alternately laminated along a second direction deviating from the substrate; the photodiode comprises at least two photosensitive layers which are sequentially stacked in the second direction, the longitudinal sections of the photosensitive layers are T-shaped, one photosensitive layer makes contact with the first surface of the substrate, substrate damage caused by ion implantation can be avoided, and meanwhile the photoelectric conversion efficiency and the quantum efficiency are improved.

The invention provides a planar gate silicon carbide VDMOS capable of improving short circuit reliability and a preparation method, and the preparation method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming drain electrode metal; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a current sharing layer; forming a barrier layer on the drift layer, and performing etching and ion implantation to form a P-type well region and a low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region and a P-type source region are formed; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a first gate dielectric layer; depositing to form a second gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; and re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, and removing the barrier layer to complete preparation. And the heat conduction capability and the thermal reliability of the insulating medium are effectively improved.

The invention provides a low-on-resistance trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation to form a low-resistance region; forming a barrier layer, etching, performing ion implantation, and forming a P + well region, a P-type well region and an N-type source region; a barrier layer is formed again, and the insulating medium is etched and deposited; forming a barrier layer again, etching and depositing metal, and forming a suspension gate; forming a barrier layer again, etching the barrier layer, and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the barrier layer is re-formed, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the P-type well region, metal is deposited, a source electrode metal layer is formed, the barrier layer is removed, preparation is completed, gate-drain capacitance is reduced, the switching speed of the device is increased, and switching loss is reduced.

The invention discloses a vertical cavity surface emitting laser and a preparation method thereof. The preparation method of the vertical cavity surface emitting laser comprises the following steps: growing a semiconductor epitaxial structure with a lower reflecting mirror layer, an active layer and an upper reflecting mirror layer which are sequentially arranged from bottom to top on a substrate to form a wafer; depositing an ohmic metal layer, and etching the semiconductor epitaxial structure until the lower reflector layer is exposed to form a plurality of grooves; performing ion implantation on the side wall and the bottom of each groove to form a plurality of insulating regions; the insulating region comprises a side wall insulating region in contact with the side wall of the groove and a bottom insulating region in contact with the bottom of the groove; the depth of the side wall insulation region is greater than that of the groove; the semiconductor epitaxial structure is jointly divided into a plurality of semiconductor units which are mutually isolated on the active layer by the grooves and the insulating regions; and each semiconductor unit comprises a lower reflecting mirror, an active region, an upper reflecting mirror and an ohmic electrode which are sequentially arranged from bottom to top. According to the embodiment of the invention, the robustness of the vertical cavity surface emitting laser can be improved.

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a current sharing layer, a body region, a P-type well region and an N-type source region are formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; a barrier layer is formed again, and etching and deposition are carried out to form a gate dielectric layer; the preparation method comprises the following steps: forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, removing the barrier layer, and completing the preparation. The gate reliability of the device can be effectively improved, and the follow current loss and reverse recovery speed of a body diode can be effectively improved.

The embodiment of the invention provides a semiconductor structure, a manufacturing method of the semiconductor structure and an image sensor, and relates to the technical field of semiconductor manufacturing. The semiconductor structure comprises a substrate and a photoelectric function layer formed on the surface of the substrate, the photoelectric function layer comprises a photoelectric sensing layer and an isolation structure used for dividing the photoelectric sensing layer into a plurality of photoelectric sensing areas; the photoelectric sensing area comprises a plurality of photoelectric sensing material layers which are arranged in a stacked mode and a cross-layer doping structure which extends in the normal direction of the photoelectric sensing layers. The doping type of the cross-layer doping structure is the same as that of the photoelectric sensing layer; wherein the cross-layer doping structure is formed through an ion implantation process; the normal direction of the photoelectric sensing layer is taken as the depth direction of ion implantation and the thickness direction of the photoelectric sensing material layer, and the ion implantation depth of the cross-layer doped structure is at least greater than the thickness of the photoelectric sensing material layer farthest from the substrate along the normal direction of the photoelectric sensing layer. According to the embodiment of the invention, the imaging quality of the image sensor is improved.

The invention discloses a parameter adjustment method of an ion implantation machine. The method comprises the following steps: acquiring a plurality of first parameters of an ion beam; acquiring historical data and screening at least one group of historical data close to the plurality of first parameters, wherein each group of historical data at least comprises a plurality of first parameters; inputting the plurality of first parameters and the historical data into a hybrid deep neural network model, and obtaining a predicted output variable; and adjusting a third parameter of the ion implantation machine according to the predicted output variable. According to the parameter adjustment method of the ion implantation machine provided by the invention, the third parameter of the machine is adjusted by adopting the hybrid deep neural network model, so that automatic ion beam parameter adjustment can be realized, the manual participation rate is reduced, and meanwhile, the working efficiency and the working accuracy of the machine which works for a long time can be improved.

The invention discloses a wafer composite film and a preparation method thereof, and belongs to the technical field of semiconductor preparation. The method comprises the following steps: (1) performing hydrogen ion or hydrogen-helium mixed ion implantation on a piezoelectric wafer to obtain an implanted wafer, wherein the implanted wafer sequentially comprises a thin film layer, an implanted layer and a residual layer; (2) sequentially forming a defect layer and an isolation layer on the supporting substrate; (3) bonding the isolation layer and the thin film layer of the injected wafer to obtain a bonding body; and (4) laser is adopted to heat the injection layer, then annealing heat treatment is carried out on the bonding body to achieve complete stripping, polishing and cleaning of the film, then the wafer composite film is obtained, the wavelength of the laser is 100-700 nm, the power of the laser is 50 mw to 100 w, and the scanning speed of the laser is 10-50 mm / s. According to the method, complete stripping of the composite film and combination of laser and thermal annealing processes can be effectively achieved, the method has high process stability, the yield of the composite film can be greatly improved, and the processing time cost of the composite film is shortened.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention provides a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, forming a plurality of N-type body regions and a plurality of diffusion regions, and forming a P-type well region, an N-type source region and a current sharing layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps of: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

The embodiment of the invention relates to a method for ion implantation simulation, electronic equipment and a storage medium. The method comprises: determining an initial position of each ion in an exposed surface of a simulated semiconductor device; determining first collision data generated by collision between specified reference ions in the ions and material atoms of the semiconductor device in the implantation process; determining second collision data of each other ion based on comparison of surrounding material information of the other ions in each ion and surrounding material information of the reference ion; and determining the distribution condition of each ion in the simulated semiconductor material based on the first collision data and the second collision data. According to the technical scheme, the calculation amount in the simulation ion implantation process can be effectively reduced, the calculation time is remarkably shortened, and the simulation efficiency is improved.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention discloses a process for improving surface defects of a quartz substrate of a photomask IC (integrated circuit) chip, relates to the technical field of quartz substrates, and aims to solve the problem that the surface defects of the quartz substrate cannot be effectively improved in the process from material selection to manufacturing to later quality control in the prior art. Through three methods of visual inspection, automatic optical detection and laser scanning detection, multi-dimensional detection from macroscopic to microscopic and from the surface to the structure is realized, the accuracy and comprehensiveness of defect identification are ensured, and by setting a clear defect classification standard and a maximum defect range, the defect identification accuracy is improved. Defects possibly affecting product performance can be found and treated in time, the surface laser repairing method is suitable for shallow layer defects, the internal ion implantation repairing method can effectively treat deep layer defects, the flexibility and adaptability of the technology are improved through diversified repairing strategies, and unnecessary material waste and machining cost are avoided through accurate repairing.

The invention provides an optical proximity effect correction method of an ion implantation layer and a semiconductor device manufacturing method, and the method comprises the steps: firstly cutting off a convex corner in a corner-to-corner structure with a small interval in an original layout of the ion implantation layer, and then carrying out the OPC of the layout after the corner cutting, according to the method, the limitation of mask rule inspection on the corner-to-corner structures can be avoided, and the space for correcting the optical proximity effect is enlarged, so that the key size of a final layout obtained by OPC can meet a target value, the problem of process hot spots caused by easy distortion of a corner-to-corner structure pattern in an ion implantation layer in the prior art can be solved, and the quality of the ion implantation layer is improved. And the accuracy of OPC correction is improved, so that a more accurate final layout of the ion implantation layer is provided. According to the manufacturing method of the semiconductor device, the final layout of the required ion implantation layer is obtained by using the optical proximity effect correction method of the ion implantation layer, so that the yield and the performance of a product can be finally improved.

The invention provides a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and carrying out the epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed on the drift layer, etching and ion implantation are carried out, a first P-type well region, a protruding part, a first low-resistance region, a second low-resistance region and a third low-resistance region are formed, and the low-resistance region comprises the first low-resistance region, the second low-resistance region and the third low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region, an N-type source region, a conductive region and a protection region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

The invention discloses a composite terminal structure of a silicon carbide PIN diode and a design method of the composite terminal structure. The composite terminal structure comprises a device cell and a device terminal. The device cell comprises an N + type heavily doped substrate, an N-type lightly doped drift layer and a P + type heavily doped layer which are arranged in sequence; the device terminal is located in the N-type lightly doped drift layer, the device terminal comprises two parts of P + type junction terminal expansion regions and three groups of P + type field limiting ring structures, P + injection rings formed by P + type ion injection are arranged in the P + type junction terminal expansion regions, a plurality of P + injection rings form the P + type field limiting ring structures, the adjacent P + injection rings are separated by the P + type junction terminal expansion regions, and the P + type field limiting ring structures are arranged in the N-type lightly doped drift layer. And the upper surfaces of the P + type junction terminal expansion region and the P + injection ring are covered with oxide layers. The high-voltage power device has the advantages of being compact in structure, small in device area, low in production cost and the like, higher breakdown voltage, better process robustness and long-term reliability are achieved within the limited chip area, and the requirements of the next-generation high-voltage power device are met.

The invention provides a semi-super-junction high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a first drift region; a barrier layer is formed, etching and ion implantation are carried out, and a column region is formed; the barrier layer is removed, epitaxial growth is carried out on the first drift region, a second drift region is formed, and the drift layer comprises the first drift region and the second drift region; forming a barrier layer, etching, performing ion implantation, and forming a first P-type well region, a lug boss, a second P-type well region, an N-type source region and a Schottky region; re-forming a barrier layer, etching and depositing to form a gate dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: re-forming a barrier layer, etching, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that dual protection can be provided during reverse voltage withstanding, and the reliability of the device is improved.

The invention relates to a super junction power device and a preparation method thereof. The preparation method comprises the following steps: providing a silicon carbide substrate; a silicon carbide epitaxial layer is formed on the top surface of the silicon carbide substrate, the silicon carbide epitaxial layer has first type impurity ions, a plurality of doped columns are formed in the silicon carbide epitaxial layer, the doped columns have second type impurity ions, and the doped columns are formed through an etching process and an epitaxial process or through a multi-step epitaxial process and a multi-step ion implantation process; forming a body region in the surface, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer, wherein the body region has second type impurity ions; forming a source region between the doped columns, wherein the source region is provided with a first type of foreign ions; forming a first groove penetrating through the source region and the body region between the adjacent doped columns, and forming a second groove penetrating through the body region above the doped columns; forming a gate structure in the first groove; and forming a source trench structure in the second trench. The on resistance of the super junction power device is reduced, and the voltage withstanding characteristic of the super junction power device is improved.

The invention provides a heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type well region, an N-type source region and a masking region; forming a barrier layer again, and etching and depositing the insulating medium to form a first insulating medium region; forming a barrier layer again, and etching to form a groove; forming a barrier layer again, etching and depositing metal, and forming a suspension gate; forming a barrier layer again, and etching and depositing the insulating medium to form a second insulating medium region; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: preparing a source electrode metal layer, re-forming a barrier layer, etching, depositing metal, forming a source electrode metal layer, removing the barrier layer, and completing the preparation, thereby realizing the characteristics of low switching loss, high switching speed and low on-resistance.

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

Disclosed in the present application are a silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET is provided with a first withstand voltage masking structure and a second withstand voltage masking structure. The withstand voltage performance of the device is improved, the breakdown problem of a gate insulating dielectric layer can be avoided, the electrostatic effect of the device on a severe environment and the high-voltage peak tolerance capability in the circuit are improved, and the surge voltage resistance of the device and the over-voltage protection capability are improved. Ion implantation can be carried out on a first trench to form the first withstand voltage masking structure, and ion implantation can be carried out on a second trench to form the second withstand voltage masking structure.

The invention discloses a method for optimizing ion implantation process parameters of an integrated circuit, which comprises the following steps of: simulating a front-end process of a CMOS (Complementary Metal Oxide Semiconductor) device by utilizing Sensor Process of Sensor TCAD (Technology Computer Aided Design) software, and changing process parameters in a Halo ion implantation step to obtain a simulated CMOS device; then, carrying out numerical solution on the electrical property of the simulation CMOS device by utilizing a Sensor Device in the software, so as to obtain electrical data; and training, verifying and testing the residual neural network model by using the process parameters and the electrical data, optimizing parameters of the residual neural network model, and finally obtaining optimized process parameters. The method not only improves the optimization efficiency and precision of the ion implantation process parameters, but also realizes the automation and intelligence of process optimization through the combination of the deep learning algorithm and the TCAD simulation technology.

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a shallow-channel super-junction MOS device and a preparation process thereof, the shallow-channel super-junction MOS device comprises a drain electrode, a source electrode, a semiconductor epitaxial layer, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and the semiconductor epitaxial layer comprises an N substrate layer and a drift layer; a P well layer, a P-layer II and an N well layer are formed in the drift layer through ion implantation; the cross section of the grid electrode is T-shaped; a first P-layer is formed in the N well layer through ion implantation, and a narrow heavily doped N layer is formed in the drift layer and located between two adjacent second P-layers through ion implantation. After the gate voltage is accessed, a charge channel is formed in the P-layer 2, so that the N-well layer and the drift layer can form a path, and the existence of the P-layer 1 can inhibit the collection of charges flowing in the N-well layer to the gate region, so that the number of parasitic charges can be greatly reduced, and the response speed of the MOS semiconductor device is improved.

The invention provides a left-right shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type source region, a low-resistance region, a P-type well region and an N-type source region; forming a barrier layer again, etching to form a first groove, and depositing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and a barrier layer is formed again, the barrier layer is etched to form a through hole, the low-resistance region, the P-type source region and the N-type source region are etched, metal is deposited, a second source electrode metal layer is formed, the barrier layer is removed, and preparation is completed.

The invention further discloses a preparation method of the wide-temperature-range, high-performance and high-binding-force soft and hard composite coating. The preparation method comprises the steps of cleaning, ion implantation, preparation of a soft layer metal Ti, preparation of a hard layer TiZrAlCrSiMN, preparation of a soft layer metal Zr and preparation of the hard layer TiZrAlCrSiMN. The invention further discloses application of the wide-temperature-range, high-performance and high-binding-force soft and hard composite coating in a dry cutting tool. The invention discloses the wide-temperature-range high-performance high-binding-force soft and hard composite coating which is prepared through the preparation method, and the wide-temperature-range high-performance high-binding-force soft and hard composite coating solves the problems that an existing tool coating is low in high-temperature hardness, poor in abrasion resistance and poor in erosion resistance and cracking resistance.

The invention discloses a Schottky diode and a manufacturing method thereof, the Schottky diode comprises a substrate, an epitaxial layer, a cathode layer, a plurality of first ion implantation regions, a plurality of first grooves, a second barrier metal layer and an anode layer, the plurality of first ion implantation regions and the plurality of first grooves are arranged in a main junction region, a first ion implantation region is arranged at the bottom of the first groove, a PN junction is formed between the first ion implantation region and the epitaxial layer, a second ion implantation region is arranged at the bottom of the first groove, a PN junction is formed between the second ion implantation region and the epitaxial layer, and a first barrier metal layer is arranged on the side wall of the first groove; the second barrier metal layer is arranged on one side, far away from the substrate, of the epitaxial layer, is positioned in the main junction region and is connected with the first ion implantation region and the first barrier metal layer; the anode layer is disposed on the second barrier metal layer. Through the above design, the reverse leakage current of the Schottky diode can be greatly reduced, and the forward conduction voltage drop of the Schottky diode can be reduced.

The invention provides a pressure sensor based on silicon-silicon bonding and a preparation method thereof. The preparation method comprises the following steps: providing a low-resistance silicon wafer, forming a silicon deep hole in a first surface of the low-resistance silicon wafer, and depositing an isolation material in the silicon deep hole to form an isolation ring; etching the first surface to form a shallow groove and a conductive silicon column to obtain a low-resistance cap wafer; providing an SOI wafer, performing ion implantation on the first surface of the SOI wafer to form a resistance region, and obtaining a substrate wafer; bonding the low-resistance cap wafer with the substrate wafer; grinding the second surface of the low-resistance cap wafer until the isolating ring is exposed; depositing an insulating layer on the second surface of the low-resistance cap wafer, and forming a metal electrode on the insulating layer; and forming a back cavity structure on the second surface of the substrate wafer, exposing the top silicon of the SOI wafer, and forming a sensitive film layer. The conductive silicon column is made of low-resistance silicon, copper ion pollution is avoided, the preparation process is simple, and the period is controllable; the device obtained based on the silicon-silicon bonding process has high bonding strength and high air tightness.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

The embodiment of the invention provides a manufacturing method of a semiconductor structure, the semiconductor structure and a CMOS (Complementary Metal Oxide Semiconductor) circuit. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor substrate; wherein the semiconductor substrate comprises a semiconductor substrate, and a buffer layer and a stress layer which cover the semiconductor substrate; the semiconductor substrate comprises an NMOS region and a PMOS region; a PMOS gate structure is formed on the surface of the PMOS region; the buffer layer covering the side surface of the PMOS gate structure and the buffer layer covering the surface of the semiconductor substrate form an adjacent region; removing a part of the stress layer covering the PMOS region in the semiconductor substrate, and forming a stress layer residual part on the surface, far away from the semiconductor substrate, of the adjacent region of the buffer layer; executing an ion implantation process in the PMOS region; wherein the region for executing the ion implantation process comprises a stress layer residual part, so that the etching rate of etching the stress layer residual part is increased; and etching to remove the residual part of the stress layer. According to the embodiment of the invention, the overall electrical performance of the CMOS circuit is improved.