1321 results about "Ion implantation" patented technology

The invention relates to a simulation method for a semiconductor device, electronic equipment and a computer readable storage medium. The method comprises the steps that a multi-way tree structure is constructed based on grid data of a gridded semiconductor device, the multi-way tree structure at least comprises a root node, a plurality of layers and a plurality of leaf nodes, and each leaf node represents a corresponding polyhedron in a plurality of polyhedrons in the gridded semiconductor device; in response to the determination of the first spatial position of the particle in the semiconductor device, determining a first search path from the root node to a first leaf node in the plurality of leaf nodes based on the corresponding relationship between each leaf node and the corresponding polyhedron; and in response to the particle moving from the first spatial position to a second spatial position within the semiconductor device, determining a second search path in the multi-way tree structure based on the first search path to determine a second leaf node representing the polyhedron where the second spatial position is located. According to the method, the ion implantation simulation performance is effectively improved.

A method to operate an ion implanter. The method may include conducting an ion beam into an acceleration stage of a linear accelerator in the ion implanter, where the ion beam is a bunched ion beam. The method may also include applying an RF signal to the acceleration stage while the ion beam passes through the acceleration stage, the RF signal comprising a determined frequency and a determined amplitude, and performing a phase scan using the RF signal. The phase scan may include varying a phase of the RF signal at the acceleration stage over a plurality of phase values; and recording a plurality of arrival times at a monitor, situated downstream of the acceleration stage, the plurality of arrival times corresponding to the plurality of phase values, respectively.

An ion source that includes a cathode near a first end plate and a non-planar second end plate is disclosed. The non-planar second end plate serves to counteract the effect of the plasma on the second end plate. In some embodiments, the plasma has the ability to erode the second end plate. Rather than making the entire second end plate thicker, the second end plate is only made thicker in the regions that are affected by the plasma. In this way, less material is used in the production of the second end plate, and increased lifetime is achieved. This concept may also be used in environments where the plasma serves to deposit material on the second end plate.

The invention discloses an ion implantation process of an image sensor. The ion implantation process comprises the following steps: providing an ion implantation machine; the ion implantation machine continuously runs the nth ion implantation process for the first time, and n is a positive integer; based on the nth ion implantation process of the first time, the ion implantation machine automatically cuts a source, and continuously operates the (n + 1) th ion implantation process of the second time; the nth ion implantation process and the (n + 1) th ion implantation process are independently selected from any one of a P-type ion implantation process, an N-type ion implantation process and a D-type ion implantation process; the nth ion implantation process is different from the (n + 1) th ion implantation process; an ion beam in the P-type ion implantation process comprises boron difluoride and / or boron, an ion beam in the N-type ion implantation process comprises arsenic and / or phosphorus, and an ion beam in the D-type ion implantation process comprises indium. Through the process, the production efficiency of the image sensor and the low-brightness white dot performance are improved.

The invention relates to the technical field of semiconductors, and provides an avalanche photodetector and a preparation method thereof, and the detector comprises a substrate, an epitaxial layer, a peripheral p-type injection well, an active region p-type injection well, an active region n-type injection well and a surface n-type injection region. The epitaxial layer is formed on the substrate, and the peripheral p-type injection well is formed in a first region and a second region on the epitaxial layer; an active region p-type injection well is formed in a third region on the epitaxial layer; the active region n-type injection well is formed on the active region p-type injection well, and the surface n-type injection region is formed on the active region n-type injection well. A plurality of periodically spaced central avalanche regions are longitudinally formed by the active region p-type injection well and the active region n-type injection well in an alternative ion injection mode with different energy and doses, so that the preparation process is compatible, the detection efficiency of the SPAD is effectively improved, and excessive noise is not additionally increased.

The invention discloses a perovskite thin film, a photoelectric device and a method for improving the surface quality of the perovskite thin film. The method for improving the surface quality of the perovskite thin film comprises the following steps: S1, preparing the perovskite thin film; s2, performing picosecond pulse laser surface polishing treatment; and S3, guanidine ion implantation and repair: applying a guanidine salt solution to the surface of the perovskite thin film, removing the redundant guanidine salt solution on the surface of the perovskite thin film after the guanidine ions are implanted into the surface of the perovskite thin film, and then carrying out annealing treatment. According to the method, the surface of the perovskite thin film is polished through the picosecond pulse laser, the roughness of the surface of the perovskite is effectively reduced, a surface layer rich in defects is removed, guanidine ions are selectively implanted again through a multi-A-site vacancy structure formed on the surface of the perovskite thin film subjected to laser polishing, multiple hydrogen bonds are formed through the guanidine ions and a perovskite framework, and the surface roughness of the perovskite thin film is effectively reduced. And deep and stable defect passivation and lattice strengthening are realized, and the high-quality perovskite thin film with smooth surface, low defect density and high stability is obtained.

The invention belongs to the technical field of coated glass, and particularly provides a deposition method of a metal seed layer in TGV metallization and magnetron sputtering equipment. The invention aims to solve the problem of serious surface discharge phenomenon caused by low adhesive force between a metal film and a glass substrate, low metal coverage rate and step rate in a through hole and high accumulated charge on the surface of glass in the existing TGV metallization process. The independent and controllable ion source is introduced to assist deposition, the ion source is started at different stages of metal film deposition, and directional and high-energy positive ion flow generated by the ion source is utilized to bombard the surface of the glass substrate so as to assist the magnetron sputtering process, so that the surface of the glass substrate is subjected to magnetron sputtering. Through shallow ion implantation, enhancement of surface migration energy of deposited metal atoms and neutralization of negative charges accumulated on the glass surface, the adhesive force between metal and a glass substrate is improved, the metal coverage rate and the step rate in a through hole are improved, surface discharge is inhibited, and therefore the process stability is improved.

The invention provides a silicon carbide substrate for epitaxial growth, a preparation method of the silicon carbide substrate, a silicon carbide epitaxial wafer and a preparation method of the silicon carbide epitaxial wafer. In one aspect, there is provided a method for preparing a silicon carbide substrate for epitaxial growth, the method comprising: performing ion implantation on a surface of the silicon carbide substrate to form a damaged region below the surface; and annealing the silicon carbide substrate subjected to ion implantation so as to recrystallize the damaged region and form a defect gettering layer comprising a dislocation ring. Therefore, the density of defects in the epitaxial layer can be remarkably reduced, and the silicon carbide epitaxial wafer with more excellent crystal quality can be obtained.

The invention relates to the technical field of semiconductors, and discloses an ion implantation process optimization method and device, a semiconductor structure and a preparation method thereof.The ion implantation process optimization method comprises the steps that the current position of a current wafer in furnace tube equipment is obtained, the multiple wafers are arranged in the furnace tube equipment, polycrystalline silicon layers are formed on the wafers, and the polycrystalline silicon layers are arranged in the furnace tube equipment; the current wafer is a wafer to be subjected to ion implantation processing at the current moment in the plurality of wafers; according to the current position and a resistance deviation model, the resistance deviation of the polycrystalline silicon layer of the current wafer is determined, and the resistance deviation model is the corresponding relation between the position of the wafer and the resistance under the target temperature and the target gas flow field; according to the resistance deviation, optimization process parameters of the current wafer during ion implantation processing are determined, and the optimization process parameters are used for compensating the resistance deviation. According to the method, the resistance trend caused by the position of the furnace tube can be specifically compensated, the resistance uniformity between sheets is improved, the furnace tube equipment of the LPCVD does not need to be modified, and the production cost is reduced.

The invention belongs to the related technical field of semiconductor doping, and discloses a method for acquiring a second harmonic signal of non-uniform ion implantation doping concentration and an application of the second harmonic signal of the non-uniform ion implantation doping concentration. Determining refractive indexes and absorption coefficients of different depth positions of the ion implantation doping sample under a specific laser wavelength based on an optical property distribution model in the ion implantation doping sample; s2, calculating fundamental frequency light electric field distribution in the doped sample based on the obtained refractive index and absorption coefficient; s3, calculating the polarization intensity and effective second-order polarizability of the non-uniform doped ion implantation sample based on the simplified bond hyperpolarizability model and the fundamental frequency photoelectric field distribution; and S4, calculating far-field second harmonics of the corresponding layers at a predetermined observation angle based on the obtained polarization intensity or effective second-order polarizability of each layer, and carrying out integration on the far-field second harmonics corresponding to all layers to obtain the total intensity of the second harmonics of junction depth far-field radiation. According to the invention, the problem that the measurement sensitivity and repeatability are reduced is solved.

The invention provides a semiconductor device threshold voltage control method, system and equipment and a medium, and the control method comprises the steps: manufacturing a gate dielectric layer, and measuring and obtaining the first thickness of the gate dielectric layer; forming a gate polycrystalline silicon layer on the basis of the gate dielectric layer, oxidizing the surface of the gate polycrystalline silicon layer to obtain an ion barrier layer, and measuring and obtaining a second thickness of the polycrystalline silicon layer and a third thickness of the ion barrier layer; and determining the ion implantation amount of grid pre-doping according to the first thickness, the second thickness and the third thickness so as to perform ion implantation on the grid polycrystalline silicon layer, so that the threshold voltage of the device after grid pre-doping is kept within a preset target voltage range. According to the method, the pre-doped threshold voltage can be dynamically adjusted under the condition of not increasing any device manufacturing process steps, and the threshold voltage control precision and the product stability are guaranteed.

The invention discloses a method for optimizing the contour of a contact hole and a semiconductor structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: introducing a silicon-containing precursor gas and a carbon-containing precursor gas on a substrate, and depositing to form a first amorphous silicon layer serving as an etching deceleration layer; and depositing on the first amorphous silicon layer to form a second amorphous silicon layer by stopping introducing the carbon-containing precursor gas and continuing introducing the silicon-containing precursor gas. Through in-situ deposition of the laminated structure of the carbon-containing layer and the pure amorphous silicon layer, the intrinsic etching selection ratio is constructed by using the property difference of materials, and an additional ion implantation step is not needed. According to the method, the technological process is simplified, the cost and the thermal budget are reduced, the etching bias load effect can be effectively improved, the contour of the contact hole is optimized, the contact hole is closer to be vertical and is uniform up and down, and therefore the yield and the reliability of the device are improved.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The embodiment of the invention provides a wafer bonding method, a manufacturing method of a gate-all-around transistor and a product. The wafer bonding method comprises the following steps: providing a semiconductor material donor wafer and a support wafer, forming a first dielectric layer on the support wafer, and forming a second dielectric layer on one side, to be bonded to the support wafer, of the semiconductor material donor wafer; performing chemical mechanical polishing on the first dielectric layer to form a first bonding surface, and performing chemical mechanical polishing on the second dielectric layer to form a second bonding surface; and bonding the support wafer and the semiconductor material donor wafer through the first bonding surface and the second bonding surface. The manufacturing method of the transistor comprises the following steps: thinning a target semiconductor material layer in a semiconductor material donor wafer; and defining a source region, a drain region and a channel region of the transistor, and enabling the channel region to be separated from the buried oxide layer and suspended. And depositing a gate dielectric layer, defining a gate region and depositing gate metal. And carrying out ion implantation and annealing. And opening holes in the source region and the drain region, and depositing a source region electrode and a drain region electrode.

The utility model belongs to the technical field of limiting tools, and particularly relates to a limiting tool for processing sub-parts of a guard plate assembly of an ion implanter, which comprises a mounting plate, the bottom of the mounting plate is fixed on a processing device, and the top of the mounting plate is connected with a supporting seat through an adjusting mechanism. The adjusting mechanism comprises fixing plates fixed to the two ends of the top of the mounting plate, two first lead screws are rotationally connected between the two fixing plates, the two sides of the bottom of the supporting base are in threaded connection with the first lead screws through strip-shaped connecting plates, and a box is mounted on the side face of one fixing plate. The first driving motor can drive the first lead screw to rotate synchronously through the first synchronous wheel and the second synchronous wheel, then the supporting base and the workbench can be moved out of the lower portion of the machining equipment for feeding and discharging, in this way, the hands of a user cannot be injured when the machining equipment breaks down, and the using effect is improved.

The invention discloses a silicon wafer suspension pressing mechanism for a target disc of a semiconductor ion implanter, and relates to the field of new energy automobiles. The target disc bases are distributed and mounted on the chassis; the target disc upper cover is rotatably connected with the target disc base through a rotating shaft assembly; the target disc upper cover rotates through the rotating shaft assembly, so that the sliding limiting device slides along the two sides of the target disc upper cover to adjust the opening and closing angle; the silicon wafer suspension pressure devices are uniformly distributed on the two sides of the bottom of the target disc upper cover; a silicon wafer is arranged on the target disc base and is pressed by a silicon wafer suspension pressing device; according to the mechanism, a set of silicon wafer suspension pressing device is additionally arranged below a pressing ring, so that a pressing block is ensured to be gently pressed on a silicon wafer, the pressure is kept controllable, the silicon wafer cannot be crushed, the silicon wafer cannot be warped in a high-speed rotating process, the tiny unevenness of the surface of the silicon wafer or the plane of a carrying table can be automatically compensated, and uniform and self-adaptive contact between the pressing piece and the surface of the silicon wafer is realized.

The invention provides a preparation method of an anti-sputtering high-density graphite material for an ion implanter, and relates to the technical field of graphite material preparation, and the preparation method comprises the following steps: mixing and modifying a reinforcing phase, matrix graphite powder and a silane coupling agent to obtain composite powder; the reinforcing phase is a compound system of silicon carbide nanowires and boron-doped diamond micro-powder; mixing the composite powder with a coal pitch binder, and molding by adopting a stepped low-speed curing process to obtain a carbon blank; the silicon carbide nanowires and the boron-doped diamond micro-powder are compounded to form a reinforcing phase and cooperate with the superfine crystalline flake graphite matrix to achieve performance complementation, the silicon carbide nanowires form a three-dimensional network supporting structure to hinder crack growth, and the boron-doped diamond micro-powder improves the surface abrasion resistance and reduces the sputtering yield; the silane coupling agent is matched to modify and reinforce interface bonding, so that the problems of performance limitation and interface stripping of a traditional single reinforced phase are solved, and the comprehensive anti-sputtering and anti-erosion performance of the material is remarkably improved.

An ion implantation system has a first linear accelerator for accelerating ions of an ion beam to a first energy along a beam path. A second linear accelerator positioned downstream of the first linear accelerator along the beam path accelerates the ions to a second energy. A charge stripper has a stripper tube with a passageway positioned between the first and second linear accelerators. A charge stripping medium is provided in the passageway to strip at least one electron from the ions as the ion beam passes through the charge stripping medium. A focusing apparatus is associated with the stripper tube to control a trajectory of the ions within the passageway of the stripper tube. The focusing apparatus can be two or more quadrupoles and include an electrostatic lens, a magnet, a solenoid, or a Einzel lens.

The invention relates to the technical field of integrated circuits, in particular to a field plate dielectric layer and a preparation method thereof. The preparation method of the field plate dielectric layer comprises the steps that a substrate is provided, a well region is arranged in the substrate, a first region and a second region are defined on the substrate, and the well region penetrates through the first region and the second region; performing ion implantation on the well region by using preset ions, and forming a drift region in the well region of the first region; a field plate dielectric material layer is formed on the surface of the substrate, and the thickness of the field plate dielectric material layer located in the first region is larger than that of the field plate dielectric material layer located in the second region under the influence of preset ions; and performing graphical processing on the field plate dielectric material layer, and removing the field plate dielectric material layer in the second region to form a field plate dielectric layer. According to the invention, the drift region is formed in the well region by using the preset ions, so that the thickness of the field plate dielectric material layer is different, the field plate dielectric layer is obtained in one etching process, and the preparation complexity of the field plate dielectric layer is reduced.

The invention provides a non-uniform ion implantation process monitoring method based on template matching image recognition, and the method comprises the steps: 1, carrying out the to-be-monitored non-uniform ion implantation of a wafer, carrying out the modeling according to the measurement data of the wafer, and obtaining a template used for monitoring the dose / resistance distribution of the non-uniform ion implantation; step 2, carrying out resistance measurement on the batch of wafers after the non-uniform ion implantation, and drawing a resistance distribution diagram according to the coordinates and the resistance values of the measurement point positions; and 3, carrying out image identification comparison operation on the template obtained in the step 1 and the resistance distribution diagram obtained in the step 2 to obtain a similarity score, and carrying out statistical process control and control on the similarity score. Abnormalities such as deviation and rotation of dose distribution patterns of the non-uniform ion implantation process are effectively captured, and monitoring of the non-uniform ion implantation process is achieved.

Hybrid integrated photonic integrated circuit laser comprising a photonic integrated circuit including an elongated optical waveguide comprising an elongated gain medium waveguide, at least a first and second optical reflector, the gain medium waveguide being located or extending between the first and second optical reflectors and being located inside an optical cavity to provide optical feedback. Further comprising a pump laser diode to provide electromagnetic radiation to the gain medium waveguide. The elongated optical waveguide, and the first and second optical reflectors are monolithically integrated inside the photonic integrated circuit. The gain medium waveguide comprises a rare-earth ion implanted silicon nitride waveguide core. The pump laser diode is positioned adjacent to the at least one photonic integrated circuit and is edge coupled or facet coupled to a lateral edge or a facet of the photonic integrated circuit to provide pump radiation to the rare-earth ion implanted silicon nitride waveguide core.

The invention discloses a silicon photomultiplier and a preparation method thereof, belongs to the technical field of semiconductor device processing, and aims to solve the problems of lattice damage, channel effect, interface defects and the like caused by single-time high-dose ion implantation in the traditional process. Through the innovative processes of dose grading ion implantation, stepped cooling annealing, Gepre-amorphization processing, atomic layer deposition passivation and the like, the dark counting rate of the device is remarkably reduced, and the photon detection efficiency and the avalanche gain stability are improved. The prepared silicon photomultiplier comprises an optimally designed doped region and an Al2O3 / SiNx composite passivation layer, has excellent detection performance in a blue-violet light band, and can be widely applied to high-sensitivity detection fields such as biomedical imaging, nuclear radiation detection and laser radar.

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a groove which extends into an epitaxial layer along a first surface, and the first surface is the surface of one side, away from a substrate, of the epitaxial layer; the source region is located in the epitaxial layer on the two sides of the groove, and the source region is a region formed by carrying out ion implantation on part of the first surface; the grid electrode is located in the groove, the grid electrode comprises a first part and a second part which are distributed in the first direction, in the second direction, the maximum width of the first part is smaller than that of the second part, the bottom of the grid electrode is an arc face protruding towards the substrate, the first direction is the direction, away from the substrate, of the groove, and the second direction is perpendicular to the extending direction of the groove. According to the invention, the problems of low reliability of the gate oxide layer and non-uniform electric field distribution caused by electric field concentration of the semiconductor device in the related technology are solved.

A method and devices for fabricating optical emitters. The method includes disposing a flake of a multi-layer material onto a wafer. The wafer has an aperture over which a portion of the flake is disposed. The flake has a first surface partially in contact with the wafer, and a second surface opposite the first surface. The method further includes disposing a deceleration mask layer adjacent the flake. The deceleration mask layer has a flake-side surface adjacent to the flake, and an exposed surface opposite the flake-side surface. An ion beam is directed at the exposed surface of the deceleration mask layer to decelerate ions of the ion beam until at least a portion of the ions are implanted in the flake.

This invention discloses a novel SM-JTE termination structure for a floating junction silicon carbide power device and its fabrication method. The method includes: providing an N+ substrate; fabricating at least one epitaxial structure on one side surface of the N+ substrate; the epitaxial structure includes: a first N- epitaxial layer, and a floating junction p-region and a JTE region formed by ion implantation on the side surface of the first N- epitaxial layer away from the N+ substrate; growing a second N- epitaxial layer on the side surface of the at least one epitaxial structure away from the N+ substrate, and fabricating a surface termination; growing an oxide layer on the side surface of the second N- epitaxial layer away from the substrate; fabricating a first electrode on the side surface of the second N- epitaxial layer away from the substrate, and fabricating a second electrode on the side surface of the N+ substrate away from the epitaxial structure, with the first electrode in contact with the oxide layer. This invention divides the JTE region into multiple SMJTE structures, which can disperse the single-point electric field peak of the JTE region to these SMJTE structures, thereby reducing the electric field peak and giving the power device stronger dose offset resistance.

The utility model provides an ion source cavity structure, an ion source and an ion implanter. The cavity structure comprises a first arc chamber, a second arc chamber, a first cathode unit, a second cathode unit and a switch. One end of the first arc chamber away from the second arc chamber is provided with an air inlet, and one end of the second arc chamber away from the first arc chamber is provided with an ion outlet; the first cathode unit is arranged on one side of the first arc chamber, and the first cathode unit and the first arc chamber are electrically insulated from each other; the switch is connected in series with the first cathode unit; the second cathode unit is arranged on one side of the second arc chamber, and the second cathode unit and the second arc chamber are electrically insulated from each other. According to the utility model, the gas dissociation efficiency can be effectively improved, so that the size of an ion beam can be effectively improved, the whole process circulation time during the running of goods on a machine table is reduced, and the production efficiency of the machine table is improved.

The utility model provides an ion implanter and a semiconductor processing system, and relates to the technical field of ion implanters. The ion implanter comprises a cavity, an exhaust pipeline, a one-way valve, an isolating valve and a tail gas treatment device, the cavity is communicated with the tail gas treatment device through the exhaust pipeline, and the one-way valve and the isolating valve are installed on the exhaust pipeline; wherein when the ion implanter is in an exhaust state, the isolation valve is conducted; when the suction force of the tail gas treatment device is greater than or equal to a threshold value, the one-way valve is switched on; when the suction force of the tail gas treatment device is smaller than a threshold value, the one-way valve is switched off; and when the ion implanter is in a non-exhaust state, the isolating valve is switched off. The ion implanter and the semiconductor processing system provided by the utility model have the advantage of being capable of effectively preventing waste gas from flowing back into the cavity.

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The invention discloses a rapid planarization method and a preparation method of a super junction power device, and belongs to the technical field of semiconductor preparation. The epitaxial wafer to be processed comprises a substrate, a drift region arranged on the substrate, a dielectric cylinder region located in the drift region and a redundant dielectric region located on the drift region; processing the redundant medium region through a rapid planarization process; the rapid planarization process comprises the following steps: injecting ions into a redundant medium region; and annealing and stripping the redundant medium region. According to the method, the polishing speed is greatly increased in the mode of ion implantation and then low-temperature annealing stripping.

The invention relates to a method for preparing a polycrystalline silicon resistor and the prepared polycrystalline silicon resistor. The method comprises the following steps: S1, forming a polycrystalline silicon layer on a substrate; s2, first ion implantation is carried out on the polycrystalline silicon layer, the implanted ions are boron, and the polycrystalline silicon layer with the first ion implantation is obtained; s3, performing second ion implantation on the polycrystalline silicon layer subjected to the first ion implantation, wherein the implanted ions are nitrogen; and S4, carrying out annealing treatment on the polycrystalline silicon layer subjected to the first ion implantation and the second ion implantation. The polycrystalline silicon resistor prepared by adopting the method disclosed by the invention is relatively low in mismatch degree.