2423 results about "Ion implantation" patented technology

The invention relates to a super junction power device and a preparation method thereof. The preparation method comprises the following steps: providing a silicon carbide substrate; a silicon carbide epitaxial layer is formed on the top surface of the silicon carbide substrate, the silicon carbide epitaxial layer has first type impurity ions, a plurality of doped columns are formed in the silicon carbide epitaxial layer, the doped columns have second type impurity ions, and the doped columns are formed through an etching process and an epitaxial process or through a multi-step epitaxial process and a multi-step ion implantation process; forming a body region in the surface, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer, wherein the body region has second type impurity ions; forming a source region between the doped columns, wherein the source region is provided with a first type of foreign ions; forming a first groove penetrating through the source region and the body region between the adjacent doped columns, and forming a second groove penetrating through the body region above the doped columns; forming a gate structure in the first groove; and forming a source trench structure in the second trench. The on resistance of the super junction power device is reduced, and the voltage withstanding characteristic of the super junction power device is improved.

Disclosed in the present application are a silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET is provided with a first withstand voltage masking structure and a second withstand voltage masking structure. The withstand voltage performance of the device is improved, the breakdown problem of a gate insulating dielectric layer can be avoided, the electrostatic effect of the device on a severe environment and the high-voltage peak tolerance capability in the circuit are improved, and the surge voltage resistance of the device and the over-voltage protection capability are improved. Ion implantation can be carried out on a first trench to form the first withstand voltage masking structure, and ion implantation can be carried out on a second trench to form the second withstand voltage masking structure.

The invention provides a pressure sensor based on silicon-silicon bonding and a preparation method thereof. The preparation method comprises the following steps: providing a low-resistance silicon wafer, forming a silicon deep hole in a first surface of the low-resistance silicon wafer, and depositing an isolation material in the silicon deep hole to form an isolation ring; etching the first surface to form a shallow groove and a conductive silicon column to obtain a low-resistance cap wafer; providing an SOI wafer, performing ion implantation on the first surface of the SOI wafer to form a resistance region, and obtaining a substrate wafer; bonding the low-resistance cap wafer with the substrate wafer; grinding the second surface of the low-resistance cap wafer until the isolating ring is exposed; depositing an insulating layer on the second surface of the low-resistance cap wafer, and forming a metal electrode on the insulating layer; and forming a back cavity structure on the second surface of the substrate wafer, exposing the top silicon of the SOI wafer, and forming a sensitive film layer. The conductive silicon column is made of low-resistance silicon, copper ion pollution is avoided, the preparation process is simple, and the period is controllable; the device obtained based on the silicon-silicon bonding process has high bonding strength and high air tightness.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

The invention relates to a simulation method for a semiconductor device, electronic equipment and a computer readable storage medium. The method comprises the steps that a multi-way tree structure is constructed based on grid data of a gridded semiconductor device, the multi-way tree structure at least comprises a root node, a plurality of layers and a plurality of leaf nodes, and each leaf node represents a corresponding polyhedron in a plurality of polyhedrons in the gridded semiconductor device; in response to the determination of the first spatial position of the particle in the semiconductor device, determining a first search path from the root node to a first leaf node in the plurality of leaf nodes based on the corresponding relationship between each leaf node and the corresponding polyhedron; and in response to the particle moving from the first spatial position to a second spatial position within the semiconductor device, determining a second search path in the multi-way tree structure based on the first search path to determine a second leaf node representing the polyhedron where the second spatial position is located. According to the method, the ion implantation simulation performance is effectively improved.

The invention provides a 2.5 D substrate packaging method and packaging structure. The 2.5 D substrate packaging method comprises the following steps: providing a substrate with a groove; wherein the groove is a step groove; the grooves comprise a first groove and a second groove which are communicated with each other, and the depth of the first groove is greater than that of the second groove. A conductive pillar is formed in a substrate. Etching the substrate to expose the conductive pillars; forming a first insulating layer on one side, where the conductive columns are exposed, of the substrate in an ion implantation mode; the first insulating layer covers the surface of the substrate and the end face and the side wall of the exposed part of the conductive column. Grinding the first insulating layer to expose the end surface of the conductive column; forming a dielectric layer with a wiring layer on one side, far away from the substrate, of the first insulating layer; the wiring layer is electrically connected with the conductive column. The bonding force between the conductive column and the substrate can be improved, the conductive column is prevented from being broken or layered with the substrate in the grinding process, and the transmission performance of the conductive column is improved.

The invention discloses a diamond MOSFET device compatible with a CMOS ohmic contact process and a preparation method of the diamond MOSFET device. The preparation method comprises the steps that S1, a diamond substrate is selected, and an intrinsic diamond layer is grown on the diamond substrate in a homoepitaxial mode; s2, preparing a mask, and forming a boron-doped diamond layer in a source region and a drain region on the intrinsic diamond layer through boron ion implantation; s3, depositing a layer of Si film and a layer of Ti film on the surface of the sample; s4, performing two-step annealing on the sample to obtain ohmic contact formed by the boron-doped diamond layer, the boron-doped silicon layer and the titanium silicide layer; s5, removing the mask and the thin film above the mask; s6, preparing a terminal diamond surface layer; s7, preparing a passivation layer and windowing to form a source window and a drain window; and S8, preparing a gate electrode. According to the method, high-quality ohmic contact can be formed on the diamond through the gold-free process, the gold ion pollution risk is thoroughly avoided, and CMOS process compatibility is achieved.

The invention provides a preparation method of a planar gate accumulation layer channel field effect transistor embedded with a 3C / 4H-SiC heterogeneous junction. The preparation method comprises the following steps: growing an (n-) 4H-SiC drift region and an (n) 4H-SiC current expansion layer (CSL) on an (n +) 4H-SiC substrate by adopting a hot wall chemical vapor deposition (HWCVD) technology; forming a (p) 4H-SiC body region and an (n) 4H-SiC layer on the two sides of the CSL by using a mask, inductively coupled plasma (ICP) etching and ion implantation methods; growing a (p) 3C-SiC region on the upper part of the inner side of each (p) 4H-SiC body region by using a mask, ICP (Inductively Coupled Plasma) etching and HWCVD (High Weight Chemical Vapor Deposition); forming (n) 4H-SiC channels on the two sides of the middle part of the CSL by using a mask and HWCVD, and forming a (p) 3C / (n) 4H-SiC heterogeneous junction with a (p) 3C-SiC region at the bottom; respectively forming an (n +) 4H-SiC source region and a (p +) 4H-SiC source region on the outer side of each (n) 4H-SiC channel by utilizing ion implantation; forming an (n +) 3C-SiC region on the outer side of each (p +) 4H-SiC source region by adopting mask, ICP etching and HWCVD, and forming an (n +) 3C / (n) 4H-SiC heterogeneous junction with the (n) 4H-SiC layer below the (p +) 4H-SiC source region; performing high-temperature annealing to eliminate defects and activate impurities; forming an oxide layer and an (n +) poly-Si gate on the top; and respectively evaporating an alloy grid electrode, a source electrode and a drain electrode to prepare the planar gate accumulation layer channel field effect transistor embedded with the 3C / 4H-SiC heterogeneous junction. The leakage current of the transistor is small and is smaller than the on-resistance (Ron, sp), and the reverse recovery time is short.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

A working electrode is inserted into the plant to monitor the health of the plant components or to detect physical, mechanical damage or environmental change in the soil or atmosphere. A standard electrode is inserted into soil surrounding the plant or in the plant itself. A data logger connects the working electrode and the standard electrode. The data logger measures the potential difference between the working electrode and the electrolyte to provide the ability to compare a measured potential difference with a predetermined critical potential difference for the plant. A second electrochemical cell can inject electrons and ions into the plant. The plant can be used as a sensor to monitor the environmental change in the soil or in the atmosphere.

The invention discloses a Ga2O3 heterojunction beta irradiation battery with a multi-groove radioactive source, relates to the technical field of microelectronics, and solves the problems of low energy utilization rate and low energy conversion efficiency of a Ga2O3 nuclear battery radioactive source in the prior art. The battery comprises a filling type multi-groove radioactive source; the Ga2O3 heterojunction diode unit sequentially comprises a P-type ohmic contact electrode, a P-type NiO ion implantation region, an N-type Ga2O3 low-doped epitaxial layer, an N-type Ga2O3 high-doped substrate and an N-type ohmic contact electrode from top to bottom; a multi-T-type radioactive isotope source layer in the filling type multi-groove radioactive source is arranged above the P-type NiO ion implantation region and forms radiation energy coupling with the Ga2O3 heterojunction diode unit; the groove type structure is filled with the radioactive source, the energy deposition of the radioactive source entering the semiconductor conversion device is greatly increased, and the energy conversion efficiency of the Ga2O3 beta irradiation battery is improved.

Techniques for ribbon beam tuning segment tuning using machine learning are described. A method comprises receiving a set of control parameters representing configurations of multiple tuning segments of a tuning assembly for an ion implanter, predicting a set of process parameters representing one or more metrics associated with a beam property for an ion beam generated by the ion implanter based on the configurations of the multiple tuning segments using a control model, the control model comprising a forward model using a tuning matrix generated from a set of observations and a covariance matrix, and configuring a set of configurations for the multiple tuning segments based on the set of process parameters, the set of configurations for the multiple tuning segments to cause the ion beam to match a target metric for the ion beam. Other embodiments are described and claimed.

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

The invention provides a process integration method of a high-voltage CMOS (Complementary Metal Oxide Semiconductor) device in a flash memory device, which comprises the following steps of: before a grid electrode of a high-voltage MOS (Metal Oxide Semiconductor) device region is prepared, by virtue of a mask plate of threshold voltage ion implantation of a flash memory device region, adopting a non-self-alignment mode and taking a patterned sacrificial layer as a mask, forming a high-voltage MOS device region; and performing threshold voltage ion implantation (CVT ion implantation) on the substrate in the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region in the first well region and form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer, and replacing traditional LDD implantation in the MOS device region with the threshold voltage ion implantation to form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer. Therefore, a low-doped expansion region can be formed between the lower part of the grid boundary of the high-voltage MOS device region and the source / drain, and an independent high-voltage LDD ion implantation process of the traditional high-voltage CMOS device region can be omitted, so that the process manufacturing cost is reduced.

The invention relates to the technical field of ion implantation, and discloses a beam control optimization method for a low-energy large-beam ion implanter. According to the method, beam current and energy monitoring values are continuously collected through a sensor system, and beam state characterization indexes are generated through real-time processing; comparing the index with a preset range, and triggering an abnormal signal when the index exceeds the range; in an abnormal state, a beam position data set is collected in a fixed period, a position influence evaluation value is calculated, and if the evaluation value reaches or exceeds a threshold value, the state is marked as a high influence state; in a high influence state, extracting a time change trend quantity and a mode similarity quantity of a beam parameter, and calculating a correlation strength coefficient; and obtaining an adjustment factor according to the high influence state, multiplying the current beam current reference value by the adjustment factor to obtain an optimized beam position value, and executing position adjustment. The method achieves the dynamic monitoring and precise adjustment of the beam state, and improves the adaptability and stability of beam control.

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

The present invention provides a planar silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor. Some shallow trenches are arranged based on that a channel current is still parallel to a (0001) crystal plane of a SiC crystal, to further effectively use a crystal plane having a high channel mobility, for example, a (1120) crystal plane, a (1100) crystal plane, or a (0338) crystal plane, of the SiC crystal, thereby effectively reducing channel resistance of the planar SiC MOSFET device. In addition, source regions, well regions, and a channel are formed without protection from an additional ion implanted layer (IMP layer), leading to simple processes.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a super junction metal oxide semiconductor field effect transistor, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, and is characterized in that the semiconductor epitaxial layer specifically comprises two P well layers, two P + layers, two N well layers, an N substrate layer and an N drift layer; a beam waist N-layer is formed in the N drift layer through ion implantation; the girdling N-layer is composed of an upper half area and a lower half area, and the profile of the section of the girdling N-layer is in the shape that the upper end and the lower end are thick and the middle is thin. The gradient doped N-layer with the waist-shaped cross section is formed in the N drift layer, electric field distribution is optimized, the longitudinal electric field supporting capacity is enhanced in the middle thin and narrow area, and the breakdown voltage is improved; a transverse conduction path is expanded in thick areas at the two ends, so that the specific on-resistance is remarkably reduced, and high-voltage tolerance and low conduction loss are synchronously realized.

The embodiment of the invention relates to an ion implantation simulation method, electronic equipment and a storage medium. The method comprises the following steps: determining real-time energy of incident ions before colliding with atoms in a semiconductor material matrix; in response to the fact that the real-time energy is larger than a first energy threshold value, a BCA model is used for simulating the movement track of ions in the semiconductor material matrix; and in response to the fact that the real-time energy is smaller than or equal to the first energy threshold value, selecting a corresponding model from the BCA model and the MD model to simulate the ion implantation process, including using the MD model to simulate the motion trail of the ions in the semiconductor material matrix. According to the embodiment of the invention, accurate simulation of ion implantation in a full energy range (from high energy to low energy) can be realized.

The invention provides a power device and a preparation method thereof. The preparation method comprises the following steps: forming a P-type layer and an N-type layer on an N-type substrate; forming a groove; performing ion implantation to form an N-type source region; forming a gate oxide layer in the groove; forming a first polycrystalline silicon layer, a thick oxide layer and a second polycrystalline silicon layer in the groove; depositing a dielectric layer; forming a source contact region, wherein the source contact region exposes a part of the N-type source region and a part of the P-type layer; forming an insulating layer; forming a gate contact region, wherein the gate contact region extends into the first polycrystalline silicon layer; forming a drain contact region, wherein the N-type layer is exposed out of the drain contact region; and forming a source electrode, a grid electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the N-type source region and the P-type epitaxial layer. According to the invention, the source electrode, the grid electrode and the drain electrode can be attached to the heat dissipation substrate at the same time, so that the heat dissipation path is greatly optimized, and the access inductance of the source electrode is reduced; the connection of the P-type layer and the N-type source region is formed in the device through the groove, so that the process can be effectively simplified, an additional lead-out process is avoided, and the manufacturing cost is effectively saved.

The utility model discloses a beam scraping device structure for a beam line of an ion implanter, which relates to the technical field of high-energy physical experiments and accelerators and comprises a beam scraping device, the beam scraping device is integrally machined and formed, and the beam scraping device is of a structure with a square rod in the middle and disc flanges at two ends. Beam channels are formed in the middles of the two ends of the beam scraping device. The cross section of the beam channel is square and is adjusted according to the shape of the beam. A plurality of round holes are formed in the disc flange-shaped surfaces at the two ends of the beam scraping device, and the two ends of the beam scraping device are connected with the beam line main pipeline through the plurality of round holes. Two U-shaped tubular water cooling flow channels are formed in the middle of a square rod in the middle of the beam scraping device, and an inlet and an outlet are formed in the positions, on the surface of the beam scraping device, of the two ends of each water cooling flow channel respectively. The utility model relates to a beam scraping device with a long beam pipeline. The utility model relates to a beam scraping device with a water cooling structure. According to the beam scraping device, an integral processing mode is adopted, and a beam channel is processed in a wire cutting mode.

A method to operate an ion implanter. The method may include conducting an ion beam into an acceleration stage of a linear accelerator in the ion implanter, where the ion beam is a bunched ion beam. The method may also include applying an RF signal to the acceleration stage while the ion beam passes through the acceleration stage, the RF signal comprising a determined frequency and a determined amplitude, and performing a phase scan using the RF signal. The phase scan may include varying a phase of the RF signal at the acceleration stage over a plurality of phase values; and recording a plurality of arrival times at a monitor, situated downstream of the acceleration stage, the plurality of arrival times corresponding to the plurality of phase values, respectively.

The invention relates to a naked eye 3D display device and a preparation method thereof, and relates to the technical field of semiconductor display. According to the preparation method of the naked eye 3D display device, a first magnetic metal ion implantation region is formed in a central region of a substrate of a first Micro LED unit, and a second magnetic metal ion implantation region is formed in an edge region of the substrate of the first Micro LED unit; the magnetic metal ion concentration of the second magnetic metal ion implantation region is set to be greater than the magnetic metal ion concentration of the first magnetic metal ion implantation region, and the implantation depth of the second magnetic metal ion implantation treatment is set to be greater than the implantation depth of the first magnetic metal ion implantation region. And the shape of the magnetic structure of the Micro LED unit is effectively improved.

An ion source that includes a cathode near a first end plate and a non-planar second end plate is disclosed. The non-planar second end plate serves to counteract the effect of the plasma on the second end plate. In some embodiments, the plasma has the ability to erode the second end plate. Rather than making the entire second end plate thicker, the second end plate is only made thicker in the regions that are affected by the plasma. In this way, less material is used in the production of the second end plate, and increased lifetime is achieved. This concept may also be used in environments where the plasma serves to deposit material on the second end plate.

The invention provides a display panel, a display device and a preparation method of a PIN diode, and relates to the technical field of semiconductors. Since the array layer of the display panel forms a plurality of film layers by adopting an ion implantation mode in the preparation process, the PIN diode is integrated in the array layer firstly, and then the P-type semiconductor layer is prepared by adopting the ion implantation mode used in the preparation process of the array layer in the preparation process of the array layer, so that the P-type semiconductor layer can be prepared in the preparation process of the array layer. The purposes of simplifying the preparation process flow and reducing the production cost are achieved. Furthermore, the ion implantation depth of the first doped ions is smaller than the thickness of the P-type semiconductor layer, and a diffusion space is provided for diffusion of the first doped ions in the region of the P-type semiconductor layer in which the first doped ions are not directly implanted, so that the depth of the first doped ions diffused to the intrinsic semiconductor layer is reduced to the greatest extent, and the diffusion efficiency of the intrinsic semiconductor layer is improved. And the photoelectric property of the PIN diode is ensured.

The invention relates to the technical field of MOS semiconductors, and discloses a SiC MOSFET structure with a second-order oxide layer and a preparation technology thereof.The SiC MOSFET structure comprises a plurality of MOS cells arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a source electrode and a grid oxide layer, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of the single MOS cell through ion implantation, and the N-doped layer is located under the grid electrode; and a plurality of N + doped isolation layers which are not in contact with each other are formed in the N-doped layer through ion implantation. By introducing the N-doped layer right below the grid electrode and the doped N + isolation layers arranged and distributed in the N-doped layer, the distribution of an electric field below the gate oxide is effectively modulated, and the peak of the electric field is inhibited, so that the breakdown voltage of the device is remarkably improved, the reliability of the gate oxide layer is enhanced, and meanwhile, relatively low specific on-resistance is kept.

The invention discloses a contact hole forming method in a BCD and SGT integration process, and the method comprises the steps: S1, providing a substrate which comprises an SGT device region and a BCD device region; s2, performing an ion implantation process on the surface layer of the substrate to form source regions and a body lead-out region on the surface layer of the substrate in the SGT device region, and forming a substrate lead-out doped region, a body lead-out doped region, a source doped region and a drain doped region on the surface layer of the substrate in the BCD region, the source regions being located at two sides of the body lead-out region, the body lead-out doped region being located at two sides of the body lead-out region, the source doped region being located at two sides of the body lead-out region, and the drain doped region being located at two sides of the body lead-out region; the source region and the body lead-out region form a common connection structure; s3, forming a polycrystalline silicon gate structure on the surface of the substrate in the BCD device area; s4, forming a dielectric layer on the surface of the substrate, wherein the dielectric layer covers the polycrystalline silicon gate structure; and S5, simultaneously forming a contact hole of the SGT device and a contact hole of the BCD device in the dielectric layer. According to the scheme, the forming efficiency of the contact hole in the BCD and SGT integrated device can be improved.

The invention discloses an ion implantation process of an image sensor. The ion implantation process comprises the following steps: providing an ion implantation machine; the ion implantation machine continuously runs the nth ion implantation process for the first time, and n is a positive integer; based on the nth ion implantation process of the first time, the ion implantation machine automatically cuts a source, and continuously operates the (n + 1) th ion implantation process of the second time; the nth ion implantation process and the (n + 1) th ion implantation process are independently selected from any one of a P-type ion implantation process, an N-type ion implantation process and a D-type ion implantation process; the nth ion implantation process is different from the (n + 1) th ion implantation process; an ion beam in the P-type ion implantation process comprises boron difluoride and / or boron, an ion beam in the N-type ion implantation process comprises arsenic and / or phosphorus, and an ion beam in the D-type ion implantation process comprises indium. Through the process, the production efficiency of the image sensor and the low-brightness white dot performance are improved.

The invention relates to the technical field of semiconductors, and provides an avalanche photodetector and a preparation method thereof, and the detector comprises a substrate, an epitaxial layer, a peripheral p-type injection well, an active region p-type injection well, an active region n-type injection well and a surface n-type injection region. The epitaxial layer is formed on the substrate, and the peripheral p-type injection well is formed in a first region and a second region on the epitaxial layer; an active region p-type injection well is formed in a third region on the epitaxial layer; the active region n-type injection well is formed on the active region p-type injection well, and the surface n-type injection region is formed on the active region n-type injection well. A plurality of periodically spaced central avalanche regions are longitudinally formed by the active region p-type injection well and the active region n-type injection well in an alternative ion injection mode with different energy and doses, so that the preparation process is compatible, the detection efficiency of the SPAD is effectively improved, and excessive noise is not additionally increased.

The invention relates to the technical field of ion implantation, and discloses a dynamic adjustment method for large beam uniformity of an ion implanter. According to the method, a beam spot distribution data sequence in a beam transmission path is collected in real time, uniformity drift prediction is carried out in combination with an injection process parameter set, and beam uniformity prediction parameters are generated. And capturing a current beam spot form image by using a beam spot imaging device, inputting the current beam spot form image and the prediction parameters into a plurality of beam spot classifiers containing independent classification paths in parallel, and identifying to obtain actual beam spot distortion parameters. And executing electromagnetic field parameter prediction based on the parameter, generating a predicted electromagnetic field adjustment parameter, collecting an adjusted beam spot image through a feedback mechanism, and inputting the beam spot image into a plurality of electromagnetic field parameter classifiers in parallel again to output an actual adjustment parameter. And finally, integrating the distortion parameter and the adjustment parameter to generate a dynamic adjustment instruction set, and realizing closed-loop control of beam uniformity. According to the method, the problem of uniformity drift in the large-beam ion implantation process is effectively solved, and the process stability and the implantation efficiency are improved.