30 results about "Thin film soi" patented technology

Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

The invention belongs to the semi-conductor power device technical field. A SOI layer of the device is thinner (1to 2um); a grid oxide layer is thick (100 to 800nm); a grid field plate gets across a grid and extends above a drift region. An active expansion region positioned below the thick grid oxide layer and connected with a source region can be also arranged in the body of the device to assure the more effective formation of the whole device. The grid oxide layer of the invention is thicker, can bear high grid-source voltage and meet the need of a level displacement circuit; the SIO layer is thinner, can decrease the parasitic effect of the device and reduce consumption; through adding the grid field plate striding over the grid on the surface of the power device, the depletion of the drift region can be increased, the electric field peak value on the silicon surface at the tail end of the grid is decreased, the breakdown characteristic of the device is improved, further more the concentration of the drift region is helped to improve, and the on-state resistance of the device is decreased. The invention has the advantages of low parasitic effect, fast speed, low power consumption, strong radiation-resistant ability and so on, and is compatible with the standard process. By adopting the invention, various high-voltage, high-speed and low conducting loss devices of excellent performance can be produced.

Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.

The embodiment of the invention discloses a preparation method for a power device structure, and the method comprises the steps: injecting phosphorus onto a thin film SOI wafer, carrying out high-temperature annealing, activating injected ions, and carrying out heavy doping of an n-type drift region from the surface of the device to the upper surface of a buried oxide layer; carrying out silicon etching till the buried oxide layer, forming a SiO2 dielectric layer window, carrying out SiO2 deposition, carrying out SiO2 etching till the surface of the buried oxide layer, forming a polycrystalline silicon window, and carrying out polycrystalline silicon deposition; carrying out phosphorus injection through a specially-customized photoetching plate, and then carrying out long-time high-temperature annealing; forming a drain electrode, a source electrode, a grid electrode, a gate-oxide, and a polysilicon gate, wherein the polysilicon gate is connected with a gate in the drift region; depositing field oxide SiO2 and metal, carrying out the etching of the metal, and forming source, drain and grid metal, thereby effectively improving the breakdown voltage of a device, and reducing the conduction resistance of the device.