29 results about "Field oxide" patented technology

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

A diode formed by a polysilicon layer is disposed between a field oxide film and an interlayer insulating film, in a semiconductor substrate, at a front surface of the semiconductor substrate. One resist mask is used to form contact holes of the interlayer insulating film and contact trenches and a p+-type region of the polysilicon layer. The contact trenches are continuously formed from bottoms of the contact holes, respectively, in a depth direction. A low-resistance contact between the p+-type region and an anode electrode is formed at least at a bottom of the contact trench. During the formation of the p+-type region, while a p-type impurity is ion-implanted in an inner wall of the contact trench 3b, an n-type cathode region maintains an n-type conductivity thereof and a contact with a cathode electrode is formed at sidewalls of the contact trench.

The application relates to an integrated circuit with a power device and a DSOI device and a manufacturing method thereof, which comprises a substrate including a first active region; a first oxide layer located on the substrate and including a field oxide region and a first insulating buried layer region; a first gate located on the substrate and extending to the field oxide region; a first semiconductor layer including a field plate region located on the field oxide region and a first SOI region located on the first insulating buried layer region; a second insulating buried layer located on the first SOI region; a second semiconductor layer located on the second insulating buried layer and including a second active region; and a second gate located on the second semiconductor layer. The field oxide region and the field plate region of the application utilize a part of the DSOI structure, so that the power device can be integrated on the DSOI structure by a simpler process and at a lower cost. Compared with the circuit design in which the power device and the DSOI device are not in one die, the application has the advantages of small size, low cost and high reliability.

The present disclosure relates to an IGBT and a manufacturing method thereof. The IGBT comprises, from bottom to top, a collector region (109), a buffer layer (108), a substrate (101), a field oxide layer (102), an insulating medium layer (106) and a metal layer (107), and further comprises a main junction region (103) of a first conductive type and a cutoff ring region (104) of a second conductive type formed by diffusion in the substrate. A polysilicon layer is arranged between the field oxide layer and the insulating medium layer, and the polysilicon layer comprises m first conductive type doped regions (p1-pm) and m second conductive type doped regions (n1-nm) arranged alternately in a horizontal direction, m≥2. The metal layer above the main junction region and the first conductive type doped region (p1) closest to the main junction region are in contact through a hole in the insulating medium layer, and the metal layer above the cutoff ring region and the second conductive type doped region (nm) closest to the cutoff ring region are in contact through a hole in the insulating medium layer. The present scheme improves the consistency and stability of the breakdown voltage of the device.

A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes steps of: depositing an N-drift layer on a substrate, conducting an ion implant process on the N-drift layer to form a plurality of P-type pillars, depositing a N-type epitaxial layer on the P-type pillars, conducting an ion implant process on the N-type epitaxial layer to form a first P-type epitaxial layer and at least one localized P region, conducting a field oxidation to the first P-type epitaxial layer to form a second P-type epitaxial layer, and forming a field oxide layer on the first P-type epitaxial layer and the N-type epitaxial layer. The localized P region passes though the N-type epitaxial layer to the field oxide layer.

The application discloses a field effect tube and a preparation method thereof, and relates to the technical field of semiconductor devices. The preparation method of the field effect tube comprises the following steps: providing a substrate; forming a deep N well and a P-type body region on the substrate, the body region is arranged at the outer periphery of the deep N well and is spaced from the deep N well, and a plurality of P-type electric field adjusting structures are embedded in the deep N well; forming a field oxide layer on the upper surface of the substrate, the field oxide layer has at least two first windows on the deep N well and a second window on the body region; forming a drain and a source in the deep N well through the first window and forming a body contact in the body region through the second window, wherein the source surrounds the outer periphery of the drain; and forming polycrystalline silicon on the field oxide layer as a field plate. The field effect tube and the preparation method thereof can homogenize an electric field while simplifying a process flow.

This invention relates to an LDMOS device and its manufacturing method. The LDMOS device includes: a source region; a drain region; a drift region; a field oxide layer; a gate extending from near the edge of the source region onto the field oxide layer; a first low-doped region located directly below the field oxide layer on the side near the source region; and a second low-doped region located directly below the gate on the side near the drain region. The region between the first and second low-doped regions has a first conductivity type. The first and second low-doped regions have the first conductivity type, and their doping concentration is lower than that of the region between them; or the first and second low-doped regions have a second conductivity type. This invention introduces low-doped or inverted regions into areas of concentrated electric field, making the potential line distribution sparser in these two areas, reducing the collisional ionization rate, and mitigating the hot carrier injection effect in these areas.

The application discloses a kind of trench power MOSFET and its preparation method, specific steps include: S1) P well region and patterned field oxide layer pattern are formed;S2) side wall silicon nitride is formed in field oxide layer pattern side wall;S3) with both as mask etching groove and forming gate oxide layer;S4) in the trench filling conductive material, form gate;S5) after removing side wall silicon nitride, with field oxide layer pattern as mask carries out N+ source region injection;S6) deposition and planarization dielectric layer;S7) remove field oxide layer and carry out over-etching to its lower silicon, form contact window;S8) by the window carries out P+ contact region injection;S9) fill metal layer, complete device production.The application fundamentally eliminates the overlaying error between trench mask and contact hole mask in conventional process to limit cell size.

This application discloses a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes an active region and a termination region; the termination region surrounds the active region; the termination region includes a semiconductor body configured with a first conductivity type; it also includes a first region configured with a second conductivity type and located on a first surface; the first surface has a plurality of trenches arranged at intervals; the vertical projection of the plurality of trenches on the first surface lies within the vertical projection of the first region on the first surface; it also includes an isolation layer disposed within the trenches; the semiconductor body further includes a plurality of field limiting rings configured with a second conductivity type and located on the first surface; a field oxide layer located on the first surface; a field plate layer located on the side of the field oxide layer away from the first surface; a gate electrode located on the side of the field plate layer away from the field oxide layer; a source electrode; and a drain electrode. The technical solution of this application embodiment can improve the avalanche tolerance of the semiconductor device and enhance its performance.

This application provides a semiconductor structure, its fabrication method, device, mask pattern generation method, and mask. The semiconductor structure includes: a substrate comprising a substrate and a field oxide structure; the substrate having opposing first and second surfaces; a channel active region formed within the substrate; the field oxide structure extending from the second surface to the first surface, defining a first boundary of the channel active region on the first surface and a second boundary of the channel active region on the second surface; the channel active region having at least one passivation connection connecting the first and second boundaries; the passivation connection protruding along a direction extending from the interior of the channel active region toward the field oxide structure; the passivation connection being composed of one or more inclined planes or curved surfaces; a gate oxide layer covering the first surface and connected to the field oxide structure; and a gate formed on the side of the gate oxide layer away from the substrate. This application improves the breakdown voltage of a high-voltage MOSFET.

This invention relates to the technical field of semiconductor devices, and in particular to a high breakdown voltage SGT-MOS device and its fabrication method. The method includes depositing an N-epitaxial layer on an N+ substrate 1, forming trenches on the N-epitaxial layer, the trenches including termination trenches and unit cell trenches, the width and depth of the termination trenches and unit cell trenches being consistent; the spacing between the termination trenches is b, the spacing between the unit cell trenches is a, and the spacing between the first termination trench adjacent to the unit cell trench is also a, the spacing b of the termination trenches should be smaller than the spacing a of the unit cell trenches; the trenches are filled with a field oxide layer and shielding polysilicon; a P+ shielding region is formed at the bottom of the termination trenches; the spacing b of the termination trenches is smaller than the spacing a of the unit cell trenches; this method improves the termination breakdown voltage, optimizes the electric field distribution, avoids premature breakdown at corner A, improves the overall breakdown voltage and avalanche resistance of the device, has a wide range of applications, and good process compatibility.

The application discloses a trench power MOSFET suitable for medium and high voltage and a preparation method thereof, which comprises an epitaxial layer, a trench gate structure, a plurality of field oxide columns, a first doped region, a second doped region, a dielectric layer, a contact hole, a doped contact region and a metal interconnection layer. The field oxide columns are arranged on the surface of the gate oxide layer in the terminal area at intervals. The first doped region is located in the epitaxial layer below each field oxide column and between adjacent trenches in the active area. The second doped region is located in the first doped region between the adjacent trenches in the active area. The dielectric layer covers the trench gate structure and the field oxide columns. The contact hole is arranged below the doped contact region in the epitaxial layer. The metal interconnection layer is filled in the contact hole and covers part of the surface of the dielectric layer, and forms an ohmic contact with the doped contact region. The preparation process of the application only needs four masks, and the production cost is significantly reduced under the premise of ensuring the key electrical characteristics and reliability of the device, and the technical problems that the existing simplified process damages the electrical performance and reliability of the device while reducing the number of masks are effectively overcome.

An electrostatic discharge semiconductor device and a method for manufacturing the same, an integrated circuit are disclosed. The electrostatic discharge semiconductor device includes: a substrate; a first N-type well region and a drift region; a P-type well region and a second N-type well region in contact with each other; a first N+ doped region and a first P+ doped region; a second P+ doped region and a second N+ doped region; a plurality of field oxide layers, separating the first N+ doped region, the first P+ doped region, the second P+ doped region, and the second N+ doped region in sequence; a gate oxide layer and a polysilicon layer, stacked in sequence on the surface of the substrate. Under electrostatic pulses, the parasitic transistor turns on first, then a controllable silicon discharge path is formed, the device has strong electrostatic protection capability and high robustness.

The present application discloses a high-voltage NMOSFET, which comprises a P-type well region formed in a first active region, a first source-drain region and a second source-drain region formed in a second active region and a third active region respectively and located outside the first and second side faces of the first active region. A fourth active region surrounds the first, second and third active regions. A P-type deep diffusion region and a substrate lead-out region are formed in the fourth active region. The P-type ion implantation region of the P-type deep diffusion region is larger than the fourth active region and extends into the adjacent field oxide layer. The P-type ion implantation region of the P-type deep diffusion region has first and second protruding parts in the region between the third and fourth side faces of the first active region and the fourth active region. The present application also discloses a manufacturing method of the high-voltage NMOSFET. The present application can improve the double-peak phenomenon of the IDVG curve of the device and reduce the sub-threshold leakage current of the device.

This invention relates to the field of semiconductor technology and discloses a planar MOSFET structure with integrated temperature sampling function and its fabrication method. The structure includes a drain contact layer, an N+ substrate on the upper surface of the drain contact layer, an N- epitaxial layer on the upper surface of the N+ substrate, and a P-type ring region and a P-type body region arranged laterally spaced within the N-type body region, with an N+ source region within the P-type body region. A gate oxide layer covers the top of the N-epitaxial layer, a field oxide layer is located at the center of the top of the gate oxide layer, and a polysilicon gate is located on top of the gate oxide layer and the field oxide layer. An interlayer dielectric layer covers the top of the field oxide layer and the polysilicon gate, and a source metal and a P-region metal connected to the P-type body region and the N+ source region are located on top of the interlayer dielectric layer. This invention achieves temperature monitoring by inputting current into the P-region of the polysilicon diode and sampling its current flow rate (VF).

Provided in the present invention is a high-voltage NLDMOS structure. The high-voltage NLDMOS structure comprises: a P-type substrate, wherein an N-type implantation region is formed in the region of the substrate that is close to a drain side, an N-type epitaxial layer is formed on the substrate, a field oxide layer is formed on a field oxide region of the epitaxial layer, a P well is formed on the epitaxial layer, and P-type doped layers close to the upper surface of the epitaxial layer are formed on the epitaxial layer on a source side and below the field oxide layer; a gate structure and a drain-side polysilicon field plate, wherein the gate structure comprises a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends onto the P well, the other end of the gate polysilicon layer extends onto the adjacent field oxide layer, and the drain-side polysilicon field plate is located on the field oxide layer close to the drain side; an N-type source-side heavily doped region, an N-type drain-side heavily doped region and a P-type heavily doped P well pickup region; and an interlayer dielectric layer located between the source side and the drain side, wherein a contact member for leading out the drain-side polysilicon field plate is formed on the interlayer dielectric layer. The breakdown voltage of a device of the present invention is improved.

This disclosure provides a semiconductor device and a method for manufacturing the same. The device includes: a semiconductor layer; a body region located within the semiconductor layer; a source region and a drain region located within the body region and spaced apart from each other; a gate conductor located above the semiconductor layer and between the source and drain regions; a gate dielectric layer located between the gate conductor and the semiconductor layer; and a field oxide layer surrounding the source and drain regions, at least on the surface of the semiconductor layer. The semiconductor device also includes a doped ring located within the semiconductor layer, with the source and drain regions located within the doped ring, and the field oxide layer surrounding the doped ring. The body region and the doped ring are of a first doping type, and the source and drain regions are of a second doping type, with the first doping type being the opposite of the second doping type. By providing a doped ring with the opposite doping type to the source / drain regions around the source / drain regions, the source / drain regions are isolated from the field oxide layer, thereby solving the technical problems of source / drain punch-through induced by positive charge in the field oxide layer (DIT) and crosstalk between adjacent devices, as well as the large current problem caused by single-event flip-flops (SEE).

The application relates to the field of semiconductor technology and provides a shielded gate power MOSFET structure and a manufacturing method thereof. When an avalanche occurs after the device is turned off, a reverse peak voltage generated by a load inductance is applied to the drain of the device, the withstand voltage is borne by a terminal trench ring, an electric field generated by the trench ring has a repelling effect on avalanche holes, and there are no avalanche holes around the field oxide layer of the terminal trench ring. The direction of an electric field generated by additional N-type polysilicon in the terminal additional trench is from the periphery to the additional N-type polysilicon. Under the condition of the same chip area, the current density of the on-current is increased, the on-resistance is reduced, and the performance of the product is improved due to the fact that there is no region without N+ source area; the avalanche hole current flowing into the source area is reduced, the anti-avalanche breakdown characteristic of the device is improved, the avalanche tolerance EAS is increased, and the reliability of the device is improved by adopting the structure.

The application provides a metal-oxide semiconductor field effect transistor and a preparation method thereof. The metal-oxide semiconductor field effect transistor comprises an active region and a terminal region. A first field limiting ring and a second field limiting ring are prepared in an epitaxial layer located in the terminal region. The doping concentration of the doping ions in the second field limiting ring is greater than the doping concentration of the doping ions in the first field limiting ring. The junction depth of the second field limiting ring is less than the junction depth of the first field limiting ring. The second field limiting ring is set as a shallow-junction high-doping-concentration field limiting ring relative to the first field limiting ring, and the corresponding field oxide layer is set, so that the fixed charges and movable charges in the terminal region field oxide layer can be effectively shielded, the terminal region depletion layer is prevented from shrinking, the reliability of the device in a high-voltage scene is improved, the device withstand voltage is improved in combination with the first field ring, and the operation performance and operation stability of the device are simultaneously improved.

A semiconductor device of the present application includes a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The second main surface has a cell region and a peripheral region between the cell region and a peripheral edge of the second main surface when viewed in plan. The silicon carbide substrate has a termination structure and a channel stopper ring formed in the second main surface in the peripheral region. The channel stopper ring is located outward of the termination structure when viewed in plan. The silicon carbide substrate and the channel stopper ring have a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface in the peripheral region so as to overlap the termination structure when viewed in plan and at least partially overlap the channel stopper ring when viewed in plan.

Disclosed is a semiconductor device and a manufacturing method thereof, in which the sharp corners of the upper surface of the semiconductor substrate and the side wall of the groove are eliminated by changing the growth step of forming the oxide layer in the groove, the thickness of the field oxide layer obtained is guaranteed, the breakdown protection performance of the field oxide layer structure is guaranteed, and thus the performance of the semiconductor device is improved.

This invention provides a method for improving gate-source leakage current. The method includes: providing a base structure comprising a trench, a first dielectric layer, and a first conductive material, wherein the top surface of the first conductive material is lower than the trench opening; thermally oxidizing the base structure; growing a second dielectric layer on the exposed surface of the first conductive material; wet etching the first dielectric layer, wherein the second dielectric layer protects the first dielectric layer on the side of the first conductive material from excessive lateral etching by utilizing the rate difference between the second and first dielectric layers in the etching solution; and depositing a third dielectric layer to fill the trench after wet etching. This invention improves the morphology of the field oxide layer after etching back through the protective effect of the thermal oxide layer, eliminates the potential for voids during subsequent dielectric filling, prevents leakage failure due to thin insulation, and significantly improves the consistency of the gate-source leakage current and its yield performance.

This application provides an LDMOS structure and a method for manufacturing the LDMOS structure. The structure includes: a substrate with mutually spaced doped well regions and drift regions formed internally; at least two spaced isolation trenches formed within the drift regions; at least two field plate structures formed within the isolation trenches; each field plate structure includes a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the substrate; and at least two isolation structures formed within the isolation trenches; the isolation structures are located on the side of the conductive layer away from the substrate. This application overcomes the limitations imposed by existing LDMOS devices on breakdown voltage and on-resistance, improving the overall performance of the LDMOS device.

A semiconductor device includes a silicon carbide substrate, a field oxide film, an insulation film, and a wiring layer. The silicon carbide substrate includes a first main surface, and a second main surface being an opposite surface of the first main surface. The second main surface includes a cell region, and an outer peripheral region located between the cell region and an outer peripheral edge of the second main surface in plan view. The silicon carbide substrate includes a termination structure and a channel stopper that are formed in the second main surface located in the outer peripheral region in the silicon carbide substrate. The channel stopper is located outside the termination structure in plan view. A conductivity type of the silicon carbide substrate and a conductivity type of the channel stopper are each a first conductivity type.

This application discloses a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes an active region and a termination region; the termination region surrounds the active region; the termination region includes a semiconductor body configured with a first conductivity type; it also includes a first region configured with a second conductivity type and located on a first surface; the semiconductor body further includes multiple second regions configured with the first conductivity type and located on the first surface; the vertical projection of the multiple second regions on the first surface lies within the vertical projection of the first region on the first surface; it also includes multiple field limiting rings configured with the second conductivity type and located on the first surface; a field oxide layer located on the first surface; a field plate layer located on the side of the field oxide layer away from the first surface; a gate electrode located on the side of the field plate layer away from the field oxide layer; a source electrode; and a drain electrode. The technical solution of this application embodiment can improve the avalanche tolerance of the semiconductor device and enhance its performance.

The application discloses a kind of trench type double-layer gate power devices, including N+ substrate, N-epitaxial layer, P well and dielectric layer;N-epitaxial layer is provided with source region trench and terminal area trench between dielectric layer;Source region trench outside is trench field oxide layer, inside has N type shield gate, isolation oxide layer, gate oxide layer and control gate, N+ source region is between P well and dielectric layer, source region contact hole is between source region trench and is connected with source region front metal layer by dielectric layer;Terminal area trench outside is terminal area trench field oxide layer, terminal area trench polysilicon is set in terminal area trench, is wrapped by terminal area trench field oxide layer and dielectric layer, before terminal area trench cutoff ring, there is avalanche resistance enhancement structure by the last terminal area trench ring of terminal area terminal area trench and its accessory structure composition.The application can increase forward on-current density, reduce on-resistance and increase avalanche resistance EAS in the case of ensuring that chip area and chip cost are not increased, and improve product performance.

This application provides a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor (MOSFET), relating to the field of semiconductor technology. The method includes: providing a substrate, the substrate including a first surface and a second surface; forming a field oxide layer on the first surface, the field oxide layer including a first ion implantation window and a second ion implantation window; performing ion implantation through the second ion implantation window to form multiple field-limiting rings; performing ion implantation through the first ion implantation window with a first implantation energy and a first implantation dose; performing ion implantation through the first ion implantation window with a second implantation energy and a second implantation dose to form a junction field-effect transistor region; wherein the first implantation energy is less than the second implantation energy, and the first implantation dose is greater than the second implantation dose; forming a gate oxide layer and forming a polycrystalline gate; and forming a P-type body region, an N+ type source region, and a P+ type deep body region in the active region. This achieves a synergistic effect of low on-resistance and high avalanche capability, thereby improving single-pulse avalanche energy.

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a plurality of transition regions, a field oxide layer, and a gate structure. The substrate comprises a laminated substrate and an epitaxial layer. The transition regions are located in the epitaxial layer, and a surface of the transition regions away from the substrate is a first surface. The first surface is a side surface of the epitaxial layer away from the substrate. The field oxide layer is located on the first surface. The field oxide layer comprises a plurality of spaced field oxide portions. The plurality of transition regions in contact with the same field oxide portion are distributed at intervals. The gate structure is located on the first surface between two field oxide portions and on a surface of the partial field oxide layer away from the epitaxial layer. Part of the gate structure is in contact with the transition region. The transition region has a first doping type, the epitaxial layer has a second doping type, and the first doping type and the second doping type are opposite. The application solves the problems of short service life and low reliability of the semiconductor device caused by the overshoot phenomenon in the prior art.