345 results about "Field oxide" patented technology

The invention relates to the technical field of semiconductors, in particular to a shield gate trench MOS (Metal Oxide Semiconductor) device, which comprises a substrate, an epitaxial layer, a trench, a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shield gate field oxide layer and a second shield gate field oxide layer, the control grid, the first shielding grid and the second shielding grid are located in the groove; the control grid, the first shielding grid and the second shielding grid are of an up-down structure. The second shield grid is located between the first shield grid and the control grid; the first interlayer dielectric layer is located between the first shielding grid and the second shielding grid; the second interlayer dielectric layer is located between the second shield gate and the control gate; the gate oxide layer is located between the control gate and the inner wall of the groove; the first shield gate field oxide layer is located between the first shield gate and the inner wall of the trench; the second shield gate field oxide layer is located between the second shield gate and the inner wall of the trench. The device reduces the gate-drain capacitance, increases the gate-source capacitance, and improves the EMI performance.

The invention provides a terminal structure of a semiconductor device, a preparation method thereof and the semiconductor device. The terminal structure comprises a substrate; the epitaxial layer is positioned on one side of the substrate; the field oxide layer is at least located on the partial surface, away from the substrate, of the epitaxial layer; the interlayer dielectric layer is located on the surface, far away from the substrate, of the field oxide layer, the partial side wall of the field oxide layer and the partial surface, far away from the substrate, of the epitaxial layer; the at least one first groove is arranged in the interlayer dielectric layer which is not covered with the field oxide layer along a first direction, the first groove penetrates into the epitaxial layer, and the first direction is the thickness direction of the substrate; and the passivation layer is at least located in the first groove and on the surface, away from the substrate, of the interlayer dielectric layer. The problem that in the prior art, the service life of a planar silicon carbide MOSFET power chip is affected due to water vapor permeation caused by the difference of thermal expansion coefficients of different dielectric layers in a high-temperature and high-humidity environment is solved.

The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

The invention relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor material layer; the first groove is located in the semiconductor material layer, the side wall and the bottom wall of the first groove are connected through an arc angle, and the included angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle; the drain region is located in the semiconductor material layer on the periphery of the first groove, and the depth of the drain region is smaller than that of the first groove; the well region is located in the semiconductor material layer below the bottom wall; the field oxide layer extends on the part, between the well region and the drain region, of the bottom wall and the side wall; the gate dielectric layer is connected with the field oxide layer and covers part of the well region; the field plate is located on the field oxide layer; the grid electrode is located on the grid electrode dielectric layer; the source region is positioned on the surface layer of the well region; a current conduction path of the semiconductor device comprises a first current conduction path which is located in the semiconductor material layer and extends close to the bottom wall and a second current conduction path which extends close to the side wall. Therefore, the on-resistance of the device is reduced, and the voltage-resistant performance of the device is ensured at the same time.

The invention provides a high-voltage NLDMOS (N-type laterally diffused metal oxide semiconductor) structure which comprises a P-type substrate, and an N-type injection region is formed in a region, close to a drain end, of the substrate; an N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on a field oxide region of the epitaxial layer; a P well is formed on the epitaxial layer, and a P-type doped layer close to the upper surface of the epitaxial layer is formed on the epitaxial layer below the source end and the field oxide layer; the gate structure comprises a gate dielectric layer and a gate polycrystalline silicon layer, one end of the gate polycrystalline silicon layer extends to the P well, the other end of the gate polycrystalline silicon layer extends to the adjacent field oxide layer, and the drain polycrystalline silicon field plate is located on the field oxide layer close to the drain end; an N-type source end heavily doped region, an N-type drain end heavily doped region and a P-type heavily doped P well lead-out region; the interlayer dielectric layer is located between the source end and the drain end, and a contact piece used for leading out the drain end polycrystalline silicon field plate is formed on the interlayer dielectric layer. The breakdown voltage of the device is improved.

The invention provides a shield gate trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, according to the manufacturing method, a field oxide layer is formed twice (a first oxide layer and a second oxide layer), a polycrystalline silicon interlayer is introduced between the first oxide layer and the second oxide layer, and the polycrystalline silicon interlayer is only reserved on a side wall opposite to a non-floating shield gate layer after being etched twice, so that the field oxide layer is formed in the first oxide layer and the second oxide layer; and a floating shield grid layer is formed. As the floating shield grid layer is introduced to the side wall opposite to the non-floating shield grid layer, the field intensity of the middle area in the depth direction of the groove can be increased, and the overall voltage endurance capability is improved. The floating shield gate layer is introduced into the shield gate trench MOSFET structure, so that the voltage withstanding level of a device can be improved, and the voltage withstanding level of the device can be improved by utilizing a capacitive coupling effect between a part of the floating shield gate layer and a part of the floating shield gate layer and a capacitive coupling effect between a source electrode and the drain electrode. Therefore, gate-drain capacitance and source-drain capacitance of the device can be reduced, and switching speed of the device is improved.

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the base comprises a substrate and an epitaxial layer which are stacked; the main junction is positioned in the epitaxial layer; at least one field limiting ring located in the epitaxial layer; the junction termination extension region is located in the epitaxial layer; the junction termination expansion region and the field limiting ring have an overlapping region; the cut-off ring is located in the epitaxial layer; wherein the surfaces of one sides, far away from the substrate, of the main junction, the field limiting ring, the cut-off ring and the junction termination extension region are flush with the surface, far away from the substrate, of the epitaxial layer; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction pointing to the main junction along the substrate; the field oxide layer is at least located on the sides, away from the substrate, of the epitaxial layer, the junction termination extension region and the cut-off ring; the field plates are respectively positioned on one sides, far away from the substrate, of the main junction and the field oxide layer; wherein the doping types of the substrate and the cut-off ring are the same, and the doping types of the main junction, the field limiting ring and the junction termination expansion region are the same. The semiconductor structure has a high withstand voltage level.

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The invention discloses a power device and a preparation method thereof. The power device comprises a substrate; the epitaxial layer of the first conduction type is arranged on the substrate, and an active region and a terminal region arranged on the periphery of the active region are arranged on the epitaxial layer; the first injection region of the second conduction type comprises a main junction, and the main junction is arranged at the position, close to the active region, of the terminal region; the first anti-breakdown structure comprises a voltage-dividing deep groove and a field oxide layer; the voltage-dividing deep groove is arranged in a terminal area outside the main junction, and the depth of the voltage-dividing deep groove is greater than the junction depth of the main junction; and the field oxide layer is filled in the partial pressure deep groove and extends out of the partial pressure protection region to cover the surface of the partial pressure deep groove. The power device has the advantages that the anti-breakdown effect is guaranteed, the preparation process is simple, and the cost is relatively low.

The invention belongs to the field of design and manufacturing of semiconductors / integrated circuits, and particularly relates to a manufacturing method of a silicon capacitor. Comprising the following steps: forming an oxide layer on a silicon substrate, photoetching and etching to form a 1 # capacitor groove, generating a field oxide layer in the groove, filling doped polycrystalline silicon, processing the surface, etching a 2 # capacitor groove, depositing a multilayer film in the groove, processing the multilayer film at two ends of the groove, depositing silicon oxide, finally connecting an upper polar plate and a lower polar plate through photoetching and metal deposition, removing redundant substances and detecting. According to the method, the structure size and performance can be accurately controlled, the electrical performance, reliability and stability of the silicon capacitor in the field of integrated circuits and the like are improved, and the circuit integration degree is improved.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

The invention relates to the technical field of semiconductors, in particular to a shield gate trench device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, wherein the substrate comprises an epitaxial layer, a first groove located in the epitaxial layer, and a first oxide layer covering at least part of the surface of the epitaxial layer and the inner wall of the first groove; a polycrystalline silicon structure filling the first groove is formed, and the doping concentration of the polycrystalline silicon structure is gradually reduced in the direction from the groove bottom to the top end of the first groove; the polycrystalline silicon structure is etched back to form a second groove, the polycrystalline silicon inner wall of the second groove covers the first oxide layer on the inner wall of the first groove, and the second groove is used for forming a shield gate structure; a second oxide layer is formed on the inner wall of the polycrystalline silicon of the second groove based on oxidation treatment, and the thickness of the second oxide layer is gradually decreased in the direction from the groove bottom to the top end of the first groove. According to the invention, free regulation and control of the thickness size and thickness change of the field oxide layer can be realized, and the device is suitable for voltage-withstanding devices with various voltage requirements.

The utility model provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and electronic equipment. The LDMOS device comprises a substrate; the gate structure is located on the surface of the substrate; the source region and the drain region extend into the substrate from the surface of the substrate and are located on the two sides of the gate structure; the field oxide layer covers at least part of the surface of the drain region and extends to cover part of the surface, close to the drain region, of the gate structure; the at least one string of field plate structure is located on the field oxide layer and is arranged between the gate structure and the drain region, each string of field plate structure comprises a plurality of conductive contact field plate holes, and the plurality of conductive contact field plate holes are arranged in a string in a plane parallel to the surface of the substrate; and in the length extension direction of at least one string of field plate structures, a gap exists between the adjacent conductive contact field plate holes.

The present invention discloses a dual-Fin ESD protection device with a parasitic SCR, which includes a single-Fin PNP transistor, a single-Fin NPN transistor, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region, a sixth field oxide isolation region, a first anode metal electrode, a second anode metal electrode, a first cathode metal electrode, and a second cathode metal electrode. The first anode metal electrode is disposed above the first N-type heavily doped region, the second anode metal electrode is disposed above the first P-type heavily doped region, the first cathode metal electrode is disposed above the second N-type heavily doped region, and the second cathode metal electrode is disposed above the second P-type heavily doped region. The single-Fin PNP transistor and the single-Fin NPN transistor are arranged side by side along the Y-axis direction to form a parasitic SCR structure. The present invention can effectively improve the robustness of small-size devices and ensure that the devices can be quickly and efficiently turned on when ESD occurs.

The invention discloses a dual-working mode silicon carbide power device structure and a manufacturing method thereof. The power device structure comprises a Bipolar part and a MOSFET part, and specifically comprises an N-type substrate and a collector metal layer arranged at the bottom of the N-type substrate, a P-base region is arranged on the top of the N-type substrate, a plurality of gate oxide layers and a trench gate vertically arranged in the corresponding gate oxide layer are arranged on the P-base region through a groove; a plurality of N+ injection regions and P+ injection regions are arranged in the P-base region, a floating base and an emitter are arranged at positions corresponding to the N+ injection region and the P+ injection region on both sides of the top of the P-base region, and the floating base and the emitter are isolated from each other by an ILD external insulating layer, and the manufacturing of the power device structure comprises the steps of growing an epitaxial layer, growing a field oxide layer, etc., and the process flow is compatible with the process flow of an ordinary silicon carbide MOSFET, and no new steps need to be added.

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with asymmetric stepped field oxide. The field oxide structure of the LDMOS device is in an asymmetric step shape, asymmetric coordinated regulation and control of the STI thickness are achieved, the step side expands the field oxide boundary through the gradient, electric field concentration at the STI corner is weakened, breakdown voltage is improved, the inclination angle of the non-step side keeps a thick field oxide area, the electric field peak of the source side is restrained, avalanche breakdown is delayed, and the device performance is improved. And meanwhile, the hot carrier injection risk is reduced. The structure gives consideration to the collaborative optimization of the breakdown capability and the conduction efficiency, is especially suitable for a high-voltage BCD platform with low loss and high reliability requirements, and is a structural innovation scheme with high process compatibility and high design flexibility.

A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

A semiconductor device includes: a recess along a top surface of a semiconductor substrate, the recess having a first sidewall and a second sidewall laterally opposite each other; a nitride-based spacer layer extending along the first sidewall of the recess; and a field oxide layer in the recess extending along a bottom surface of the recess. The second sidewall is defined by a shallow trench isolation structure extending into the semiconductor substrate. A lateral tip of the field oxide layer is blocked by the nitride-based spacer layer from laterally extending beyond the first sidewall into the semiconductor substrate.

The present invention provides a semiconductor device and a manufacturing method thereof, the manufacturing method comprising: forming first and second trench regions in a semiconductor substrate having an active region and a lead-out region, and defining first and second mesa regions; forming a field oxide layer covering the inner wall of the groove and each mesa area, and filling a first polycrystalline silicon layer; forming a mask layer with a first opening (exposing the active region) and a second opening (exposing the second mesa region); synchronously removing the field oxide layers on the table tops of the two areas through one-time wet etching, so that the two table top areas obtain consistent surface height reference; a gate structure is then formed. The step difference between the two intervals is eliminated from the source through synchronous etching, accumulation and amplification of morphology deviation in the follow-up process are avoided, and the uniformity of the dielectric layer, the photoetching precision and the injection consistency are remarkably improved. According to the method, additional masks or planarization modules do not need to be added, the process is simplified, the cost is reduced, and the reliability and the yield of the device are greatly improved.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

The invention provides a high-voltage Resurf LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure capable of resisting a single-particle burning effect. The device comprises a P-type substrate, an N-type epitaxy, a P-type buried layer, a P-type well region, a source region P + injection, an N-type well region, a source region N + injection, a drain region N + injection, a gate oxide layer, a field oxide layer, polycrystalline silicon and metal. According to the invention, the unequal-length P-type buried layer is introduced into the N-type drift region, and the P-type buried layer is directly connected with the P-type substrate, so that an extra leakage path is provided for hole current generated by single-particle radiation. A long P-type buried layer is introduced below an N-type drift region to improve the extraction capability of hole current, a short P-type buried layer is introduced above the N-type drift region to relieve the electric field concentration phenomenon of a drain side N + region, and the unequal-length P-type buried layers act together to inhibit the parasitic triode self-maintenance phenomenon caused by single-particle incidence and improve the single-particle burnout resistance of the device.

The present invention discloses an optimized integration method for high stress edge effect of analog BiCMOS process and a high linearity dual polycrystalline capacitor, the steps of which include: 1) depositing a polycrystalline film layer of a polycrystalline capacitor lower plate of P1 angstrom above a field oxide layer on the surface of an N-type well, and completing N-type photolithography implantation doping; 2) depositing a first dielectric layer of a dual polycrystalline capacitor of d1 angstrom, and completing the production of a protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor by an exposure and etching process; 3) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the production of a capacitor dielectric layer structure by an exposure and etching process; the high linearity dual polycrystalline capacitor includes a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a self-aligned P-type well, etc. The present invention significantly improves the edge effect of the dual polycrystalline capacitor by integrating a high stress edge effect optimization technical solution of a high linearity dual polycrystalline capacitor in an analog integrated circuit.

The utility model discloses a silicon carbide MOSFET device comprising at least one cell, and each cell comprises a silicon carbide substrate of a first doping type; an epitaxial layer of a first doping type; the well regions of the second doping type are located in the epitaxial layer, and JFET regions are arranged between the adjacent well regions; the source region of the first doping type is located in the well region; the contact region of the second doping type is located in the well region and is adjacent to the source region; the field oxide layer is located on the surface of the epitaxial layer and located above the JFET region; the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer, and the first gate oxide layer and the second gate oxide layer are located on the two sides of the field oxide layer respectively and are adjacent to the field oxide layer respectively; the gate conductors comprise a first gate conductor and a second gate conductor, the first gate conductor covers the surface of the first gate oxide layer and part of the surface of the field oxide layer, the second gate oxide layer covers the surface of the second gate oxide layer and part of the surface of the field oxide layer, and the first gate conductor and the second gate conductor are separated from each other.

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, an isolation structure and a field oxide layer. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type, and is disposed on the substrate. The isolation structure has a first conductivity type and is disposed in the epitaxial layer. The isolation structure comprises a first well, a second well and a doped region arranged between the first well and the second well. The field oxide layer is disposed on the epitaxial layer. Wherein the field oxide layer exposes the top surface of the epitaxial layer between the first well and the doped region or exposes the top surface of the epitaxial layer between the second well and the doped region.

The invention discloses a drain extension field effect transistor and a preparation method, and relates to the technical field of semiconductor preparation. The drain expansion field effect transistor comprises a field oxidation structure, a field plate structure, a gate structure, a drain region and a source region, and the drain region and the source region are located on the two sides of the field oxidation structure. The field oxidation structure is divided into a first region, a second region and a third region, the second region is located between the first region and the third region, the field plate structure is located above the third region, the upper part of the second region is empty, one part of the gate structure covers the upper part of the first region, and the other part of the gate structure is close to the source region. According to the drain extended field effect transistor, the gate structure and the field plate structure of the drain extended field effect transistor are separated, so that specific voltage can be independently applied to the field plate structure to reduce conduction loss, switching loss and temperature rise of a device, and the problems of poor performance and low reliability of the device in the prior art are solved.

The present invention provides a semiconductor device, comprising a semiconductor substrate, a first well, a second well, a field oxide layer, and a polysilicon layer. The semiconductor substrate has a first conductivity type. The first well is formed in the semiconductor substrate and has a second conductivity type. The second well is formed in the first well and has the first conductivity type. The field oxide layer is formed over the second well. The polysilicon layer is formed over the field oxide layer and forms a resistance element.

The application provides a high-frequency semiconductor device with improved voltage resistance and a manufacturing method thereof. The device comprises a first conductive type substrate, a first conductive type epitaxial layer arranged on the first conductive type substrate, a single-cell groove arranged in the first conductive type epitaxial layer, a top space arranged in the single-cell groove, a field oxide layer arranged on the inner wall below the top space in the single-cell groove, a gate oxide layer arranged on the sidewall of the top space in the single-cell groove, a first polysilicon field plate arranged in the middle of the single-cell groove, a second polysilicon field plate and a third polysilicon field plate arranged on both sides of the top of the first polysilicon field plate in the single-cell groove, the first polysilicon field plate, the second polysilicon field plate and the third polysilicon field plate being all arranged below the top space of the single-cell groove, and a first gate polysilicon and a second gate polysilicon being arranged on both sides of the top space in the single-cell groove. The application can improve the voltage resistance of the device and the working frequency of the device simultaneously.

A semiconductor device includes: a recess along a top surface of a semiconductor substrate, the recess having a first sidewall and a second sidewall laterally opposite each other; a nitride-based spacer layer extending along the first sidewall of the recess; and a field oxide layer in the recess extending along a bottom surface of the recess. The second sidewall is defined by a shallow trench isolation structure extending into the semiconductor substrate. A lateral tip of the field oxide layer is blocked by the nitride-based spacer layer from laterally extending beyond the first sidewall into the semiconductor substrate.