143 results about "Field oxide" patented technology

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

The present invention provides a semiconductor device and a manufacturing method thereof, the manufacturing method comprising: forming first and second trench regions in a semiconductor substrate having an active region and a lead-out region, and defining first and second mesa regions; forming a field oxide layer covering the inner wall of the groove and each mesa area, and filling a first polycrystalline silicon layer; forming a mask layer with a first opening (exposing the active region) and a second opening (exposing the second mesa region); synchronously removing the field oxide layers on the table tops of the two areas through one-time wet etching, so that the two table top areas obtain consistent surface height reference; a gate structure is then formed. The step difference between the two intervals is eliminated from the source through synchronous etching, accumulation and amplification of morphology deviation in the follow-up process are avoided, and the uniformity of the dielectric layer, the photoetching precision and the injection consistency are remarkably improved. According to the method, additional masks or planarization modules do not need to be added, the process is simplified, the cost is reduced, and the reliability and the yield of the device are greatly improved.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, an isolation structure and a field oxide layer. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type, and is disposed on the substrate. The isolation structure has a first conductivity type and is disposed in the epitaxial layer. The isolation structure comprises a first well, a second well and a doped region arranged between the first well and the second well. The field oxide layer is disposed on the epitaxial layer. Wherein the field oxide layer exposes the top surface of the epitaxial layer between the first well and the doped region or exposes the top surface of the epitaxial layer between the second well and the doped region.

The invention discloses a drain extension field effect transistor and a preparation method, and relates to the technical field of semiconductor preparation. The drain expansion field effect transistor comprises a field oxidation structure, a field plate structure, a gate structure, a drain region and a source region, and the drain region and the source region are located on the two sides of the field oxidation structure. The field oxidation structure is divided into a first region, a second region and a third region, the second region is located between the first region and the third region, the field plate structure is located above the third region, the upper part of the second region is empty, one part of the gate structure covers the upper part of the first region, and the other part of the gate structure is close to the source region. According to the drain extended field effect transistor, the gate structure and the field plate structure of the drain extended field effect transistor are separated, so that specific voltage can be independently applied to the field plate structure to reduce conduction loss, switching loss and temperature rise of a device, and the problems of poor performance and low reliability of the device in the prior art are solved.

The application provides a high-frequency semiconductor device with improved voltage resistance and a manufacturing method thereof. The device comprises a first conductive type substrate, a first conductive type epitaxial layer arranged on the first conductive type substrate, a single-cell groove arranged in the first conductive type epitaxial layer, a top space arranged in the single-cell groove, a field oxide layer arranged on the inner wall below the top space in the single-cell groove, a gate oxide layer arranged on the sidewall of the top space in the single-cell groove, a first polysilicon field plate arranged in the middle of the single-cell groove, a second polysilicon field plate and a third polysilicon field plate arranged on both sides of the top of the first polysilicon field plate in the single-cell groove, the first polysilicon field plate, the second polysilicon field plate and the third polysilicon field plate being all arranged below the top space of the single-cell groove, and a first gate polysilicon and a second gate polysilicon being arranged on both sides of the top space in the single-cell groove. The application can improve the voltage resistance of the device and the working frequency of the device simultaneously.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The application provides a semiconductor device, comprising a U-shaped boost diode, the U-shaped boost diode comprising a first isolation structure arranged below a first field oxide region, a source terminal and a base terminal, and a second isolation structure arranged below a second field oxide region, the first isolation structure and the second isolation structure are arranged in the same layer and are spaced apart, and a part of the first isolation structure along a thickness direction and a part of the second isolation structure along the thickness direction are located in a substrate, and the remaining part of the first isolation structure along the thickness direction and the remaining part of the second isolation structure along the thickness direction are located in an epitaxial layer. The second isolation structure in the application can disperse the electric field across the high potential, so as to prevent the electric field from concentrating, so that the electric field does not concentrate at the source terminal at the bottom of the U-shaped boost diode, and the breakdown voltage BV of the boost diode in the semiconductor device is increased.

The present application relates to a lateral device, comprising: a source region (134) having a first conductivity type; a drain region (132) having the first conductivity type; a drift region (110) having the first conductivity type and at least partially located between the source region (134) and the drain region (132); a buried region (112) of a second conductivity type located in the drift region (110) between the source region (134) and the drain region (132); a field oxide layer (150) located on the drift region (110); a top-doped region (120) located in the drift region (110) that is above the buried region (112) of the second conductivity type and below the field oxide layer (150), the top-doped region comprising at least one doped layer of the first conductivity type, and the doped layer of the first conductivity type having a doping concentration greater than that of the drift region (110); and field plates (140) located on the field oxide layer (150).

Disclosed are a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor substrate; etching the substrate to form a trench in the substrate; filling the trench with insulating material; etching the insulating material to expose a sharp corner at the intersection of the trench sidewall and the upper surface of the substrate; and forming a field oxide layer on part of the upper surface of the substrate and the insulating material, wherein the sharp corner at the intersection of the trench sidewall and the upper surface of the substrate is oxidized in the step of forming the field oxide layer. The method exposes a sharp corner at the intersection of the shallow trench isolation structure and the substrate surface by etching back the shallow trench isolation structure, and eliminates the sharp corner in the step of forming the field oxide layer, thereby avoiding charge accumulation at the sharp corner and improving the breakdown voltage and reliability of the device.

Disclosed in the present invention is a method for manufacturing a mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design. The method comprises the steps of: 1) growing a field oxide layer above a P-type well of an analog integrated circuit; 2) depositing a polycrystalline capacitor lower electrode plate polycrystalline film layer on a field oxide layer above an N-type well, and performing matched implantation doping; 3) growing a capacitor dielectric layer; 4) depositing a polycrystalline capacitor upper electrode plate polycrystalline film layer, and manufacturing a protective film layer and a protective structure. The mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design comprises a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low-dielectric-coefficient filling film layer, a metal interconnection film layer, and a passivation layer. The present invention reduces the impact of parasitic capacitance, substrate noise and crosstalk noise, and realizes the low noise characteristic of integrated capacitors.

The invention provides an anti-radiation transverse integrated power semiconductor device. The anti-radiation transverse integrated power semiconductor device comprises a P-type substrate, an N-type epitaxial region, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a first P-type doped region and a second P-type doped region, the first dielectric layer is arranged on the surface of an active region of the device, the second dielectric layer is arranged on the surface of a field region of the device, and the active region is of a closed structure and covers and exceeds the first N-type doped region; and the polycrystal gate is arranged on the surface of the first dielectric layer. The drift region of the transverse device is of a longitudinal structure, the surface of the drift region is not provided with a thick field oxide layer, and a large amount of charges generated by total dose radiation are avoided, so that the influence of the total dose radiation effect on the performance of the device is greatly reduced, and the device has high total dose radiation resistance.

The invention discloses a power device. The power device comprises an interlayer film. The semiconductor substrate is divided into an active region and a termination region. A device unit structure is formed in the active region; and a field oxide layer surrounding the periphery of the active region is formed in the terminal region. In the active region, an interlayer film overlies a top surface of the semiconductor substrate on which the device cell structure is formed and is formed with a first contact hole through the interlayer film. In the termination region, an interlayer film overlies a top surface of the field oxide layer. The interlayer film is subjected to graphical etching, so that the first thickness of the interlayer film in the terminal area and the second thickness of the interlayer film in the active area are independently set, the second thickness is smaller than or equal to the thickness required by the depth-to-width ratio of the first contact hole, the first thickness is larger than the second thickness, and the reliability of the power device is guaranteed by increasing the first thickness. The invention further discloses a manufacturing method of the power device. Long-term reliability of the device can be improved, and application of the device in the field of vehicle gauges can be expanded.

The invention provides a multi-suspension shield grid MOSFET and a preparation method thereof, a shield grid is divided into a left part, a middle part and a right part, the left part and the right part are symmetrically distributed along the middle part, the upper part width of the middle part is larger than the lower part width, and the top of the middle part is higher than the tops of the left part and the right part. The middle part of the shield gate is connected with a source electrode, the left and right parts are floating, in a blocking state, the left and right floating shield gates can improve electric field distribution in the middle of a drift region, the thicker field oxide layer at the bottom can bear a higher electric field, and device breakdown at the bottom of the shield gate electrode is avoided. The output capacitance Coss contributed by the shield gate electrode is reduced while the reliability is improved, the switching loss is reduced, and the on-resistance is lower when the withstand voltage is the same.

According to the 4H-SiC MOSFET chip and the main junction region structure and the manufacturing method thereof, the main junction region structure of the 4H-SiC MOSFET chip is characterized in that an N-drift layer is formed on a substrate, a P well is embedded in the N-drift layer, a field oxide layer is arranged on the surface of the P well, the field oxide layer is divided into a plurality of field oxide blocks within the range of the P well, electric field distribution of a transition region is optimized, and the field effect of the N-drift layer is improved; electric field peak intensity is weakened, electric field concentration is avoided, dynamic avalanche breakdown probability is reduced, chip breakdown voltage performance is guaranteed, capacitance distribution of a transition area is adjusted, coupling effect of parasitic gate-drain capacitance is reduced, displacement current is reduced, gate misconduction is avoided, and local temperature rise and stress of the transition area are relieved. The stress transition layer is arranged between the field oxide layer and the P well, thermal expansion and cold contraction differences are reduced, the interface matching performance is improved, the stress transition layer is matched with the field oxide layer, thermal stress concentration can be reduced, the interface crack and stripping risk is remarkably reduced, and the structural stability of the main junction region is improved.

A method includes: forming a first oxide layer having a thickness of 400 nm or less on a first main surface of a semiconductor wafer; forming a second layer on the first oxide layer; altering an etch rate of at least a first part of the second layer such that a horizontal component (r1) of the etch rate is greater than a vertical component (r2) of an etch rate of the first oxide layer; etching the oxide layers through an opening in a mask using an isotropic etchant, wherein due to the difference between r1 and r2, a first thickness transition region of the first oxide layer under the mask is etched with a taper of less than 45 degrees relative to the first main surface; after the etching, removing the second layer and then forming a gate oxide adjacent to the first thickness transition region.

This invention provides a three-dimensional SiC superjunction diode and its fabrication method. The diode comprises a p+ type SiC epitaxial layer arranged in multiple spaced hemispheres, with an n+ type SiC epitaxial layer deposited on top. An n+ type electron transport layer is positioned between two hemispheres on the left side of the diode and located inside the n+ type SiC epitaxial layer. A field oxide passivation layer is deposited on the right side of the n+ type SiC epitaxial layer. A groove is located at the center of each hemisphere, directly opposite the anode PAD. This invention utilizes an annealing and reflow process with an alkaline earth-doped silicon oxide mask to achieve the three-dimensional structure etching mask, solving the problem of realizing a three-dimensional superjunction structure. This results in a three-dimensional superjunction structure with multiple hemispheres formed by the p+ type SiC epitaxial layer. The superjunction diode fabricated based on this structure exhibits superior voltage-resistance balance and can achieve lower resistance under the same voltage level.

The invention discloses a manufacturing method of a U-shaped groove, which is characterized in that a photoresist reserved on a field oxide in an X-direction photoetching process of the U-shaped groove can protect a hard mask on the field oxide of a Y-direction opening of a non-U-shaped groove region, the loss of the hard mask on the field oxide of the Y-direction opening of the non-U-shaped groove region cannot be caused, and a U-shaped groove process window is enlarged; in the process of performing X-direction silicon etching to form a U-shaped groove, silicon at an X-direction opening at a non-overlapping position of an X-direction opening pattern and a Y-direction opening pattern is protected by a mask first silicon oxide layer and a mask second silicon nitride layer, when the mask at the position is removed, the mask second silicon nitride layer is removed firstly, then the first silicon oxide layer is removed, and the first silicon oxide layer is removed after the mask second silicon nitride layer is removed. The SIN hard mask on the field oxide is not damaged, and the morphology standard of the U-shaped groove can be ensured.

The invention provides an LDMOS device and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a substrate, forming a first oxidation material with a preset thickness on the substrate, and forming a first oxidation layer; forming a dielectric material layer, and performing ion implantation on the substrate around the first oxide layer by using the dielectric material layer; a preset photomask is adopted to perform patterning on the dielectric material layer, the surface of the substrate is exposed, the remaining dielectric material layer covering the surface of the first oxide layer serves as a dielectric layer, the remaining dielectric material layer covering the side wall of the first oxide layer serves as a side wall layer, and the dielectric layer is connected with the side wall layer; a second oxide layer is formed on the surface of the substrate, the second oxide layer is connected with the side wall layer, and the thickness of the second oxide layer is smaller than the preset thickness; a conductive layer is formed, and a patterning process is performed to form a field oxide structure and a field plate. The performance of the ROX structure in the LDMOS device can be improved, and the preparation process of the ROX structure can be simplified.

The invention provides a shield gate trench MOSFET device and a preparation method thereof, in the preparation method, a first polycrystalline silicon layer with a certain height is exposed through back etching, then the first polycrystalline silicon layer with the certain height is oxidized into an isolation oxide layer by using a two-time thermal oxidation process, the residual first polycrystalline silicon layer is buried in a field oxide layer and the isolation oxide layer, and the field oxide layer and the isolation oxide layer are separated from each other. Finally, the gaps between the isolation oxidation layers on the tops of the shielding grids and the isolation oxidation layers on the side walls of the first grooves are filled with the grids, the shielding grids are located below the grids, dislocation of the shielding grids and the grids is achieved, and overlapping of the shielding grids and the grids on transverse projection is eliminated; the capacitance between the grid electrode and the shielding grid is greatly reduced, the switching loss of the device is reduced, the switching rate is improved, the brand-new structure is not limited by the width of the groove, the process difficulty is lower, and a smaller unit size is easier to realize.

The invention discloses a method for improving voltage resistance of a transverse transistor device by adopting irradiation. The method comprises the following steps: providing a silicon wafer as a substrate; forming a buried layer and a base deep well region on the substrate; pN junction isolation structures are formed on the two sides of the buried layer respectively, and a base deep junction well region connected with one end of the buried layer is formed; isolation grooves are formed between the emitter region and the collector regions on the two sides; filling an isolation medium in the isolation groove, and forming a thick field oxygen isolation structure on the base deep well region; completing the manufacturing of a base electrode, an emitter electrode and a collector electrode; a surface of the lateral transistor device is irradiated. According to the invention, a longitudinal base region current channel is formed through the isolation groove, electric leakage between an emitter and a collector of the device is greatly reduced, surface inversion of the device is reduced through irradiation of the surface of the transverse transistor device, CE voltage resistance of the device is further improved while CE spacing of the device is reduced, and the device is suitable for large-scale production. Therefore, the integration level of the transverse transistor high-power device can be improved.

The invention discloses a current regulative diode chip terminal structure, a chip and a manufacturing method of the current regulative diode chip terminal structure, and belongs to the technical field of semiconductor power devices. The terminal structure is located at the edge of an N-silicon epitaxial layer and comprises a cell-terminal transition region and a terminal region. The transition region is provided with a P region, a P + region and an N + region in the P region, and a first polycrystalline silicon layer located on the surface passivation oxide layer, and the P region and the P + region and the N + region are connected through front metal. The terminal region is provided with a P region connected with the transition region, a P + region in the P region and a thicker field oxide layer; the front metal is connected with the P + region through a contact hole, and the metal is connected with the transition region metal. The invention further discloses a current regulative diode chip comprising the terminal structure and a manufacturing method of the current regulative diode chip. According to the scheme, smooth transition and effective modulation of the electric field are realized through optimized design of the transition region and the selectable terminal field plate in combination with accurate and controllable process parameters, and the breakdown voltage and reliability of the chip are remarkably improved.

The invention belongs to the technical field of power devices, and provides a trench gate MOSFET, a preparation method thereof and a chip, a P-type shielding region is formed at the bottom of a gate oxide layer with a concave trench, an N-type injection region is formed between the P-type shielding region and the bottom of the gate oxide layer, and the two ends of the P-type shielding region are in contact with the edge region of the bottom of the gate oxide layer respectively, so that the trench gate MOSFET is formed. A gate material layer is formed in a groove of a gate oxide layer, a field oxide layer and the gate oxide layer form a closed structure wrapping the gate material layer, a PN junction is formed between a P-type shielding region and an N-type drift region, and a PN junction is formed between the P-type shielding region and an N-type injection region, so that the area of a depletion region can be increased under the condition of reverse bias of the device, and the device reliability is improved. Therefore, the breakdown voltage is improved, and the purpose of optimizing the static quality factor is achieved.

The invention relates to a semiconductor device comprising: a source region; the conduction type of the drain electrode region is the same as that of the source electrode region; the field oxide layer is located between the source electrode region and the drain electrode region; the grid electrode is located between the source electrode region and the drain electrode region and extends to the field oxide layer from the edge of the source electrode region; the resistive field plate is located on the field oxide layer, a plurality of series diodes obtained through N-type doping and / or P-type doping are formed on the resistive field plate, and the conduction direction of one part of the series diodes is opposite to the conduction direction of the other part of the series diodes; the resistive field plate is electrically connected with the drain electrode region and the grid electrode. When a potential difference exists between the grid electrode and the drain electrode, a part of diodes of the resistive field plate are reversely biased, so that electric leakage is blocked.

Aspects of the present disclosure are directed to an apparatus including a circuit region and a fluidic region. In a particular example, the circuit region with logical circuits thereon, includes a thermal oxide layer on a silicon substrate, and a dielectric layer over the field oxide layer, the dielectric layer including a doped dielectric film. The microfluidic device further includes a fluidic region including fluid ports formed through a surface of the apparatus and including an un-doped dielectric film. The fluidic region includes an aperture in the dielectric layer, where the aperture is defined by a dielectric wall which forms part of the dielectric layer. A sealing film deposited over the dielectric wall may prevent the doped dielectric film from contacting fluid contained in the fluid port.

A diode formed by a polysilicon layer is disposed between a field oxide film and an interlayer insulating film, in a semiconductor substrate, at a front surface of the semiconductor substrate. One resist mask is used to form contact holes of the interlayer insulating film and contact trenches and a p+-type region of the polysilicon layer. The contact trenches are continuously formed from bottoms of the contact holes, respectively, in a depth direction. A low-resistance contact between the p+-type region and an anode electrode is formed at least at a bottom of the contact trench. During the formation of the p+-type region, while a p-type impurity is ion-implanted in an inner wall of the contact trench 3b, an n-type cathode region maintains an n-type conductivity thereof and a contact with a cathode electrode is formed at sidewalls of the contact trench.

The invention discloses a manufacturing method of an SGT device. The manufacturing method comprises the following steps: step 1, forming a gate trench; and 2, performing field oxygen growth to form a field oxide layer. And step 3, forming a step polycrystalline silicon field plate of the current layer in the gate trench by adopting polycrystalline silicon deposition and back etching. And step 4, performing field oxygen etching to reduce the thickness of the field oxide layer on the top surface of the step polycrystalline silicon field plate of the current layer. Step 5, repeating the step 3 and the step 4 to obtain a groove field plate formed by overlapping multiple layers of stepped polycrystalline silicon field plates; and the step 4 after the step 3 corresponding to the step polycrystalline silicon field plate on the topmost layer is completed is omitted. And step 6, forming a first inter-electrode dielectric layer on the top surface of the trench field plate and removing the hard mask layer. And 7, forming a gate dielectric layer. And step 8, filling a gate conductive material layer. According to the invention, the polysilicon field plate and the field oxide layer with the stepped structure can be realized, the longitudinal distribution of the electric field intensity of the drift region can be optimized, and the withstand voltage of the device can be improved.

The present disclosure relates to a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: forming a hard mask on a main surface of a wafer; performing active region photolithography and etching, and removing the hard mask at a position where a field oxide layer needs to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, wherein the photoresist layer covers a position where no drift region needs to be formed; and performing drift region implantation by using the photoresist layer as an implantation blocking layer, wherein ions implanted during drift region implantation pass through the hard mask and the field oxide layer and enter the wafer. In the present disclosure, during drift region implantation, the implanted ions at the edge of the field oxide layer are blocked by using the hard mask, so as to avoid excessive PN junction depth and excessively high ion doping concentration at this position. Rapid depletion of the implanted ions in a JFET region at this position is achieved, thereby reducing the electric field strength at this position, and optimizing and improving the voltage withstand and reliability of the device.