215 results about "Field oxide" patented technology

The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

The invention provides a shield gate trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, according to the manufacturing method, a field oxide layer is formed twice (a first oxide layer and a second oxide layer), a polycrystalline silicon interlayer is introduced between the first oxide layer and the second oxide layer, and the polycrystalline silicon interlayer is only reserved on a side wall opposite to a non-floating shield gate layer after being etched twice, so that the field oxide layer is formed in the first oxide layer and the second oxide layer; and a floating shield grid layer is formed. As the floating shield grid layer is introduced to the side wall opposite to the non-floating shield grid layer, the field intensity of the middle area in the depth direction of the groove can be increased, and the overall voltage endurance capability is improved. The floating shield gate layer is introduced into the shield gate trench MOSFET structure, so that the voltage withstanding level of a device can be improved, and the voltage withstanding level of the device can be improved by utilizing a capacitive coupling effect between a part of the floating shield gate layer and a part of the floating shield gate layer and a capacitive coupling effect between a source electrode and the drain electrode. Therefore, gate-drain capacitance and source-drain capacitance of the device can be reduced, and switching speed of the device is improved.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

A semiconductor device includes: a recess along a top surface of a semiconductor substrate, the recess having a first sidewall and a second sidewall laterally opposite each other; a nitride-based spacer layer extending along the first sidewall of the recess; and a field oxide layer in the recess extending along a bottom surface of the recess. The second sidewall is defined by a shallow trench isolation structure extending into the semiconductor substrate. A lateral tip of the field oxide layer is blocked by the nitride-based spacer layer from laterally extending beyond the first sidewall into the semiconductor substrate.

The present invention provides a semiconductor device and a manufacturing method thereof, the manufacturing method comprising: forming first and second trench regions in a semiconductor substrate having an active region and a lead-out region, and defining first and second mesa regions; forming a field oxide layer covering the inner wall of the groove and each mesa area, and filling a first polycrystalline silicon layer; forming a mask layer with a first opening (exposing the active region) and a second opening (exposing the second mesa region); synchronously removing the field oxide layers on the table tops of the two areas through one-time wet etching, so that the two table top areas obtain consistent surface height reference; a gate structure is then formed. The step difference between the two intervals is eliminated from the source through synchronous etching, accumulation and amplification of morphology deviation in the follow-up process are avoided, and the uniformity of the dielectric layer, the photoetching precision and the injection consistency are remarkably improved. According to the method, additional masks or planarization modules do not need to be added, the process is simplified, the cost is reduced, and the reliability and the yield of the device are greatly improved.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

The invention provides a high-voltage Resurf LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure capable of resisting a single-particle burning effect. The device comprises a P-type substrate, an N-type epitaxy, a P-type buried layer, a P-type well region, a source region P + injection, an N-type well region, a source region N + injection, a drain region N + injection, a gate oxide layer, a field oxide layer, polycrystalline silicon and metal. According to the invention, the unequal-length P-type buried layer is introduced into the N-type drift region, and the P-type buried layer is directly connected with the P-type substrate, so that an extra leakage path is provided for hole current generated by single-particle radiation. A long P-type buried layer is introduced below an N-type drift region to improve the extraction capability of hole current, a short P-type buried layer is introduced above the N-type drift region to relieve the electric field concentration phenomenon of a drain side N + region, and the unequal-length P-type buried layers act together to inhibit the parasitic triode self-maintenance phenomenon caused by single-particle incidence and improve the single-particle burnout resistance of the device.

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, an isolation structure and a field oxide layer. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type, and is disposed on the substrate. The isolation structure has a first conductivity type and is disposed in the epitaxial layer. The isolation structure comprises a first well, a second well and a doped region arranged between the first well and the second well. The field oxide layer is disposed on the epitaxial layer. Wherein the field oxide layer exposes the top surface of the epitaxial layer between the first well and the doped region or exposes the top surface of the epitaxial layer between the second well and the doped region.

The invention discloses a drain extension field effect transistor and a preparation method, and relates to the technical field of semiconductor preparation. The drain expansion field effect transistor comprises a field oxidation structure, a field plate structure, a gate structure, a drain region and a source region, and the drain region and the source region are located on the two sides of the field oxidation structure. The field oxidation structure is divided into a first region, a second region and a third region, the second region is located between the first region and the third region, the field plate structure is located above the third region, the upper part of the second region is empty, one part of the gate structure covers the upper part of the first region, and the other part of the gate structure is close to the source region. According to the drain extended field effect transistor, the gate structure and the field plate structure of the drain extended field effect transistor are separated, so that specific voltage can be independently applied to the field plate structure to reduce conduction loss, switching loss and temperature rise of a device, and the problems of poor performance and low reliability of the device in the prior art are solved.

The application provides a high-frequency semiconductor device with improved voltage resistance and a manufacturing method thereof. The device comprises a first conductive type substrate, a first conductive type epitaxial layer arranged on the first conductive type substrate, a single-cell groove arranged in the first conductive type epitaxial layer, a top space arranged in the single-cell groove, a field oxide layer arranged on the inner wall below the top space in the single-cell groove, a gate oxide layer arranged on the sidewall of the top space in the single-cell groove, a first polysilicon field plate arranged in the middle of the single-cell groove, a second polysilicon field plate and a third polysilicon field plate arranged on both sides of the top of the first polysilicon field plate in the single-cell groove, the first polysilicon field plate, the second polysilicon field plate and the third polysilicon field plate being all arranged below the top space of the single-cell groove, and a first gate polysilicon and a second gate polysilicon being arranged on both sides of the top space in the single-cell groove. The application can improve the voltage resistance of the device and the working frequency of the device simultaneously.

A semiconductor device includes: a recess along a top surface of a semiconductor substrate, the recess having a first sidewall and a second sidewall laterally opposite each other; a nitride-based spacer layer extending along the first sidewall of the recess; and a field oxide layer in the recess extending along a bottom surface of the recess. The second sidewall is defined by a shallow trench isolation structure extending into the semiconductor substrate. A lateral tip of the field oxide layer is blocked by the nitride-based spacer layer from laterally extending beyond the first sidewall into the semiconductor substrate.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The present invention discloses a field plate terminal structure with single particle radiation reinforcement and a preparation method thereof, belonging to the field of microelectronics technology. The structure includes a substrate, an epitaxial layer, a device main junction region and a carrier lifetime control region, a field oxide layer, an anode, a field plate, which is arranged on the field oxide layer, and a cathode, wherein the anode is in contact with the field plate; the carrier lifetime control region is located in the region of the field plate corresponding to the epitaxial layer. The present invention reduces the number of hole carriers moving to the edge of the main junction by introducing a carrier lifetime control layer (i.e., the carrier lifetime control region) on the upper surface layer of the semiconductor material in the terminal region, thereby alleviating the current density and heat accumulation at the edge of the main junction and improving the SEB resistance of the field plate terminal structure.

The application provides a semiconductor device, comprising a U-shaped boost diode, the U-shaped boost diode comprising a first isolation structure arranged below a first field oxide region, a source terminal and a base terminal, and a second isolation structure arranged below a second field oxide region, the first isolation structure and the second isolation structure are arranged in the same layer and are spaced apart, and a part of the first isolation structure along a thickness direction and a part of the second isolation structure along the thickness direction are located in a substrate, and the remaining part of the first isolation structure along the thickness direction and the remaining part of the second isolation structure along the thickness direction are located in an epitaxial layer. The second isolation structure in the application can disperse the electric field across the high potential, so as to prevent the electric field from concentrating, so that the electric field does not concentrate at the source terminal at the bottom of the U-shaped boost diode, and the breakdown voltage BV of the boost diode in the semiconductor device is increased.

The present invention provides a manufacturing method and structure of an IGBT device. The method includes: providing a substrate, the substrate including an active region, a transition region and a terminal region, and including opposite first and second main surfaces; performing a first ion implantation on the first main surfaces of the transition region and the terminal region to form a doped terminal layer spanning the transition region and the terminal region, and performing a second ion implantation on the edge of the terminal region to form a cutoff ring, and then performing a thermal process push treatment; etching the first main surface of the terminal region to form a trench communicating the doped terminal layer and the cutoff ring, and forming a field oxide layer in the trench; performing a second ion implantation on the first main surface to form a carrier storage doped region, and then performing a thermal process push treatment; forming a front structure and a back structure. When manufacturing the carrier storage doped region in the active region in the present invention, implantation can be performed without a mask plate, thereby saving manufacturing costs and at the same time avoiding a great influence of the carrier storage layer on the breakdown voltage of the IGBT.

The present invention discloses a method for manufacturing a U-shaped groove, comprising: providing a semiconductor substrate on which field oxide is formed, wherein in a first region, the field oxide is used to isolate parallel-arranged first active regions. Forming a hard mask layer in the first region. Performing a first patterned etching on the hard mask layer to form a first groove and a first hard mask layer strip. The first groove is located directly above the first active region and exposes the top surface of the first active region. Applying an organic bottom layer. Performing a second patterned etching on the organic bottom layer to form an organic bottom layer pattern having a second groove, wherein the length directions of the first and second grooves are perpendicular, the second groove has a first overlapping region that overlaps with the first groove, and the top surface of the first active region in the first overlapping region is exposed. Performing a third etching on the semiconductor substrate using the organic bottom layer pattern as a mask to form a U-shaped groove in the first overlapping region. The present invention can increase the process window, improve the morphology of the U-shaped groove, and simplify the process steps.

The present application relates to a lateral device, comprising: a source region (134) having a first conductivity type; a drain region (132) having the first conductivity type; a drift region (110) having the first conductivity type and at least partially located between the source region (134) and the drain region (132); a buried region (112) of a second conductivity type located in the drift region (110) between the source region (134) and the drain region (132); a field oxide layer (150) located on the drift region (110); a top-doped region (120) located in the drift region (110) that is above the buried region (112) of the second conductivity type and below the field oxide layer (150), the top-doped region comprising at least one doped layer of the first conductivity type, and the doped layer of the first conductivity type having a doping concentration greater than that of the drift region (110); and field plates (140) located on the field oxide layer (150).

Disclosed are a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor substrate; etching the substrate to form a trench in the substrate; filling the trench with insulating material; etching the insulating material to expose a sharp corner at the intersection of the trench sidewall and the upper surface of the substrate; and forming a field oxide layer on part of the upper surface of the substrate and the insulating material, wherein the sharp corner at the intersection of the trench sidewall and the upper surface of the substrate is oxidized in the step of forming the field oxide layer. The method exposes a sharp corner at the intersection of the shallow trench isolation structure and the substrate surface by etching back the shallow trench isolation structure, and eliminates the sharp corner in the step of forming the field oxide layer, thereby avoiding charge accumulation at the sharp corner and improving the breakdown voltage and reliability of the device.

The utility model provides a double-gate oxide MOS (Metal Oxide Semiconductor) structure, which comprises a substrate, a high-voltage well region and a low-voltage well region, the low-voltage well region comprises a thin gate oxide layer and a low-voltage side gate which are located on the surface of the low-voltage well region, and low-voltage side source / drain regions which are located in the low-voltage well region and located on the two sides of the low-voltage side gate, and the high-voltage well region comprises a high-voltage side gate oxide layer and a high-voltage side gate which are located on the surface, a drift region located in the high-voltage well region, and high-voltage side source / drain regions located on the two sides of the high-voltage side gate oxide layer; the high-voltage side gate oxide layer comprises a thick gate oxide layer and a first field oxide layer which are arranged in an overlapped mode in the gate length direction and only covers the high-voltage side gate instead of covering the whole high-voltage well region, so that a thick film layer exists in a region corresponding to the high-voltage side gate in the follow-up manufacturing process of the polycrystalline silicon gate, and when the polycrystalline silicon layer is etched to form the two gates, the high-voltage side gate oxide layer is formed. The residual film difference of other regions is small, so that LDD injection and the injection dose and depth of the source / drain region can be accurately controlled, and the electrical performance and reliability of the double-gate oxide MOS structure are further improved.

Disclosed in the present invention is a method for manufacturing a mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design. The method comprises the steps of: 1) growing a field oxide layer above a P-type well of an analog integrated circuit; 2) depositing a polycrystalline capacitor lower electrode plate polycrystalline film layer on a field oxide layer above an N-type well, and performing matched implantation doping; 3) growing a capacitor dielectric layer; 4) depositing a polycrystalline capacitor upper electrode plate polycrystalline film layer, and manufacturing a protective film layer and a protective structure. The mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design comprises a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low-dielectric-coefficient filling film layer, a metal interconnection film layer, and a passivation layer. The present invention reduces the impact of parasitic capacitance, substrate noise and crosstalk noise, and realizes the low noise characteristic of integrated capacitors.

The present application provides a semiconductor device. The semiconductor device includes: a substrate having a first conductivity type; a shallow trench isolation structure disposed in the substrate and having a first annular structure, wherein the region of the substrate surrounded by the shallow trench isolation structure is an active region; a drain doped region having a second conductivity type, disposed on the upper surface of the central region of the active region; a source doped region having a second conductivity type, disposed on the upper surface of the active region on both sides of the drain doped region and spaced apart from the drain doped region; a field oxide layer disposed on the upper surface of the substrate within the active region and having a second annular structure, surrounding the drain doped region; a gate polycrystalline layer disposed on the upper surface of the substrate and having a third annular structure, surrounding the field oxide layer; and a drift region having a second conductivity type, disposed in the substrate and surrounding the drain doped region.

The invention provides an anti-radiation transverse integrated power semiconductor device. The anti-radiation transverse integrated power semiconductor device comprises a P-type substrate, an N-type epitaxial region, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a first P-type doped region and a second P-type doped region, the first dielectric layer is arranged on the surface of an active region of the device, the second dielectric layer is arranged on the surface of a field region of the device, and the active region is of a closed structure and covers and exceeds the first N-type doped region; and the polycrystal gate is arranged on the surface of the first dielectric layer. The drift region of the transverse device is of a longitudinal structure, the surface of the drift region is not provided with a thick field oxide layer, and a large amount of charges generated by total dose radiation are avoided, so that the influence of the total dose radiation effect on the performance of the device is greatly reduced, and the device has high total dose radiation resistance.

Provided in the present application are an LDMOS device and a preparation method therefor. A substrate has a channel region and a drift region, a drain region is provided in the drift region, and a trench, which has a first field plate region, a second field plate region and a third field plate region connected in sequence, is provided between the drain region and the channel region; a first field oxide is located in the first field plate region, a second field oxide is located in the second field plate region, and a third field oxide is located in the third field plate region, with the thicknesses of the third field oxide and the first field oxide both being greater than the thickness of the second field oxide, and the height of the first field oxide being less than or equal to the distance between the bottom of the trench and the channel region; in the direction from the bottom of the trench to the opening of the trench, a gate oxide layer is disposed on the first field oxide and is located in the trench; gate polycrystalline silicon fills the space above the first field oxide and the second field oxide in the trench, and the surfaces of the gate polycrystalline silicon and the third field oxide away from the trench are flush with the opening of the trench; and the gate oxide layer and the third field oxide are disposed on the side surfaces of the gate polycrystalline silicon, so as to reduce the transverse dimensions of the device and improve voltage resistance.

The present disclosure provides a metal oxide semiconductor device and a method for manufacturing the same. The metal oxide semiconductor device includes a semiconductor substrate, a patterned field oxide layer, first JFET implantation regions and second JFET implantation regions. Active regions and gate regions are formed on an upper surface of the semiconductor substrate, each active region is surrounded by two or more of the gate regions, and the gate regions form a grid and some gate regions overlap to form gate intersections. The first JFET implantation regions are formed by implanting ions underneath the gate intersections of the upper surface of the semiconductor substrate. Orthogonal projections of the first JFET implantation regions and the field oxide layer onto the substrate don't overlap. The second JFET implantation regions are formed by implanting ions into the upper surface of the semiconductor substrate and located underneath the gate regions that are not gate intersections.

The invention discloses a power device. The power device comprises an interlayer film. The semiconductor substrate is divided into an active region and a termination region. A device unit structure is formed in the active region; and a field oxide layer surrounding the periphery of the active region is formed in the terminal region. In the active region, an interlayer film overlies a top surface of the semiconductor substrate on which the device cell structure is formed and is formed with a first contact hole through the interlayer film. In the termination region, an interlayer film overlies a top surface of the field oxide layer. The interlayer film is subjected to graphical etching, so that the first thickness of the interlayer film in the terminal area and the second thickness of the interlayer film in the active area are independently set, the second thickness is smaller than or equal to the thickness required by the depth-to-width ratio of the first contact hole, the first thickness is larger than the second thickness, and the reliability of the power device is guaranteed by increasing the first thickness. The invention further discloses a manufacturing method of the power device. Long-term reliability of the device can be improved, and application of the device in the field of vehicle gauges can be expanded.

The invention provides a multi-suspension shield grid MOSFET and a preparation method thereof, a shield grid is divided into a left part, a middle part and a right part, the left part and the right part are symmetrically distributed along the middle part, the upper part width of the middle part is larger than the lower part width, and the top of the middle part is higher than the tops of the left part and the right part. The middle part of the shield gate is connected with a source electrode, the left and right parts are floating, in a blocking state, the left and right floating shield gates can improve electric field distribution in the middle of a drift region, the thicker field oxide layer at the bottom can bear a higher electric field, and device breakdown at the bottom of the shield gate electrode is avoided. The output capacitance Coss contributed by the shield gate electrode is reduced while the reliability is improved, the switching loss is reduced, and the on-resistance is lower when the withstand voltage is the same.

According to the 4H-SiC MOSFET chip and the main junction region structure and the manufacturing method thereof, the main junction region structure of the 4H-SiC MOSFET chip is characterized in that an N-drift layer is formed on a substrate, a P well is embedded in the N-drift layer, a field oxide layer is arranged on the surface of the P well, the field oxide layer is divided into a plurality of field oxide blocks within the range of the P well, electric field distribution of a transition region is optimized, and the field effect of the N-drift layer is improved; electric field peak intensity is weakened, electric field concentration is avoided, dynamic avalanche breakdown probability is reduced, chip breakdown voltage performance is guaranteed, capacitance distribution of a transition area is adjusted, coupling effect of parasitic gate-drain capacitance is reduced, displacement current is reduced, gate misconduction is avoided, and local temperature rise and stress of the transition area are relieved. The stress transition layer is arranged between the field oxide layer and the P well, thermal expansion and cold contraction differences are reduced, the interface matching performance is improved, the stress transition layer is matched with the field oxide layer, thermal stress concentration can be reduced, the interface crack and stripping risk is remarkably reduced, and the structural stability of the main junction region is improved.