126 results about "High voltage transistors" patented technology

A reference current generating circuit including a reference voltage generating circuit and a current source circuit is provided. The reference voltage generating circuit generates a first reference voltage according to a first current. The reference voltage generating circuit includes a native transistor device, and the first current flows through the native transistor device. The current source circuit is coupled to the reference voltage generating circuit. The current source circuit generates a reference current according to the first reference voltage. The current source circuit includes a cascode transistor circuit, and the reference current flows through the cascode transistor circuit. The cascode transistor circuit includes a low-voltage transistor device and a high-voltage transistor device coupled in series.

Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

The present disclosure describes a method for the formation of n-type and p-type epitaxial source / drain structures with substantially co-planar top surfaces and different depths across input / output (I / O) and non-I / O regions of a substrate. In some embodiments, the method includes forming fin structures and a planar portion on a substrate. The method also includes forming first gate structures on the fin structures and second gate structures on the planar portion. The method also includes etching the fin structures between the first gate structures to form first openings and etching the planar portion between the second gate structures to form second openings. Further, the method includes forming first epitaxial structures in the first openings and second epitaxial structures in the second openings, where top surfaces of the first and second epitaxial structures are substantially co-planar and bottom surfaces of the first and second epitaxial structures are not co-planar.

A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.

The application discloses a micro-power-consumption fast-response low-voltage-difference linear voltage stabilizer with mode control function, which comprises a dual-mode controller, a SET end of an external partial voltage resistor is connected to a negative phase input end of the dual-mode controller, a positive phase end of the dual-mode controller is connected to GND, an output end of the dual-mode controller is connected to a positive phase input end of a controller of an error amplifier, and the dual-mode controller is used for adjusting the stabilizer to be in a fixed output voltage mode or an adjustable output voltage mode; a negative phase input end of the error amplifier is connected to a reference voltage V REF , an output end is connected to an input end of a driving circuit with voltage clamping function; an output end of the driving circuit with voltage clamping function is connected to a gate of an M p1 high-voltage PMOS transistor, a substrate and a source are connected to an input voltage V IN , and a drain is connected to an output end OUT of the stabilizer; when the linear voltage stabilizer is applied, the type of capacitor and the equivalent resistance of capacitor series connection do not need to be considered, and the needs of micro-power-consumption electronic system power supply and battery power supply system can be met.

The present application provides an electrostatic protection circuit and an electronic device, wherein the electrostatic protection circuit includes: a detection module, the detection module is used to output an enable signal when an electrostatic pulse is input to the positive input terminal of a power supply; a clamping module, the clamping module is used to discharge the electrostatic pulse at the positive input terminal of the power supply to the negative input terminal of the power supply in response to the enable signal; wherein the clamping module includes a plurality of clamping transistors connected in series between the positive input terminal of the power supply and the negative input terminal of the power supply, and the maximum source-drain voltage of the clamping transistor is less than or equal to a preset value; the detection module includes at least one detection unit, each detection unit is connected in parallel between the positive input terminal of the power supply and the negative input terminal of the power supply, and each clamping transistor is turned on in response to the enable signal output by the same or different detection units. The present application adopts a plurality of low-voltage clamping transistors connected in series to replace the traditional high-voltage transistor, which is conducive to quickly discharging the electrostatic pulse current and reducing the circuit area of ​​the electrostatic protection circuit.

A deep trench structure may be formed to include a doped polysilicon core and dielectric isolation layers on the sidewalls of the doped polysilicon core. The deep trench structure may be provided as a deep trench isolation structure that laterally surrounds transistors in a semiconductor device. Additionally and / or alternatively, the deep trench structure may be included in a high-voltage transistor as a vertical drain region that extends into a semiconductor layer of a semiconductor device.

A structure of a semiconductor device, including a substrate, is provided. A first gate insulating layer is disposed on the substrate. A second gate insulating layer is disposed on the substrate. The second gate insulating layer is thicker than the first gate insulating layer and abuts the first gate insulating layer. A gate layer has a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer. A dielectric layer has a top dielectric layer and a bottom dielectric layer. The top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate. A field plate layer is disposed on the dielectric layer and includes a depleted region, and is at least disposed on the bottom dielectric layer. A method for fabricating the semiconductor device is provided too.

A vehicle propulsion system including a battery for supplying a direct current (DC), an inverter including a wide band gap transistor for converting the DC to an alternating current (AC) in response to a transistor control signal applied to a gate of the wide band gap transistor, a high voltage power switch coupled in anti-parallel with the wide band gap transistor to provide a path for the current when the wide band gap transistor is turned off, an inverter controller including a power supply for supplying a DC current, a current sensor for detecting a current level of the DC current, and a high voltage transistor for generating the transistor control signal in response to a variation of the current level and the DC current, and an electric motor configured to generate an electromotive torque in response to the AC voltage to propel a vehicle.

Embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes a peripheral circuit chip and a memory array chip, the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer, the first device layer including a plurality of high-voltage transistors; a second substrate disposed on the first circuit element layer and in contact with the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer, the second device layer including a plurality of low-voltage transistors; the memory array chip is disposed on the second circuit element layer.

The present application discloses a driving circuit, which includes a medium-voltage logic circuit and two voltage level converters, saving high-voltage transistor area and power consumption compared with traditional driving circuits, and minimizing the number of voltage level converters to control the output signal of the output stage circuit to be in one of four states.

A low-loss active high voltage power switch is provided. A vehicle propulsion system includes: a battery for supplying direct current (DC); an inverter including a wide bandgap transistor for converting DC into an alternating current (AC) in response to a transistor control signal applied to a gate of the wide bandgap transistor; the high-voltage power switch is coupled with the wide-band-gap transistor in an anti-parallel manner so as to provide a path for the current when the wide-band-gap transistor is turned off; an inverter controller including a power source for supplying the DC current, a current sensor for detecting a current level of the DC current, and a high voltage transistor for generating a transistor control signal in response to a change in the current level and the DC current; and a motor configured to generate an electromotive force torque to propel the vehicle in response to the AC voltage.

An electronic device includes a circuit module and a protection module. The circuit module includes a P-N junction between a reference terminal and an electrical node, and metal connection lines coupled to the electrical node and configured to be charged due to antenna effect. The protection module includes an HV transistor and a capacitor. The capacitor is connected between the electrical node and the HV transistor and configured to turn on the HV transistor when the electrical node charges positively due to the antenna effect. The circuit module is thus maintained at a potential that does not damage the electronic device.

A high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values and / or a composite gate structure having multiple regions of different work function values. The composite dielectric layer having multiple regions with different dielectric constant values and / or the composite gate structure having multiple regions with different work functions increases the threshold voltage uniformity across a channel region of the high-voltage transistor. The increased threshold voltage uniformity may enable a low subthreshold swing and a low subthreshold off-stage current leakage to be achieved for the high-voltage transistor, which increases the operating efficiency of the high-voltage transistor and enables the size of the high-voltage transistor to be reduced without increasing (or with minimal increase to) the subthreshold swing and and / or the subthreshold off-stage current leakage of the high-voltage transistor.

The present invention discloses a synchronous rectification chip circuit, which mainly solves the problems of high cost and multiple withstand voltage versions of synchronous rectification chips in the prior art. The circuit includes a synchronous rectification driving chip, a switch tube NH1 whose gate and drain are connected to the synchronous rectification driving chip, and a diode D7 whose positive electrode is connected to the drain of the switch tube NH1 and whose negative electrode is connected to the source of the switch tube; wherein the synchronous rectification driving chip also leads out a VIN pin to the output voltage VOUT end of the synchronous rectification chip circuit; the driving chip of the present invention is simple in design and low in cost, and synchronous rectification chips of different withstand voltage versions are realized by matching high-voltage transistors NH2 and switch tubes NH1 of different specifications, which greatly improves the application scope of the driving chip, reduces the resource allocation cost, and thus greatly reduces the cost of the switching power supply system.

The application provides a manufacturing method of a semiconductor device, before an active region manufacturing process, a substrate region to be manufactured into a high-voltage transistor is subjected to groove etching to form at least a gate oxide groove and a first depth adjusting groove and define an active region horn, the depth of the first depth adjusting groove is used to increase the bottom depth of a shallow trench isolation structure for isolating a source / drain region and a channel region of the high-voltage transistor, the breakdown voltage of the high-voltage transistor is increased, and by ion implantation and oxidation on the active region horn, a relatively thick first gate oxide layer is formed, the problem of the thin gate oxide layer of the high-voltage transistor at the top corner of the active region is solved, the leakage at the top corner of the active region is reduced, the hot carrier effect and the gate-induced drain leakage are reduced, and the first gate oxide layer can also be used as a barrier layer to block the lateral diffusion of oxygen in the process of forming a second gate oxide layer, thereby improving the beak effect on the source / drain region of the high-voltage transistor.

Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

A high-voltage transistor may include a planar active region for a first source / drain active region, a second source / drain active region, and / or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and / or may provide increased operational lifetime of the high-voltage transistor.

A semiconductor structure includes a first well, a second well, a first doping region, a second doping region, a field oxide layer, a third well, and a fourth well. The first well is N-type. The second well is P-type, adjacent to the first well and in contact with the first well at an interface. The first doping region is N-type and deposited in the first well. The second doping region is P-type and deposited in the second well. The field oxide layer is formed in the first well and deposited between the first doping region and the second doping region. The third well is N-type, formed in the first well, and deposited below the field oxide layer. The fourth well is N-type, formed in the first well, and deposited below the field oxide layer.

An improved structure of a lateral n-channel LDMOS transistor is provided to avoid gate-oxide breakdown that occurs during transistor operation. The LDMOS transistor includes a dielectric isolation structure that physically isolates a region including a parasitic NPN transistor from a region that generates a hole current due to weak impact ionization (i.e., the extended drain region of the LDMOS transistor). According to an embodiment of the present disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to reduce the gain of the parasitic NPN transistor and reduce the back-gate resistance in order to further improve the robustness of the LDMOS transistor.

The present invention relates to an electronic component package and a manufacturing method therefor. In an embodiment, the electronic component package comprises: a first metal layer, a high-voltage transistor semiconductor die, a first molding compound layer, a second metal layer, a first vertical connection structure, a second vertical connection structure, a control circuit bare chip, and a second molding compound layer. In the electronic component package of the present invention, a lead frame and electrical leads are replaced with the metal layers and the vertical connection structures, so that the position of the electrical connection of the chip is more flexible and the heat dissipation effect is better. Compared with the lead frames and the electrical leads, the electronic component package of the present disclosure is more suitable for packaging high-voltage or high-current chips.

A high voltage transistor may include a stepped dielectric layer between a field plate structure and a channel region of the high voltage transistor in a substrate. The stepped dielectric layer may increase the breakdown voltage of the high voltage transistor by reducing the electric field strength near the drain region of the high voltage transistor. In particular, a portion of the stepped dielectric layer near the drain region includes a thickness that is greater relative to a thickness of another portion of the stepped dielectric layer near the gate structure. The increased thickness near the drain region provides increased electric field suppression near the drain region (which operates at high voltages). In this way, the stepped dielectric layer enables the high voltage transistor described herein to achieve higher breakdown voltages without increasing the distance between the gate structure and the drain region of a high voltage transistor.

A reference current generating circuit including a reference voltage generating circuit and a current source circuit is provided. The reference voltage generating circuit generates a first reference voltage according to a first current. The reference voltage generating circuit includes a native transistor device, and the first current flows through the native transistor device. The current source circuit is coupled to the reference voltage generating circuit. The current source circuit generates a reference current according to the first reference voltage. The current source circuit includes a cascode transistor circuit, and the reference current flows through the cascode transistor circuit. The cascode transistor circuit includes a low-voltage transistor device and a high-voltage transistor device coupled in series.

A control circuit for preventing hot plugging during high-voltage lithium battery charging, comprising a charge pump module for converting the power supply voltage VDD into a high-voltage power supply V1, a clamping module for limiting the high-voltage power supply V1 to a fixed voltage. The clamping module includes a first clamping unit and a second clamping unit connected in series between the high-voltage power supply V1 and the ground terminal in sequence, a control switch MLC1, a high-voltage transistor MHV1, an LDO module for converting the power supply V2 voltage into the normal charging voltage VBAT of the battery, and a battery full detection circuit for detecting the charging state of the battery. When the battery is in the charging state, the high-voltage transistor MHV1 is turned on, and V2 = VIN; when the battery is in the full state, the battery full detection circuit outputs a high-level signal to the control switch MLC1, the control switch MLC1 is turned on, and the control switch MLC1 shorts the second clamping unit to reduce the voltage of the high-voltage power supply V1 to protect the LDO module.

The invention provides a test circuit for dynamic switching characteristics of a high-voltage power assembly and a test method thereof. The test method comprises the following steps: measuring a test voltage of a test endpoint between the first high-voltage transistor and the second high-voltage transistor; when the high-voltage power assembly is in a conducting state, in a first period, the first high-voltage transistor is driven to be conducted through a first signal, and the second high-voltage transistor is driven to be cut off through a second signal, so that the test voltage is equal to the to-be-tested voltage of the high-voltage power assembly. When the high-voltage power assembly is in a cut-off state, the first high-voltage transistor is driven to be cut off through the first signal, and the second high-voltage transistor is driven to be conducted through the second signal, so that the test voltage is clamped. The first signal and the second signal drive the first high-voltage transistor and the second high-voltage transistor not to be in a conducting state at the same time.

A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.

The present disclosure describes a method for the formation of n-type and p-type epitaxial source / drain structures with substantially co-planar top surfaces and different depths across input / output (I / O) and non-I / O regions of a substrate. In some embodiments, the method includes forming fin structures and a planar portion on a substrate. The method also includes forming first gate structures on the fin structures and second gate structures on the planar portion. The method also includes etching the fin structures between the first gate structures to form first openings and etching the planar portion between the second gate structures to form second openings. Further, the method includes forming first epitaxial structures in the first openings and second epitaxial structures in the second openings, where top surfaces of the first and second epitaxial structures are substantially co-planar and bottom surfaces of the first and second epitaxial structures are not co-planar.

The present application discloses a driving circuit, which includes a medium voltage logic circuit and two voltage level converters. Compared with a traditional driving circuit, it saves high voltage transistor area and power, and minimizes the number of voltage level converters to control the output signal of the output stage circuit to be in one of four states.