53 results about "High voltage transistors" patented technology

The present disclosure describes a method for the formation of n-type and p-type epitaxial source / drain structures with substantially co-planar top surfaces and different depths across input / output (I / O) and non-I / O regions of a substrate. In some embodiments, the method includes forming fin structures and a planar portion on a substrate. The method also includes forming first gate structures on the fin structures and second gate structures on the planar portion. The method also includes etching the fin structures between the first gate structures to form first openings and etching the planar portion between the second gate structures to form second openings. Further, the method includes forming first epitaxial structures in the first openings and second epitaxial structures in the second openings, where top surfaces of the first and second epitaxial structures are substantially co-planar and bottom surfaces of the first and second epitaxial structures are not co-planar.

A deep trench structure may be formed to include a doped polysilicon core and dielectric isolation layers on the sidewalls of the doped polysilicon core. The deep trench structure may be provided as a deep trench isolation structure that laterally surrounds transistors in a semiconductor device. Additionally and / or alternatively, the deep trench structure may be included in a high-voltage transistor as a vertical drain region that extends into a semiconductor layer of a semiconductor device.

A vehicle propulsion system including a battery for supplying a direct current (DC), an inverter including a wide band gap transistor for converting the DC to an alternating current (AC) in response to a transistor control signal applied to a gate of the wide band gap transistor, a high voltage power switch coupled in anti-parallel with the wide band gap transistor to provide a path for the current when the wide band gap transistor is turned off, an inverter controller including a power supply for supplying a DC current, a current sensor for detecting a current level of the DC current, and a high voltage transistor for generating the transistor control signal in response to a variation of the current level and the DC current, and an electric motor configured to generate an electromotive torque in response to the AC voltage to propel a vehicle.

Embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes a peripheral circuit chip and a memory array chip, the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer, the first device layer including a plurality of high-voltage transistors; a second substrate disposed on the first circuit element layer and in contact with the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer, the second device layer including a plurality of low-voltage transistors; the memory array chip is disposed on the second circuit element layer.

A low-loss active high voltage power switch is provided. A vehicle propulsion system includes: a battery for supplying direct current (DC); an inverter including a wide bandgap transistor for converting DC into an alternating current (AC) in response to a transistor control signal applied to a gate of the wide bandgap transistor; the high-voltage power switch is coupled with the wide-band-gap transistor in an anti-parallel manner so as to provide a path for the current when the wide-band-gap transistor is turned off; an inverter controller including a power source for supplying the DC current, a current sensor for detecting a current level of the DC current, and a high voltage transistor for generating a transistor control signal in response to a change in the current level and the DC current; and a motor configured to generate an electromotive force torque to propel the vehicle in response to the AC voltage.

An electronic device includes a circuit module and a protection module. The circuit module includes a P-N junction between a reference terminal and an electrical node, and metal connection lines coupled to the electrical node and configured to be charged due to antenna effect. The protection module includes an HV transistor and a capacitor. The capacitor is connected between the electrical node and the HV transistor and configured to turn on the HV transistor when the electrical node charges positively due to the antenna effect. The circuit module is thus maintained at a potential that does not damage the electronic device.

A high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values and / or a composite gate structure having multiple regions of different work function values. The composite dielectric layer having multiple regions with different dielectric constant values and / or the composite gate structure having multiple regions with different work functions increases the threshold voltage uniformity across a channel region of the high-voltage transistor. The increased threshold voltage uniformity may enable a low subthreshold swing and a low subthreshold off-stage current leakage to be achieved for the high-voltage transistor, which increases the operating efficiency of the high-voltage transistor and enables the size of the high-voltage transistor to be reduced without increasing (or with minimal increase to) the subthreshold swing and and / or the subthreshold off-stage current leakage of the high-voltage transistor.

The application provides a manufacturing method of a semiconductor device, before an active region manufacturing process, a substrate region to be manufactured into a high-voltage transistor is subjected to groove etching to form at least a gate oxide groove and a first depth adjusting groove and define an active region horn, the depth of the first depth adjusting groove is used to increase the bottom depth of a shallow trench isolation structure for isolating a source / drain region and a channel region of the high-voltage transistor, the breakdown voltage of the high-voltage transistor is increased, and by ion implantation and oxidation on the active region horn, a relatively thick first gate oxide layer is formed, the problem of the thin gate oxide layer of the high-voltage transistor at the top corner of the active region is solved, the leakage at the top corner of the active region is reduced, the hot carrier effect and the gate-induced drain leakage are reduced, and the first gate oxide layer can also be used as a barrier layer to block the lateral diffusion of oxygen in the process of forming a second gate oxide layer, thereby improving the beak effect on the source / drain region of the high-voltage transistor.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

A high voltage transistor may include a stepped dielectric layer between a field plate structure and a channel region of the high voltage transistor in a substrate. The stepped dielectric layer may increase the breakdown voltage of the high voltage transistor by reducing the electric field strength near the drain region of the high voltage transistor. In particular, a portion of the stepped dielectric layer near the drain region includes a thickness that is greater relative to a thickness of another portion of the stepped dielectric layer near the gate structure. The increased thickness near the drain region provides increased electric field suppression near the drain region (which operates at high voltages). In this way, the stepped dielectric layer enables the high voltage transistor described herein to achieve higher breakdown voltages without increasing the distance between the gate structure and the drain region of a high voltage transistor.

The present disclosure describes a method for the formation of n-type and p-type epitaxial source / drain structures with substantially co-planar top surfaces and different depths across input / output (I / O) and non-I / O regions of a substrate. In some embodiments, the method includes forming fin structures and a planar portion on a substrate. The method also includes forming first gate structures on the fin structures and second gate structures on the planar portion. The method also includes etching the fin structures between the first gate structures to form first openings and etching the planar portion between the second gate structures to form second openings. Further, the method includes forming first epitaxial structures in the first openings and second epitaxial structures in the second openings, where top surfaces of the first and second epitaxial structures are substantially co-planar and bottom surfaces of the first and second epitaxial structures are not co-planar.

A method of manufacturing a semiconductor device. According to some embodiments, the method includes forming a substrate of a first conductivity type having a doped layer fabricated therein that can be used as a bottom layer of a barrel-like structure in the semiconductor device. The bottom layer has a second conductivity type opposite the first conductivity type, and a peak doping concentration plane of the bottom layer has a predetermined bottom layer embedding depth from a top surface of an initial substrate layer of the substrate, the predetermined embedding depth being substantially greater than 0.5 [mu] m. The method may further include forming a plurality of sidewalls of the barrel-like structure. The method may further include forming the high voltage transistor of the barrel-like structure.

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least spaced-apart gate oxide trenches and a first depth adjustment trench. This increases the bottom depth of the shallow trench isolation structure used to isolate the source / drain region and the channel region of the high-voltage transistor by utilizing the depth of the first depth adjustment trench, thereby increasing the charge path of the high-voltage transistor, increasing its breakdown voltage, and improving the performance of the high-voltage transistor. Furthermore, the active region convex angle between the gate oxide trench and the shallow trench outside it thickens the edge of the thick gate oxide layer, which helps to reduce leakage current at the apex of the active region of the thick gate oxide layer, solving the problem of the thick gate oxide layer being thin at the apex of the active region. This reduces the hot carrier effect and gate-induced drain leakage current, further improving the voltage withstand capability of the high-voltage transistor in the semiconductor device of this invention.

Field plate structures for gallium nitride (GaN) high voltage transistors are disclosed. In one aspect, a transistor includes a GaN substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separated from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, wherein the field plate extends from a proximal region positioned between the source region and the pedestal toward the drain region, wherein at least a portion of the field plate overlaps at least a portion of the pedestal.

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a gate oxide trench and a first depth adjustment trench. This allows the depth of the first depth adjustment trench to be used to increase the bottom depth of the shallow trench isolation structure in the high-voltage transistor, thereby increasing the charge path of the high-voltage transistor, increasing its breakdown voltage, and reducing the step height between the high-voltage transistor and other components compared to existing technologies. This reduces the load effect and defects in subsequent processes, improving the performance of the high-voltage transistor. Furthermore, after forming the side trench and before forming the thick gate oxide layer, the surface of the active region's exposed corners is oxidized to form a corner oxide layer. This allows for more favorable growth of the oxide layers on each crystal plane of the active region at the gate oxide trench during the growth of the thick gate oxide layer, solving the problem of the thick gate oxide layer being thin at the active region's corners.

The invention provides an output chip and a light-operated relay, the output chip is integrated with a high-voltage HEMT transistor and a clamping circuit, and the high-voltage HEMT transistor and the clamping circuit are isolated through an electrical isolation structure; the grid electrode of the high-voltage HEMT transistor is used for receiving a photovoltaic voltage signal from a photovoltaic element; and the clamping circuit is connected between a grid electrode and a source electrode of the high-voltage HEMT transistor and is configured to perform accelerated charging and discharging on a grid electrode capacitor of the high-voltage HEMT transistor based on the photovoltaic voltage signal. Compared with the prior art, the output chip and the light-operated relay comprising the output chip provided by the invention have the advantages of high integration, nanosecond speed, low resistance consumption, single-chip compatibility of alternating current, direct current and normally open / normally closed, suitability for a wide voltage range of more than 40V, remarkable reduction of packaging and the like.

Multiplexer for controlling access to memory cells of a memory, including: - a first chain that controls access to the source lines of the memory, wherein the first chain comprises two high-voltage transistors and several low-voltage transistors; - a second chain that controls access to the memory's bit lines, the second chain comprising two high-voltage transistors and several low-voltage transistors, - wherein the two high-voltage transistors of the first chain and / or the second chain are arranged such that a first high-voltage transistor is arranged in each chain to apply the high voltage to the memory, and a second high-voltage transistor is arranged in series with the several low-voltage transistors to protect the low-voltage transistors from the high voltage.

A structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor includes a substrate. The substrate includes a high voltage region, a middle voltage region and a low voltage region. A high voltage transistor is disposed within in the high voltage region. The high voltage transistor includes a first gate dielectric layer embedded in the substrate, and a first gate structure disposed on the first gate dielectric layer. A middle voltage transistor is disposed in the middle voltage region. The middle voltage transistor includes a second gate dielectric layer embedded in the substrate. A second gate structure is disposed on the second gate dielectric layer, wherein a thickness of the second gate structure is greater than a thickness of the first gate structure.

Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

The present application belongs to the technical field of power integrated circuit, and particularly relates to a method for establishing and simulating a lateral high-voltage device equivalent circuit model. The circuit model comprises: a field effect transistor; a drain resistance, one end of which is connected to the drain of the field effect transistor and the second end of which is used as the drain of a high-voltage device; a source resistance, one end of which is connected to the source of the field effect transistor and the second end of which is used as the source of a high-voltage transistor; a body diode, which is connected in series with a diode cathode through a parallel network of a cathode resistance and an inductor, the anode of which is connected to the source of the high-voltage transistor, and the other end of the cathode resistance is connected to the drain of the high-voltage device; a first current source, one end of which is connected to the drain of the high-voltage device and the other end of which is connected to the source of the high-voltage device; and a simulation model, which uses a voltage control resistance value relationship to correct the resistance value of an external resistance. Compared with a traditional model, the resistance expression of the present application has a clear physical meaning, effectively improves the simulation accuracy of the lateral high-voltage device model, and has better convergence.

A power radio frequency (RF) switch used in wireless communication is disclosed. A boosted switching control signal, which swings between a boosted supply voltage in which a system supply voltage is boosted and a negative supply voltage in which a polarity of the system supply voltage is inverted, is applied to a gate of a high-voltage transistor. Further, a substrate control signal which is synchronized with the boosted switching control signal, and swings between the negative supply voltage and a reference voltage may be applied to a substrate of the high-voltage transistor thereof.

Vehicle propulsion system comprising a battery for supplying direct current (DC), an inverter with a wide-bandgap transistor for converting the DC to alternating current (AC) in response to a transistor control signal applied to a gate of the wide-bandgap transistor, a high-voltage power switch connected antiparallel to the wide-bandgap transistor to provide a path for current when the wide-bandgap transistor is off, an inverter controller with a power supply for providing DC, a current sensor for detecting a current level of the DC, and a high-voltage transistor for generating the transistor control signal in response to a variation in the current level and DC, and an electric motor configured to produce electromotive torque in response to the AC voltage to propel a vehicle.

A vehicle propulsion system including a battery for supplying a direct current (DC), an inverter including a wide band gap transistor for converting the DC to an alternating current (AC) in response to a transistor control signal applied to a gate of the wide band gap transistor, a high voltage power switch coupled in anti-parallel with the wide band gap transistor to provide a path for the current when the wide band gap transistor is turned off, an inverter controller including a power supply for supplying a DC current, a current sensor for detecting a current level of the DC current, and a high voltage transistor for generating the transistor control signal in response to a variation of the current level and the DC current, and an electric motor configured to generate an electromotive torque in response to the AC voltage to propel a vehicle.

A high-voltage transistor includes an asymmetric gate dielectric layer and / or a gate structure that includes one or more asymmetric work function metal layers. The gate dielectric layer and / or the work function metal layer(s) are asymmetric in that the height of the gate dielectric layer and / or the height of the work function metal layer(s) on opposing sides of the gate structure are different. In particular, the height of the gate dielectric layer and / or the height of the work function metal layer(s) on a side of the gate structure facing the drain region of the high-voltage transistor are lower than the height of the gate dielectric layer and / or the height of the work function metal layer(s) on an opposing side of the gate structure facing the source region of the high-voltage transistor.

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter. .

This invention discloses a method for fabricating a low-voltage transistor, a medium-voltage transistor, and a high-voltage transistor. The method includes providing a substrate, a first active region disposed in a low-voltage region, a second active region disposed in a medium-voltage region, two second source / drain regions buried in the second active region, a third active region disposed in a high-voltage region, and two third source / drain regions disposed in the third active region. Next, a medium-voltage gate dielectric material layer is formed to cover the first active region, the second active region, and the two third source / drain regions. Then, a patterned mask is formed to cover a portion of the medium-voltage gate dielectric material layer in the second active region to expose all the medium-voltage gate dielectric material layers located in the first active region, the medium-voltage gate dielectric material layers located on the two second source / drain regions, and the medium-voltage gate dielectric material layers located on the two third source / drain regions. Finally, using the patterned mask as a mask, the exposed medium-voltage gate dielectric material layers are completely removed.

Memory circuitry comprises strings of NAND memory cells and horizontal high voltage transistors that are operatively electrically coupled with the vertical strings. The horizontal high voltage transistors individually comprise two horizontally-spaced regions having a vertical fin extending horizontally there-between. Two source / drain regions are individually in one of the two horizontally-spaced regions and individually comprise a highest-doped region that is horizontally spaced from the vertical fin and a lightly-doped region that is beneath and laterally aside the highest-doped region between the highest-doped region and the vertical fin (with the lightly-doped region being horizontally spaced from the vertical fin by an intermediate region of one of the two horizontally-spaced regions). A channel region is horizontally between the two source / drain regions and is in the vertical fin and in each intermediate region. A conductive gate is operatively over a top surface and opposing lateral side surfaces of the vertical fin and over a top surface of each intermediate region. Methods are disclosed.

A level shifter circuit including a bias-voltage generation circuit, a charge-discharge balancer circuit, a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, a low-voltage processing circuit, and a high-voltage processing circuit is provided. The bias-voltage generation circuit generates a stable voltage. The charge-discharge balancer circuit generates a first control voltage and a second control voltage based on the stable voltage, a first processed signal, and a second processed signal. The first high-voltage NMOS transistor receives the first control voltage and a third processed signal. The second high-voltage NMOS transistor receives the second control voltage and a fourth processed signal. The low-voltage processing circuit processes an input signal to provide the first, second, third, and fourth processed signals. The high-voltage processing circuit generates an output signal based on the drain voltage of the first high-voltage NMOS transistor and the drain voltage of the second high-voltage NMOS transistor.

A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source / drain doping region and a second source / drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source / drain doping region and a second silicide layer covers and contacts the second source / drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source / drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source / drain doping region.