63results about "Angle modulation details" patented technology

This invention relates to the field of radio frequency (RF) power supplies, specifically to an RF power supply frequency tuning dynamic tracking method and system. The method includes the following steps executed sequentially: S1: Generating a frequency-modulated signal based on an initial carrier frequency and the frequency of a preset modulation signal; S2: Coupled sampling of the RF signal output from the RF power supply after power amplification, filtering the sampled signal, extracting the corresponding signal components, and calculating the corresponding reflection coefficient amplitudes; S3: Comparing the corresponding reflection coefficient amplitudes and selecting the minimum reflection coefficient amplitude; S4: Using the frequency corresponding to the minimum reflection coefficient amplitude as the new carrier frequency, and obtaining a new first sideband frequency and a second sideband frequency based on the new carrier frequency; S5: Repeating steps S1 to S4 based on the updated frequencies. This solution, through iterative updates of the carrier frequency and sideband frequency, possesses the ability to detect and track the reflection coefficient amplitude in real time, and significantly shortens the tuning time.

The invention relates to the field of radio frequency power supplies, in particular to a radio frequency power supply frequency tuning dynamic tracking method and system, and the method comprises the following steps: S1, generating a frequency modulation signal based on the initial carrier frequency and the frequency of a preset modulation signal; s2, carrying out coupling sampling on the radio frequency signal which is output by the radio frequency power supply and is subjected to power amplification, carrying out filtering processing on the sampled signal, extracting corresponding signal components, and respectively calculating corresponding reflection coefficient amplitudes; s3, the corresponding reflection coefficient amplitudes are compared, and the minimum reflection coefficient amplitude is selected; s4, taking the frequency corresponding to the minimum reflection coefficient amplitude as a new carrier frequency, and obtaining a new first sideband frequency and a second sideband frequency based on the new carrier frequency; and S5, repeatedly executing the steps S1 to S4 according to the updated frequency. According to the scheme, through loop iteration updating of the carrier frequency and the sideband frequency, the real-time detection and tracking capability of the reflection coefficient amplitude is achieved, and the tuning time is remarkably shortened.

Disclosed herein are methods of using a type I phase locked loop, PLL, comprising an oscillator and a feedback path to a phase detector. The method comprises: locking a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal; locking a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal; and a one of: adjusting the second relative phase to equal the first relative phase, and adjusting the oscillator frequency, by applying a correction to the PLL

A single-sideband phase-sensitive detection method is provided. A time-dependent target signal of a to-be-detected system is repeatedly triggered. A plurality of modulation signal sets varying in modulation phase corresponding to a plurality of triggering moments are generated. The time-dependent target signal is modulated based on the plurality of modulation signal sets corresponding to each of the triggering moments to obtain a plurality of detection signal sets varying in time and modulation phase. The plurality of detection signal sets are processed to obtain a plurality of equivalent single-sideband modulation signal sets. The plurality of equivalent single-sideband modulation signal sets are demodulated to obtain a plurality of processed signals. A single-sideband phase-sensitive detection system, device, storage medium and computer program product are also provided.

The utility model provides a signal modulation and demodulation system of a digital isolator. The digital isolator and a pulse signal output end and a signal input end of a modulation module are respectively connected with a primary modulation node through a first switch; the first-stage modulation node is connected with the input end of the second-stage modulation node through the phase inverter; the RF signal output end is also connected with the input end of the secondary modulation node; the first switch is controlled by a level signal input by the signal input end to be switched on or switched off so as to control whether the pulse signal and the level signal can reach a primary modulation node for primary modulation or not, and a primary modulation signal is obtained; the secondary modulation node is controlled by the signal flowing out of the primary modulation node to be switched on or switched off so as to control whether the RF signal output by the RF signal output end and the signal flowing out of the primary modulation node can be subjected to secondary modulation or not, and a composite modulation signal is obtained. According to the utility model, two-stage precise modulation control is realized through the arrangement of the two-stage switch, so that the signal modulation precision of the digital isolator is remarkably improved.

This invention belongs to the field of mixed-signal circuits and relates to a modulator structure applied in a multi-charge pump phase-locked loop (PLL), specifically providing a method for implementing a modulator with fractional spurious emission suppression due to mismatch. In multi-charge pump PLLs, mismatches between different shunt charge pumps, such as current source mismatch and layout mismatch, can lead to integer boundary spurious emission. To alleviate the problem of integer boundary spurious emission degradation caused by mismatch in multi-charge pump PLLs, this invention proposes a method for implementing a modulator with fractional spurious emission suppression due to mismatch. This is achieved by making the net injected charge of long-range mismatch zero and filtering out the low-frequency components of the mismatch injected charge, thereby suppressing fractional spurious emission. Simulation results show that this invention can significantly suppress fractional spurious emission caused by mismatch.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

This application provides a signal compensation method and circuit, a digital power amplifier, and a storage medium, relating to the field of signal processing. The signal compensation method includes: determining a compensation value for a distorted signal based on a preset memory group; the memory group storing a compensation table, the compensation table including the relationship between the compensation value and the distorted signal; and compensating the distorted signal using the compensation value; wherein the memory group includes multiple memories, each memory including different sub-compensation tables; the sub-compensation tables are parts of the compensation table, and all the sub-compensation tables constitute the compensation table. This signal compensation method can reduce the memory footprint in a digital compensation pre-distortion circuit.

The invention relates to a digital transmitter (10) for providing a high-frequency analog signal, the transmitter comprising: conversion means (3) for receiving a digitally modulated baseband signal (12) and providing a discrete spectrum of the digitally modulated baseband signal (12) in polar coordinates or in oblique coordinates; and a synthesis means (90) for generating the high-frequency analog signal on the basis of the discrete spectrum provided in polar coordinates or in oblique coordinates, where the synthesis means (90) is a means for performing a continuous inverse Fourier transform. The invention also relates to a method for providing a high-frequency analog signal, comprising: receiving a digitally modulated baseband signal; and providing a discrete spectrum of the digitally modulated baseband signal in polar coordinates or in oblique coordinates; and generating the high-frequency analog signal based on the discrete spectrum provided in polar coordinates or in oblique coordinates by performing a continuous inverse Fourier transform.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

Interfaces between clock domains of an integrated circuit (IC) depend on synchronization of phase-locked loops (PLLs) that generate clocks in the different domains and on how each PLL responds to jitter in a shared reference clock. The well-controlled same bandwidth (and loop dynamic) for those PLLs renders the same and, therefore, ignorable reference jitter contribution. As a key component that determines a digital PLL bandwidth, digitally controlled oscillator (DCO) may have its gain vary with process, temperature, and supply IR drop from chip to chip or even module to module. A calibration circuit provides a gain correction factor to achieve a nominal gain in DCO as well as a desired / target PLL loop bandwidth. In some examples, the calibration circuit in each PLL determines a gain correction factor that causes the PLLs to have a common jitter response and stores the gain correction factors in the calibration circuits.

A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises a plurality of unit variable reactance structures comprising respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.

An automatic level control (ALC) circuit includes an input configured to receive a radio frequency (RF) input signal, a level control circuit coupled to the input and configured to control a level of the RF input signal in response to a feedback signal, and an output coupled to the level control circuit and configured to output a level-controlled RF output signal. The ALC circuit further includes a feedback path coupled to the output and configured to sample the level-controlled RF output signal to determine an error detected in the level-controlled RF output signal, and to generate the feedback signal in accordance with the error. The ALC circuit still further includes a feedforward path coupled to the input and configured to emulate a frequency response in the feedback path and to adjust the error determined in the feedback path according to the emulated frequency response.

The invention provides a frequency modulation method for a low-noise broadband phase-locked loop, and relates to the technical field of phase-locked loop frequency modulation. The method includes: acquiring initial parameters of a component; identifying and quantizing a noise source to obtain noise characteristics; calculating a frequency error and a phase error, and determining a noise level; introducing a control strategy based on fuzzy logic, and defining an input variable to obtain a control strategy; according to the control strategy, adjusting component parameters, and modulating phase and frequency; and evaluating the optimization effect. According to the invention, through a clear target and data driven decision process, the trial and error cost is reduced, the automatic control strategy is optimized, and the system can still operate stably in a noise environment. The phase-locked loop system is higher in robustness and adaptability, not only improves the accuracy of frequency and phase, but also improves the operation efficiency of the whole system under a dynamic condition, and provides a reliable signal processing scheme for related applications.

This modulator includes: a first energy distribution unit whereby a signal wave to be transmitted is distributed at a first ratio corresponding to a desired level for each side wave component; an even term side wave generation unit whereby one or more signals that have an even-numbered side wave component are generated on the basis of a carrier signal and the signal wave distributed at the first ratio by the first energy distribution unit; and an odd term side wave generation unit whereby one or more signals that have an odd-numbered side wave component are generated on the basis of the carrier signal and the signal wave distributed at the first ratio by the first energy distribution unit.　

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to generate a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to adjust a second duty cycle of a first clock output signal responsive to a set of control signals or a phase difference between a first phase clock signal and a second phase clock signal of the first set of phase clock signals. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

The present invention discloses a modulation and demodulation circuit for anti-common mode interference. The modulation and demodulation circuit includes a modulation circuit and a demodulation circuit. The demodulation circuit includes a high-pass filter and a comparator. The modulation circuit is electrically connected to the high-pass filter, and the high-pass filter is electrically connected to the comparator. The modulation circuit is used to convert an input signal into a modulated signal and transmit the modulated signal to the high-pass filter. The high-pass filter is used to filter out the common mode interference signal in the modulated signal. The comparator is used to convert the filtered modulated signal into a digital signal corresponding to the input signal. By reasonably setting the carrier signal frequency, the cut-off frequencies of the high-pass filter and the low-pass filter in the modulation and demodulation circuit, the present invention can effectively suppress the common mode interference signal while completing the signal modulation and demodulation function, thereby reducing the bit error rate of signal transmission.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a multiplexed selection signal, the first clock output signal having a second duty cycle; and adjust the second duty cycle responsive to at least a set of control signals or a phase difference between a first and second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

This modulator comprises: an even-term side wave generation unit that generates one or more signals having an even-numbered side wave component on the basis of a carrier signal and a signal wave to be transmitted; an odd-term side wave generation unit that generates one or more signals having an odd-numbered side wave component on the basis of the carrier signal and the signal wave; and a multiplexing unit that multiplexes the carrier signal, the one or more signals having an even-numbered side wave component, and the one or more signals having an odd-numbered side wave component.　

The present application discloses a signal processing circuit based on transformer isolation, comprising: the signal modulation module is used to modulate the input signal to obtain a modulated signal; the isolation transformer is used to transmit the modulated signal to the signal demodulation module; the signal demodulation module is used to demodulate the modulated signal to obtain a restored input signal. The modulation and demodulation principle of the present invention is simple and easy to implement, and the signal transmission frequency is not limited by the original signal.

The invention relates to an FMCW-based fill-level measuring device (1) which can operate in two frequency bands which are clearly delimited from one another. For this purpose, the fill-level measuring device (1) comprises two high-frequency units (11, 12), each having a frequency-controllable oscillator (111, 112), in order, in accordance with the FMCW principle, to generate radar signals (SHF1, 2) in the frequency bands or to receive same after reflection at the filling material surface. An antenna arrangement (13) is used to transmit and receive the radar signals (SHF1, 2) towards the filling material (L) and to receive same after reflection at the filling material surface, wherein a control / evaluation unit (14) can determine the fill level (L) on the basis of the received signal (RHF1, 2) of the first frequency band or of the second frequency band. According to the invention, the fill-level measuring device (1) is characterised by a common clock unit (15). This is used to form a phase-locked loop with both the first oscillator (111) and the second oscillator (121) in order to generate, in accordance with the FMCW principle, the corresponding radar signals (SHF1, 2, RHF1, 2) of the two frequency bands. As a result, it is unnecessary to provide a complete phase-locked loop for each of the two frequency bands. The number of required components is thus reduced.

Provided is a modulator comprising: a first energy distributing unit that distributes, at a predetermined ratio corresponding to a first level of each sideband component, a signal wave to be transmitted, which has been subjected to integration or an operation approximately equivalent to integration; an even-term sideband generating unit that generates one or more signals having an even-numbered sideband component, on the basis of a carrier signal and the signal wave distributed at the first ratio by the first energy distributing unit; and an odd-term sideband generating unit that generates one or more signals having an odd-numbered sideband component, on the basis of the carrier signal and the signal wave distributed at the first ratio by the first energy distributing unit.　

The invention discloses a sensor interface circuit based on frequency modulation and a sensor signal transmission method. A sensor analog signal generation circuit is used for outputting a first analog signal to a first conversion module; the first conversion module is used for converting the first analog signal into a digital signal and transmitting the digital signal to the first control module; the first control module is used for converting the digital signal into a pulse square wave signal and transmitting the pulse square wave signal to the frequency modulation circuit; the frequency modulation circuit is used for converting the pulse square wave signal into a frequency waveform signal and transmitting the frequency waveform signal to the frequency demodulation circuit; the frequency demodulation circuit is used for demodulating the frequency waveform signal into a pulse square wave signal and transmitting the pulse square wave signal to the second control module; and the second control module analyzes and processes the pulse square wave signal to generate sensor signal value data. The sensor interface circuit provided by the invention not only can transmit analog signals, but also can be compatible with a digital serial signal transmission function.

Disclosed is technology related to a signal synthesis apparatus that corrects an offset between a closed loop and an open loop to output a frequency-modulated signal. The signal synthesis apparatus includes a VCO configured to output a frequency signal in response to an input voltage, an energy storage unit configured to output a voltage using stored energy, a VCO input selector configured to connect the VCO to input of the energy storage unit in the case of a closed loop mode and connect the VCO to output of the energy storage unit in the case of an open loop mode, and a digital controller configured to control an operation mode of the VCO input selector and transmit an offset control signal for adjusting an offset of a voltage output from the energy storage unit to the energy storage unit.

A reading device for capacitive sensing element comprises a differential capacitive sensing element, a modulator, a charge-voltage conversion circuit, a phase adjustment circuit, a demodulator and a low-pass filter. The modulator outputs a modulation signal to the common node of the capacitive sensing element and modulates the output signal of the capacitive sensing element. The two input terminals of the charge-to-voltage conversion circuit are connected to two non-common nodes of the capacitive sensing element. The charge-to-voltage converter read the output charge of the capacitive sensing element and convert it into a voltage signal. The modulator generates a demodulation signal through the phase adjustment circuit. The demodulator receives the demodulation signal from the phase adjustment circuit and demodulates the output of the charge-to-voltage conversion circuit. The low-pass filter is connected to the output of the demodulator for filtering the demodulated voltage signal to output the read signal.

The invention discloses a clock modulation circuit and a clock modulation method for generating a spread spectrum clock signal. The clock modulation circuit comprises a current generator used for respectively generating a trimming current with a preset value and a modulation current changing along with time, and a current control type oscillator used for respectively generating a standard clock signal and a spread spectrum clock signal according to the trimming current and the modulation current, the current adjusting precision of the modulation current is higher than that of the trimming current. According to the clock modulation circuit, high-precision frequency jump of spread spectrum clock signals can be realized by using a high-precision jitter current channel, and overshoot or undershoot of the spread spectrum clock signals during frequency jump can be suppressed.