1037 results about "Loop filter" patented technology

A method and an apparatus for video coding using a super-resolution in-loop filter utilize an in-loop filter based on upsampling or super-resolution techniques in processing a video signal through downsampling to the compression and upsampling to the reconstruction thereof. The video decoding method includes obtaining the reconstructed frame, obtaining a scale value representing a resolution difference between the reconstructed frame and the original frame, generating, based on the scale value, an upsampled reconstructed frame by inputting the reconstructed frame into a resampling in-loop filter that is deep learning-based, and storing an output frame as a reference frame once generated by the plurality of filters and the resampling in-loop filter in a decoded picture buffer (DPB).

The invention relates to a digital lock-in amplifier based on a frequency adaptive technology and a weak signal acquisition system and method, and the system comprises a front-end signal processing module which is used for obtaining a weak signal to be detected; the frequency self-adaptive tracking module is used for performing fast Fourier transform on the frequency of the weak signal to be measured to obtain the position of the maximum spectral line so as to synthesize a frequency control word, further generate a local reference signal and simultaneously adjust the coefficients of a low-pass filter and a loop filter and the series adjustment mode of a carrier synchronization ring; the multi-rate narrow-band low-pass filter module is used for multiplying the digital signal by a local reference signal and then carrying out filtering and down-sampling on a high-frequency signal to obtain a plurality of mutually orthogonal difference frequency components; the vector operation module is used for carrying out vector operation on the plurality of mutually orthogonal difference frequency components to obtain the phase and the amplitude in the weak signal to be measured; and the man-machine interaction module is used for displaying and storing the phase and the amplitude in the weak signal to be detected.

The present disclosure relates to signaling in a bitstream coded block data and in-loop filtering parameters of a video sequence comprising video pictures, each video picture being split into multiple coding tree units, denoted CTU, each CTU comprising CTU blocks, CTU coded blocks data being obtained for each CTU by encoding blocks of said CTU, reconstructed CTU blocks associated with a CTU being obtained by decoding CTU coded blocks data associated with said CTU, reconstructed CTU blocks associated with a CTU being filtered using in-loop filtering parameters associated with said CTU, denoted CTU in-loop filtering parameters, wherein CTU coded blocks data associated with a CTU and CTU in-loop filtering parameters associated with said CTU are signaled in distinct Network Abstract Layer units, called NAL units.

A method of processing video data. The method includes selecting an in-loop filter from a plurality of neural network (NN) filter model candidates, wherein the plurality of NN filter model candidates are based on a reconstructed quality level of a video unit, and performing a conversion between a video media file comprising the video unit and a bitstream based on the in-loop filter selected. A corresponding video coding apparatus and non-transitory computer readable medium are also disclosed.

Disclosed are systems and methods for adaptive noise cancellation (ANC) at a virtual microphone located at the eardrum of a wearer of an earphone. The techniques estimate the level of leakiness of ambient noise in the earphone from the magnitude of the gain of the transfer function of the feed forward loop filter of the ANC. Based on the estimated leakiness, the techniques estimate the transfer function of the feed forward loop filter to compensate for the difference in the effect of noise cancellation at the virtual microphone and error microphone. A bias term that represents the difference in the frequency response of the attenuated noise at the virtual and error microphone may be added to the adaptive feed forward algorithm. The ANC operation may apply the bias term to the adaptive feed forward loop filter to reduce the ambient noise at the eardrum rather than at the error microphone.

The invention discloses a tracking processing method for a baseband signal of a receiver, which comprises the following steps of: firstly, performing frequency correction through a frequency-locked loop, and performing phase correction through a phase-locked loop to realize accurate synchronization of carrier frequency and phase; then bit synchronization processing and incoherent integration are carried out, and the output signal-to-noise ratio of the loop and the measurement precision of the code phase are improved; and finally, the local pseudo-random code generator generates a local pseudo-random code, then the local pseudo-random code generator outputs three paths of pseudo-random codes which are mutually delayed by half a chip, namely a lead code, a real-time code and a lagging code, correlation values of the three paths of pseudo-random codes are obtained, a code phase error is obtained by calculating the correlation value difference of the lead code and the lagging code, and the local pseudo-random code is obtained. And after the code phase error is processed by a loop filter, an adjustment amount of a digital control oscillator is generated, so that the phase of the local pseudo-random code is adjusted. According to the invention, continuous adjustment of the digital control oscillator of the local carrier and the pseudo-random code is realized, so that correct navigation data information is demodulated for positioning calculation.

An electronic apparatus performs a method of decoding video data, including: reconstructing, from a video bitstream, a picture frame that includes a luma component, a first and a second chroma components, and applying a trained neural network based in-loop filter to the reconstructed picture frame by: converting a first resolution of the samples of the at least one of the first and the second chroma components to a second resolution of the samples of the luma component when the first resolution is different from the second resolution; concatenating samples of at least one of the first and the second chroma components with the luma component; processing the concatenated samples using a convolutional neural network; and reconverting the samples of the at least one of the first and the second chroma components processed by the convolutional neural network from the second resolution back to the first resolution.

The invention discloses a composite loop tracking method of an anti-interference navigation signal receiver. The method comprises the following steps: copying a pseudo code and a carrier corresponding to a satellite signal based on a roughly captured signal; performing coherent operation to obtain a coherent integral value; performing FLL frequency discrimination, PLL phase discrimination and FFT frequency discrimination on the coherent integral value, and performing weighting processing to obtain a frequency error; carrying out carrier loop filtering on the frequency error to output a carrier loop tracking result; performing incoherent accumulation to obtain an incoherent integration result, and performing DLL phase discrimination to obtain an epoch code loop phase difference; performing code loop filtering on the epoch code loop phase difference to output a code loop tracking result; calculating a first frequency control word corresponding to the code loop according to the wave loop tracking result; and controlling code loop updating based on the first frequency control word and the code loop tracking result. According to the invention, stable tracking of navigation signals in different dynamic and different interference scenes can be realized.

A loop filtering method, a video encoding method, a video decoding method, an electronic device, and a medium are provided. The loop filtering method includes: acquiring a first reconstructed video unit processed by a loop filter; performing pixel classification on the first reconstructed video unit; determining a scale factor corresponding to each class; and performing scale adjustment on the first reconstructed video unit according to the scale factor, so as to obtain a second reconstructed video unit.

Disclosed are a loop filtering implementation method and apparatus, and a computer storage medium. The method comprises: obtaining an picture to be filtered, wherein the picture to be filtered is generated from an original picture during the video encoding of a video to be encoded, the video to be encoded comprises an original picture frame, and the original picture frame comprises the original picture; based on the picture to be filtered, separately obtaining at least two colour components of the picture to be filtered; determining the fusion information of the picture to be filtered, wherein the fusion information is obtained by fusing the at least two colour components; and based on the fusion information, performing loop filtering processing on the picture to be filtered to obtain at least one colour component subsequent to filtering the picture to be filtered.

The invention discloses a vehicle-mounted bidirectional power converter which comprises a pre-stage voltage stabilization module, a pre-stage driving circuit, a post-stage driving circuit, a post-stage filtering module and an electric vehicle battery module, the pre-stage voltage stabilization module is used for balancing circuit voltage and supporting reactive power, the pre-stage driving circuit is of a single-phase full-bridge AD-DC topological structure, and the post-stage filtering module is of a single-phase full-bridge AD-DC topological structure. The front-stage driving circuit is of a half-bridge type bidirectional DC-DC topological structure, the rear-stage driving circuit is of a half-bridge type bidirectional DC-DC topological structure, the front-stage driving circuit and the rear-stage driving circuit are connected together through a direct-current voltage-stabilizing bus, the size is small, the weight is light, a front stage and a rear stage do not interfere with each other, control is easy, the rear-stage filtering module is used for restraining direct-current side second harmonics, the harmonic quantity is prevented from influencing the stability of output direct-current voltage, and the output direct-current voltage is stable. According to the converter, a corresponding control method is designed, non-inductive decoupling control and a single-phase phase-locked loop of an improved loop filter are adopted, the phase of a power grid is accurately and efficiently obtained, and the converter works stably.

The invention discloses an FPGA (Field Programmable Gate Array) implementation method of a DVB (Digital Video Broadcasting) high-speed demodulator. A digital signal enters a parallel DDC (Direct Digital Control) module and is re-adapted to multiple symbol rates; the parallel AGC module adjusts the power of the digital signal to a fixed power value; the method comprises the following steps: passing through Oamp; m algorithm: completing symbol synchronization; related peaks are extracted, and frame synchronization is completed; correcting the frequency to enable the frequency to reach participation frequency deviation; performing frequency compensation on the digital signal after loop filtering; after error information is calculated and filtered, the digital signal is compensated; and restoring the original information of the digital signal. According to the invention, by adopting the parallel processing module, the real-time performance and the parallelism degree of digital signal processing can be greatly improved, and the performance of the whole demodulator is enhanced. Each module is designed to be adaptive to the change of a digital signal, for example, the AGC module can dynamically adjust the power of the digital signal to ensure that the output digital signal is always kept at a fixed power level so as to adapt to different receiving conditions.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

The invention discloses a frequency synthesizer, and relates to the technical field of communication hardware. The frequency synthesizer comprises a six-layer substrate and a plurality of elements, layout and wiring are reasonably performed in the six-layer substrate, the elements are placed in a limited space, then a coplanar waveguide transmission line model is adopted for a loop filter part, and shielding holes are selected to be added to the position away from the metal edge to reduce return loss and insertion loss. According to the frequency synthesizer, the return loss reaches-30dB or below, the insertion loss is lower than 0.05 dB, a bonding pad and a through hole are adopted for connection aiming at an output high-frequency signal line, a metal column type quasi-coaxial structure and a shielding hole are added to optimize the return loss and the insertion loss, the frequency synthesizer is miniaturized and high in performance, and the frequency synthesizer is suitable for high-integration and miniaturized application scenes.

Embodiments of the invention provide a high density liquid cooling system including a rack, primary loop piping including a primary inlet, a primary outlet, a primary loop filter, and a primary bypass valve, and secondary loop piping including a secondary inlet, a secondary outlet, a first pump, a first filter downstream of the first pump, and a secondary bypass valve. The system includes a heat exchanger having a first side and a second side. When the primary bypass valve is open, at least a portion of the fluid in the primary loop piping flows through the primary inlet and the primary outlet without traversing the heat exchanger, and when the secondary bypass valve is open, at least a portion of the fluid in the secondary loop piping flows through the secondary inlet and the secondary outlet without traversing the heat exchanger.

The invention provides a voltage-controlled oscillator, a phase-locked loop and a temperature compensation method for the frequency of the voltage-controlled oscillator, and the voltage-controlled oscillator comprises an adjustable capacitor and a temperature compensation circuit. The first end of the adjustable capacitor is connected with control voltage, the second end of the adjustable capacitor is connected with the temperature compensation circuit, and the temperature compensation circuit provides temperature compensation voltage changing along with temperature for the adjustable capacitor. According to the technical scheme, the temperature compensation circuit is used for providing the temperature compensation voltage for the voltage-controlled oscillator of the phase-locked loop, so that in and Ip of a charge pump Cp of the phase-locked loop can still be kept approximately equal when the temperature is changed and the control voltage provided by the loop filter of the phase-locked loop is kept unchanged, and the control voltage of the phase-locked loop is kept constant. Compared with a voltage-controlled oscillator in the related technology, the circuit structure in the application can reduce periodic jitter introduced in the PLL by temperature change.

Methods and devices for decoding video data are described. An example method includes in-loop filtering a current block of the video data using a neural network-based in-loop filter to generate an in-loop filtered current block, wherein the neural network-based in-loop filter is trained using an architecture comprising a U-Net architecture comprising one or more residual blocks and one or more transform blocks; and outputting the in-loop filtered current block.

The invention relates to the technical field of wind generating set control, and discloses a three-order semi-tangent type wind generating set position and rotating speed estimation method and system, and the method comprises the steps: converting three-phase power data into rotating two-phase counter electromotive force under rotating coordinates through two times of coordinate transformation and a preset counter electromotive force observer; and then error data of the wind generating set is calculated based on a semi-tangent algorithm, the error data is combined with set operation data to serve as the input of an improved third-order loop filter, the precision of estimation information is improved, more accurate target rotating speed data is obtained, the accurate target rotating speed data serves as the input of a position estimator, and the accuracy of the position estimator is improved. Therefore, more accurate target position data can be obtained; the technical problem of how to accurately estimate the position and the rotating speed of the wind generating set is solved.

The invention provides a continuous time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation. The continuous time Sigma-Delta modulator comprises a loop filter, a quantizer and a digital-to-analog converter, the loop filter is used for amplifying a signal in an effective signal bandwidth and attenuating an out-of-band signal at the same time, and the loop filter comprises a first-stage negative resistance compensation integrator and a second-stage negative resistance compensation integrator which are connected in sequence, the first-stage negative resistance compensation integrator comprises a first negative resistance unit containing a negative resistance of a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, and a single operational amplifier resonator structure is formed to generate a second-order response; the integrator of the second-stage negative resistance compensation comprises a second negative resistance unit and a second integrator unit comprising an operational amplifier; and the quantizer is connected with the loop filter, adopts a successive approximation analog-to-digital converter, and is used for converting the analog voltage signal into a digital signal and outputting the digital signal. And the digital-to-analog converter is used for converting the digital signal into an analog signal and feeding back the analog signal to the loop filter.

The invention discloses a pig body size measurement method based on double-view point cloud registration, and the method comprises the following steps: collecting point cloud data of two sides of a pig; simplifying the point cloud data by adopting an equal-interval thinning algorithm, and removing the abnormal value point cloud data by utilizing an improved LoOP filtering algorithm; obtaining complete pig point cloud data; the contour features of the pigs are extracted in combination with extraction, and non-contact measurement of the multi-body-size parameters of the pigs is achieved. The method has the advantages that the average relative errors of the measured body length, the measured body height, the measured hip height, the measured body width, the measured abdomen width, the measured hip width, the measured chest circumference and the measured abdomen circumference are 1.28%, 0.88%, 1.97%, 2.71%, 2.83%, 3.71%, 2.03% and 2.17% respectively, the average relative error value is 2.20%, and the average absolute error value is 1.04 cm; and 2, measurement of multiple body size parameters of the live pig can be realized, the precision is high, the body size measurement requirement during breeding of the live pig can be well met, and a new way is provided for non-contact measurement of the body size of the live pig.

Methods and devices for decoding video data are described. An example method includes in-loop filtering a current block of the video data using a neural network-based in-loop filter to generate an in-loop filtered current block, wherein the neural network-based in-loop filter is trained using an architecture comprising a U-Net architecture comprising one or more residual blocks and one or more transform blocks; and outputting the in-loop filtered current block.

The invention provides a reference-clock-free clock data recovery device and a clock data recovery method thereof, and relates to the technical field of electronics. The reference-clock-free clock data recovery device comprises a linear phase discriminator used for carrying out phase discrimination processing on received four-level pulse amplitude modulation data and outputting a phase discrimination signal voltage; the frequency discriminator is used for carrying out frequency discrimination processing on the received phase discrimination voltage signal and outputting a frequency discrimination signal voltage; the first voltage-current converter is used for outputting pulse signal current; the loop filter is used for converting the pulse signal current into control voltage; the inductance-capacitance oscillator is used for converting the control voltage into an orthogonal clock signal; the self-biased multiphase clock generator is used for outputting a multiphase clock signal according to the orthogonal clock signal; and the starting circuit is used for discharging the control voltage to zero during power-on starting, so that the orthogonal clock signal is at the initial frequency, and traversal search of the control voltage is realized.

Amplifying a signal includes outputting an output signal from a Class D amplifier configured to operate as a current driver to a load, such as a loudspeaker, the output of the Class D amplifier controlled by a feedback loop, and, in the feedback loop: performing analog filtering using an active analog filter on an error signal that is based on the output of the Class D amplifier and a reference signal, digitizing a filtered output of the analog filter to produce a sequence of digital values, performing digital filtering on the sequence of digital values to produce a sequence of filtered digital values, and generating a pulse signal to control the output of the Class D amplifier based on the sequence of filtered digital values. The digital filter reduces a destabilizing effect of the loudspeaker's inductance. Associated circuits, systems, modules and electronic devices are disclosed.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention belongs to the technical field of optical communication, and particularly relates to a high-stability photo-generated millimeter wave system based on a phase-locked loop, which comprises a first laser, a second laser, an acousto-optic frequency shifter, a dense wavelength division multiplexer, an inner loop feedback control loop and an outer loop signal output branch, the inner loop feedback control loop comprises a phase modulator, an optical filter, a photoelectric detector, a frequency division arithmetic unit, a phase frequency detector, a loop filter, a voltage-controlled oscillator and a first power amplifier which are sequentially connected in series, and the output of the first power amplifier is connected with an acousto-optic frequency shifter; the inner loop feedback control loop further comprises a cesium atomic clock, a microwave source and a second power amplifier; wherein the cesium atomic clock is connected with the microwave source and the phase frequency detector, and the output of the microwave source is connected with the phase modulator after passing through the second power amplifier.

The invention provides a three-phase grid-connected phase-locked loop two-stage filter and a filtering method thereof, and belongs to the related technical field of effective detection and extraction of power grid voltage phase signals. The invention provides a three-phase grid-connected phase-locked loop two-stage filter and a filtering method thereof in order to solve the problem that a traditional phase-locked loop filter cannot completely filter harmonic waves and direct-current offset voltage due to insufficient filtering capacity under a non-ideal power grid condition. In order to enhance the anti-interference capability of a phase-locked loop filter, the invention designs a mixed-order generalized integrator and constructs a double-mixed-order generalized integrator. Meanwhile, the double-mixed-order generalized integrator serves as a first-stage filtering unit, and a Parker transformation unit and a comb filter are introduced to serve as a second-stage filtering unit, so that a double-stage filter is formed through combination. By applying the filtering method in the phase-locked loop, it is proved that the method can effectively filter interference in a power grid. The method is mainly used for the grid-connected phase-locked loop filtering process under the non-ideal power grid condition.

An audio amplifier includes a loop filter, at least one high pass filter (HPF) circuit, a pulse width modulation (PWM) generator, and a power stage. The loop filter is arranged to receive an audio signal and a feedback signal, and includes a first amplifier and a second amplifier, wherein the first amplifier has a first output node, and is arranged to process the audio signal and the feedback signal; the second amplifier has a first input node, and is arranged to receive a first amplifier input and a second amplifier input; and the first amplifier input is obtained from a signal path coupled between the first output node and the first input node. The at least one HPF circuit is coupled between the first amplifier and the second amplifier, and is arranged generate and output the second amplifier input according to an amplifier output of the first amplifier.

A method implemented by a video coding apparatus. The method includes determining, in real time, padding dimensions for padding samples to be applied to a video unit of a video for in-loop filtering, wherein d1, d2, d3, and d4 represent the padding dimensions corresponding to top, bottom, left, and right boundaries of the video unit, respectively; and performing a conversion between a video unit and a bitstream of the video based on the padding dimensions that were determined. A corresponding video coding apparatus and non-transitory computer-readable recording medium are also disclosed.