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2898 results about "Loop filter" patented technology

Delta-sigma A/D converter

A delta-sigma modulator comprising a first quantizer providing a first digital signal d0(k) representing the input signal g(t); a loop filter with input signal paths; a loop quantizer providing a corrective digital signal d1(k) representing the loop filter's output signal y(t); an array of feedback DACs D/A converting the sum d(k)=df(k)=d0(k)+d1(k) of the first and the corrective digital signals and injecting feedback signals into the loop filter.The loop filter's input node is applied the difference of the input signal g(t) and the global analog feedback signal a3(t). The global feedback signal a3(t) is delayed several clock cycles with respect to the digital output signal d(k). The delay is used to carry out mismatch-shaping and deglitching algorithms in the feedback DACs. The feedback DACs' different delays and gain coefficients are designed such that the modulator is stable. The filter's input signal paths and the compensating DAC are designed such that the gain from the input signal g(t) to the loop quantizer is small, ideally zero. Thus, the loop quantizer's resolving range can be a fraction of the first quantizer's resolving range, whereby the output signal's d(k) resolution can be much higher than the individual resolutions of d0(k) and d1(k).The delta-sigma modulator is well suited for the implementation of high-resolution wide-bandwidth A/D converters. Important applications include digital communication systems.
Owner:ANALOG DEVICES BV

Method and apparatus to achieve a process, temperature and divider modulus independent PLL loop bandwidth and damping factor using open-loop calibration techniques

Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.
Owner:SILICON LAB INC

Low energy consumption RF telemetry control for an implantable medical device

In an implantable medical device, a frequency synthesizer employed in the RF transceiver of the IMD operating system functions in a PLL LOCK mode wherein the VCO frequency is governed by the PLL and an energy saving HOLD mode wherein the PLL is not operational and the VCO generated carrier frequency can drift over time. The PLL circuit is powered up and coupled with a control voltage input and the output of the VCO to develop a frequency control voltage stored by a capacitive loop filter during initial LOCK portions of both uplink and downlink telemetry transmission time periods. A frequency modulation (FM) input of the VCO receives data bit modulation voltages that modulates the carrier frequency during uplink transmission of patient data. During the HOLD portion of a downlink telemetry transmission, an AFC algorithm is enabled and derives a frequency correction value from the difference in frequency of the constant received carrier frequency and the drifting VCO generated carrier frequency, and the frequency correction value is applied to the VCO FM input to compensate for loop filter capacitor discharge of the control voltage causing the drift. The AFC algorithm derived frequency correction value is stored in memory and is also applied during the HOLD portion of an uplink telemetry transmission to the VCO FM input to compensate for loop filter capacitor discharge of the control voltage causing the drift. In addition, a recharge current is applied to the capacitive loop filter.
Owner:MEDTRONIC INC
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