508 results about "Loop filter" patented technology

Embodiments of the invention provide a high density liquid cooling system including a rack, primary loop piping including a primary inlet, a primary outlet, a primary loop filter, and a primary bypass valve, and secondary loop piping including a secondary inlet, a secondary outlet, a first pump, a first filter downstream of the first pump, and a secondary bypass valve. The system includes a heat exchanger having a first side and a second side. When the primary bypass valve is open, at least a portion of the fluid in the primary loop piping flows through the primary inlet and the primary outlet without traversing the heat exchanger, and when the secondary bypass valve is open, at least a portion of the fluid in the secondary loop piping flows through the secondary inlet and the secondary outlet without traversing the heat exchanger.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

A video encoder is configured to determine to filter video data using a neural network (NN)-based filter and a fixed block size inference, and encode a flag that indicates the fixed block size inference is used for the NN-based filter. Reciprocally, a video decoder is configured to decode a flag that indicates whether a fixed block size inference is used for an NN-based filter, and filter video data using the NN-based filter based on the flag. The flag may be signaled at a sequence parameter set (SPS) level.

An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and / or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.

A method of processing video data includes receiving, with a neural network in-loop filter (NN-ILF), a current block of video data of a current picture; and filtering, with the NN-ILF, the current block of video data to generate a filtered current block of video data, wherein filtering the current block of video data comprises: generating, with an attention block of the NN-ILF, an attention map indicative of a correlation between elements of features of the current block of video data; modifying, with the attention block of the NN-ILF, the attention map based on a size of blocks used for training the NN-ILF to generate a modified attention map; generating, with the attention block of NN-ILF, feature data based on the modified attention map; and filtering, with the NN-ILF, the current block of video data based on the feature data to generate the filtered current block of video data.

Various implementations described herein include methods and systems for coding video. In one aspect, a video bitstream includes a current image frame and a first syntax element for a CCSO mode. When the CCSO mode is enabled, a plurality of candidate luma sets are identified in a filter range that includes a first luma sample and neighboring luma samples. Each candidate luma set includes respective luma samples having positions symmetric with respect to a position of the first luma sample, and each luma sample located in the filter range is used in at least one of the candidate luma sets. A set of target luma samples is selected from the candidate luma sets. A loop filter is applied to combine the set of target luma samples and the first luma sample to generate the first sample offset of a first color sample collocated with the first luma sample.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

The invention relates to a high-dynamic time division navigation signal tracking method assisted by adaptive Kalman filtering, and belongs to the technical field of satellite navigation. Aiming at the problems of tracking delay, precision reduction and easy lock loss caused by discontinuous loop update in a high dynamic environment in the existing time division navigation signal tracking method, the method comprises the steps of carrier and code stripping, time-slot error identification, adaptive Kalman filter AKF preprocessing and loop filtering and tracking of three-order FLL-assisted four-order PLL. And full-time-slot continuous tracking is realized. The core of the method is that process noise covariance is adaptively adjusted through AKF, optimal estimation and smoothing are carried out on errors, and then processing is carried out through a post-stage loop filter. According to the method, the tracking continuity, robustness and precision in a high dynamic environment are effectively improved.

A method and apparatus for padding out-of-boundary pixels are disclosed. According to the method, input data associated with a current block located at or near a picture boundary are received, wherein the input data comprise prediction data and reconstructed residual data related to the current block. An extended motion-compensated reconstructed block for the current block is generated based on the prediction data and the reconstructed residual data, wherein the extended motion-compensated reconstructed block for the current block is inter coded and comprises a padded area located outside the picture boundary and a reconstructed current block. At least one in-loop filter is applied to the extended motion-compensated reconstructed block.

A video decoder is configured to determine, from the encoded video data, a block of a picture; apply a neural network (NN)-based filter to the block to generate a filtered block, wherein applying the NN-based filter comprises transforming the block of the picture with a transform block, wherein transforming the block of the picture with the transform block comprises rounding a floating point value to a nearest integer; determine a decoded version of the block based on the filtered block; and output a decoded version of the picture comprising the decoded version of the block.

A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.

A down-sampling function folds the thermal noise into a lower frequency band. A capacitor samples a voltage during a period of bus inactivity and supplies the sampled voltage to an input of operational amplifier in a loop filter of a phase-locked loop when the bus is active. The sampling frequency determines the reduction in thermal noise that can be achieved. The PLL generates a clock signal for a bus. A voltage generator charges the capacitor through a transistor when the bus is inactive. The transistor turns on responsive to the bus being inactive to allow the capacitor to charge and the transistor turns off responsive to the bus being active to isolate the capacitor and operational amplifier from the voltage generator. When the bus is active, the voltage across the capacitor is supplied to the operational amplifier.

Example methods and devices are described for processing video data. An example device includes one or more memories configured to store a reconstructed block of the video data and one or more processors in communication with the one or more memories. The one or more processors are configured to receive encoded video data, the encoded video data representing a block of the video data. The one or more processors are configured to reconstruct the block based on the encoded video data to generate the reconstructed block. The one or more processors are configured to perform a neural network (NN)-based filter process on the reconstructed block to generate a filtered block, wherein as part of performing the NN-based filter process, the one or more processors are configured to apply one or more residual groups to a residual group input, each of the residual groups comprising a respective attention block.

The invention discloses a digital signal processing method and system based on an FPGA, relates to the field of digital signal processing, and introduces a staged variable bandwidth CDR strategy. In the initial stage, the signal frequency offset is quickly estimated through feedforward frequency analysis, and a high-bandwidth loop is started on the basis of the signal frequency offset, so that top-speed locking is realized, and the requirements of production testing and other scenes on efficiency are met. When the system confirms that locking is stable through hardware logic, a multi-step interpolation state machine is triggered, the state machine can smoothly switch the coefficient of the loop filter from a high bandwidth mode to a low bandwidth mode without disturbance, and the lock losing risk in the switching process is avoided. Finally, in a stable low-bandwidth mode, the system can perform accurate jitter decomposition and data analysis by using a high-precision recovery clock. In this way, the two modes of rapid capture and high-precision measurement are fused in one operation process, and the static design limitation in the prior art is solved.

A video decoder is configured to determine, from encoded video data, a block of a picture; apply a neural network (NN)-based filter to the block to generate a filtered block, wherein to apply the NN-based filter, the one or processors process the block by a backbone block, wherein to process the block by the backbone block, the one or more processors are configured to: process input data for the block by a first activation layer; process an output of the first activation layer by a first convolution layer; process an output of the first convolution layer by a second activation layer; process an output of the second activation layer by a second convolution layer; and determine the filtered block based on an output of the second convolution layer.

A clock recovery system for recovering an in-band communication clock in a wireless power transfer system can in include: a phase locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide the error signal to the loop filter responsive to detected bits in the in-band communication bitstream. The phase locked loop can further include: a phase detector that computes an error signal from a difference between an instantaneous peak location and an estimated peak location correlated to a symbol in an in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency responsive to an output of the loop filter.

The invention discloses a phase synchronization circuit, an expanded phase-locked loop circuit and a delay phase-locked loop circuit. The phase synchronization circuit comprises a clock comparison unit, a biasing circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit. The clock comparison unit is connected with the clock output unit, the charge pump circuit and the time / analog conversion circuit; the biasing circuit is connected with the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected with the compensation charge pump circuit; the loop filter is connected with the charge pump circuit, the compensation charge pump circuit and the clock output unit. According to the phase synchronization circuit and the expansion structure thereof, time information can be directly converted into voltage for leakage current compensation, so that comparison action based on the voltage is not needed, and analog circuits such as an integrated operational amplifier and a voltage comparator are not needed. Therefore, it is possible to suppress an increase in the chip area of the compensation circuit and to reduce the phase error of the output clock.

The invention relates to a satellite navigation signal weak signal tracking loop switching method. The method comprises the following steps: designing a loop filter of a double-frequency phase-locked loop, a loop filter of a double-frequency frequency-locked loop and a loop filter of a pilot component single-frequency frequency-locked loop based on a Kalman filtering algorithm; constructing observed quantity and state quantity of a Kalman filter based on phase discrimination, frequency discrimination and code discrimination results of the B2a signal and the B1I signal; the state quantity output by the loop filter is fed back to a local carrier generator and a composite spreading code generator for error correction; in the filtering process, the adopted loop filter is switched according to the carrier-to-noise ratio, the phase locking detection index and the frequency locking detection index of the two signals, the corresponding loop filter is adaptively selected to complete parameter estimation, loop locking is further carried out, and signal tracking and positioning are achieved.

A device for decoding encoded video data is configured to determine, from the encoded video data, a block of a picture; apply a neural network (NN)-based filter process to the block to generate a filtered block, wherein to apply the NN-based filter process, the processing circuitry is configured to process a first input channel comprising sample data in a transform domain and process a second input channel comprising context data in a non-transform domain; determine a decoded version of the block based on the filtered block; and output a decoded version of the picture comprising the decoded version of the block.

An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and / or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.

Embodiments of the present disclosure provide a solution for video processing. A method for video processing is presented. In the method, a conversion between a current video unit of a video and a bitstream of the video is performed. A neural network (NN)-based loop filter is applied to the conversion. During the parameter selection process for the NN-based loop filter, the number of parameter candidates in the parameter candidate list for the NN-based loop filter is less than a threshold number.

The utility model discloses a Ka wave band frequency source based on a phase-locked loop structure, which comprises a master controller, a crystal oscillator module, a phase-locked loop module and a frequency doubling processing module, and the phase-locked loop module is respectively connected with the master controller, the crystal oscillator module and the frequency doubling processing module. The phase-locked loop module comprises a power supply module, a phase-locked loop main chip, a loop filter module and a locking state indication module, and the phase-locked loop main chip is respectively connected with the power supply module, the loop filter module, the locking state indication module and the main controller; the frequency doubling processing module comprises a low-pass filter, a high-pass filter, a fixed frequency attenuator, a power amplifier, a frequency doubling chip and a band-pass filter which are connected in sequence, and the input end of the low-pass filter is connected with the output end of the voltage-controlled oscillator. The frequency output by the phase-locked loop module is input to the frequency multiplication processing module, and the frequency multiplication processing module carries out harmonic suppression, attenuation, amplification and frequency multiplication processing on the input frequency, so that the output frequency has the advantages of low phase noise, wide frequency band and high stability.

An amplifier device may include a signal input for receiving a reference signal and amplifier circuitry. The amplifier device has a feed-forward signal path providing a feed-forward signal. First signal combining circuitry is configured to generate an error signal representative of a difference between the reference signal and a signal proportional to an amplified signal. Signal processing circuitry is configured to process the error signal to obtain a first signal. Second signal combining circuitry is configured to combine the first signal and the feed-forward signal to obtain a combined signal which is applied to an input of the amplifier circuitry. The signal processing circuitry has a limiter coupled to a loop filter. The limiter is configured to limit an amplitude of a second signal to a predetermined value thereby obtaining a limited signal. The loop filter is configured to obtain the first signal based on the limited signal.

This invention discloses a pilot-type carrier phase recovery circuit and a reverse antenna array system, belonging to the field of 5G millimeter-wave communication. The pilot-type carrier phase recovery circuit includes a digital phase detector, a quadrature mixer, a quadrature voltage-controlled oscillator, a low-pass filter, a high-pass filter, a polyphase filter, a loop filter, a first intermediate frequency amplifier, a second intermediate frequency amplifier, a first shaping circuit, and a second shaping circuit. Applied to a reverse antenna array system, this invention performs carrier phase recovery on the data signal and pilot signal output from the receiver, separating the data signal without spatial phase information and the spatial phase information used for reverse transmission. This invention enables high-order modulation full-duplex communication and real-time tracking of moving targets, featuring high integration, small area, high communication speed, and strong anti-interference capability.

This application relates to methods and apparatus for outputting a modulated signal for driving a switching output stage. A modulator circuit includes a digital modulator that receives an input signal modified by a correction signal and outputs the modulated signal. A feedback node receives a feedback signal of the output of the switching output stage and a first filter receives and filters an inverted version of the modulated signal to generate a reference signal, such that the reference signal has gain and phase matching to the feedback signal. The reference signal and the feedback signal are both applied to a summation node to generate an analog correction signal which is input to an ADC. An error loop filter is configured to filter the ADC output to generate the digital correction signal.

The application discloses a double feedback branch current compensation type charge pump circuit, which comprises a core circuit, a double feedback branch and a bias circuit connected in sequence, wherein the input node of the double feedback branch is connected with the core circuit for detecting the potential change of the output voltage, the first output node of the first feedback branch in the double feedback branch is connected with the gate of the bias circuit, the second output node of the second feedback branch is connected with the bias circuit, and the up and down charging and discharging currents are carried out phased current compensation through the bias circuit according to the degree of the output voltage deviating from the center potential. The application solves the mismatching problem of the up and down charging and discharging currents when the output voltage deviates from the center potential through the double feedback branch, can convert the phase error output by the frequency discriminator into the difference between the charging and discharging currents, charges and discharges the loop filter to generate the control voltage of the voltage controlled oscillator, thereby realizing the lower charging and discharging current mismatching in the wider control voltage range, the smaller ripple on the output voltage, and the optimization of the jitter performance of the output clock of the phase-locked loop.

A video encoder or a video decoder is disclosed which uses Intra Block Copy (IntraBC) mode. If IntraBC mode is enabled and a loop filter is not used for a current picture, a current decoded reference picture for the current picture is marked as a long-term reference picture before and during the decoding of the current picture. The current decoded reference picture is assigned to a reference picture list construction for IntraBC reference of the current picture, and by considering a buffer which stores only one reference picture, a buffer storage degree of a decoded picture buffer is calculated before starting to decode the current picture. According to another method, if a maximum decoded picture buffer size is 1, a variable or a syntax element is set to a target value to limit to use only one picture storage buffer in the decoded picture buffer to store a reference picture for encoding or decoding the current picture.

A control circuit for generating a control parameter that defines a state sequence of a power converter may include a loop filter configured to, based on an error signal between a reference current signal and a feedback current measurement signal, correct for unmodeled errors in the feedback current measurement signal to generate the control parameter. The control circuit may also include a first feedforward block configured to generate a first offset to the control parameter based on a slew rate of the reference current signal.