718 results about "Loop filter" patented technology

The invention relates to a digital lock-in amplifier based on a frequency adaptive technology and a weak signal acquisition system and method, and the system comprises a front-end signal processing module which is used for obtaining a weak signal to be detected; the frequency self-adaptive tracking module is used for performing fast Fourier transform on the frequency of the weak signal to be measured to obtain the position of the maximum spectral line so as to synthesize a frequency control word, further generate a local reference signal and simultaneously adjust the coefficients of a low-pass filter and a loop filter and the series adjustment mode of a carrier synchronization ring; the multi-rate narrow-band low-pass filter module is used for multiplying the digital signal by a local reference signal and then carrying out filtering and down-sampling on a high-frequency signal to obtain a plurality of mutually orthogonal difference frequency components; the vector operation module is used for carrying out vector operation on the plurality of mutually orthogonal difference frequency components to obtain the phase and the amplitude in the weak signal to be measured; and the man-machine interaction module is used for displaying and storing the phase and the amplitude in the weak signal to be detected.

A method of processing video data. The method includes selecting an in-loop filter from a plurality of neural network (NN) filter model candidates, wherein the plurality of NN filter model candidates are based on a reconstructed quality level of a video unit, and performing a conversion between a video media file comprising the video unit and a bitstream based on the in-loop filter selected. A corresponding video coding apparatus and non-transitory computer readable medium are also disclosed.

Disclosed are systems and methods for adaptive noise cancellation (ANC) at a virtual microphone located at the eardrum of a wearer of an earphone. The techniques estimate the level of leakiness of ambient noise in the earphone from the magnitude of the gain of the transfer function of the feed forward loop filter of the ANC. Based on the estimated leakiness, the techniques estimate the transfer function of the feed forward loop filter to compensate for the difference in the effect of noise cancellation at the virtual microphone and error microphone. A bias term that represents the difference in the frequency response of the attenuated noise at the virtual and error microphone may be added to the adaptive feed forward algorithm. The ANC operation may apply the bias term to the adaptive feed forward loop filter to reduce the ambient noise at the eardrum rather than at the error microphone.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

Embodiments of the invention provide a high density liquid cooling system including a rack, primary loop piping including a primary inlet, a primary outlet, a primary loop filter, and a primary bypass valve, and secondary loop piping including a secondary inlet, a secondary outlet, a first pump, a first filter downstream of the first pump, and a secondary bypass valve. The system includes a heat exchanger having a first side and a second side. When the primary bypass valve is open, at least a portion of the fluid in the primary loop piping flows through the primary inlet and the primary outlet without traversing the heat exchanger, and when the secondary bypass valve is open, at least a portion of the fluid in the secondary loop piping flows through the secondary inlet and the secondary outlet without traversing the heat exchanger.

The invention provides a continuous time Sigma-Delta modulator with constant transconductance bias and negative resistance compensation. The continuous time Sigma-Delta modulator comprises a loop filter, a quantizer and a digital-to-analog converter, the loop filter is used for amplifying a signal in an effective signal bandwidth and attenuating an out-of-band signal at the same time, and the loop filter comprises a first-stage negative resistance compensation integrator and a second-stage negative resistance compensation integrator which are connected in sequence, the first-stage negative resistance compensation integrator comprises a first negative resistance unit containing a negative resistance of a constant transconductance bias circuit and a first integrator unit containing an operational amplifier, and a single operational amplifier resonator structure is formed to generate a second-order response; the integrator of the second-stage negative resistance compensation comprises a second negative resistance unit and a second integrator unit comprising an operational amplifier; and the quantizer is connected with the loop filter, adopts a successive approximation analog-to-digital converter, and is used for converting the analog voltage signal into a digital signal and outputting the digital signal. And the digital-to-analog converter is used for converting the digital signal into an analog signal and feeding back the analog signal to the loop filter.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention belongs to the technical field of optical communication, and particularly relates to a high-stability photo-generated millimeter wave system based on a phase-locked loop, which comprises a first laser, a second laser, an acousto-optic frequency shifter, a dense wavelength division multiplexer, an inner loop feedback control loop and an outer loop signal output branch, the inner loop feedback control loop comprises a phase modulator, an optical filter, a photoelectric detector, a frequency division arithmetic unit, a phase frequency detector, a loop filter, a voltage-controlled oscillator and a first power amplifier which are sequentially connected in series, and the output of the first power amplifier is connected with an acousto-optic frequency shifter; the inner loop feedback control loop further comprises a cesium atomic clock, a microwave source and a second power amplifier; wherein the cesium atomic clock is connected with the microwave source and the phase frequency detector, and the output of the microwave source is connected with the phase modulator after passing through the second power amplifier.

The invention provides a three-phase grid-connected phase-locked loop two-stage filter and a filtering method thereof, and belongs to the related technical field of effective detection and extraction of power grid voltage phase signals. The invention provides a three-phase grid-connected phase-locked loop two-stage filter and a filtering method thereof in order to solve the problem that a traditional phase-locked loop filter cannot completely filter harmonic waves and direct-current offset voltage due to insufficient filtering capacity under a non-ideal power grid condition. In order to enhance the anti-interference capability of a phase-locked loop filter, the invention designs a mixed-order generalized integrator and constructs a double-mixed-order generalized integrator. Meanwhile, the double-mixed-order generalized integrator serves as a first-stage filtering unit, and a Parker transformation unit and a comb filter are introduced to serve as a second-stage filtering unit, so that a double-stage filter is formed through combination. By applying the filtering method in the phase-locked loop, it is proved that the method can effectively filter interference in a power grid. The method is mainly used for the grid-connected phase-locked loop filtering process under the non-ideal power grid condition.

An audio amplifier includes a loop filter, at least one high pass filter (HPF) circuit, a pulse width modulation (PWM) generator, and a power stage. The loop filter is arranged to receive an audio signal and a feedback signal, and includes a first amplifier and a second amplifier, wherein the first amplifier has a first output node, and is arranged to process the audio signal and the feedback signal; the second amplifier has a first input node, and is arranged to receive a first amplifier input and a second amplifier input; and the first amplifier input is obtained from a signal path coupled between the first output node and the first input node. The at least one HPF circuit is coupled between the first amplifier and the second amplifier, and is arranged generate and output the second amplifier input according to an amplifier output of the first amplifier.

A method implemented by a video coding apparatus. The method includes determining, in real time, padding dimensions for padding samples to be applied to a video unit of a video for in-loop filtering, wherein d1, d2, d3, and d4 represent the padding dimensions corresponding to top, bottom, left, and right boundaries of the video unit, respectively; and performing a conversion between a video unit and a bitstream of the video based on the padding dimensions that were determined. A corresponding video coding apparatus and non-transitory computer-readable recording medium are also disclosed.

A video encoder is configured to determine to filter video data using a neural network (NN)-based filter and a fixed block size inference, and encode a flag that indicates the fixed block size inference is used for the NN-based filter. Reciprocally, a video decoder is configured to decode a flag that indicates whether a fixed block size inference is used for an NN-based filter, and filter video data using the NN-based filter based on the flag. The flag may be signaled at a sequence parameter set (SPS) level.

An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and / or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.

The invention discloses a phase-locked loop quantization noise calibration method and system, electronic equipment and a storage medium. The method comprises the following steps: a phase frequency detector performs correlation processing on a feedback signal output by a modulator and a reference signal output by a phase discriminator to generate a gain coefficient; multiplying the gain coefficient by a feedback signal output by the modulator to output a first gain signal; subtracting the first gain signal from a reference signal output by the phase discriminator to output a second gain signal; the second gain signal is filtered by the digital loop filter to obtain a filtered signal and the filtered signal is output to the digital time converter; and the digital time converter processes the filtering signal to obtain a pulse signal suitable for being processed by the phase discriminator and outputs the pulse signal to the phase discriminator. The LMS algorithm is adopted, and on the basis of the complementary digital time converter calibration technology, quantization noise is eliminated through a low-energy-consumption circuit.

A method of processing video data includes receiving, with a neural network in-loop filter (NN-ILF), a current block of video data of a current picture; and filtering, with the NN-ILF, the current block of video data to generate a filtered current block of video data, wherein filtering the current block of video data comprises: generating, with an attention block of the NN-ILF, an attention map indicative of a correlation between elements of features of the current block of video data; modifying, with the attention block of the NN-ILF, the attention map based on a size of blocks used for training the NN-ILF to generate a modified attention map; generating, with the attention block of NN-ILF, feature data based on the modified attention map; and filtering, with the NN-ILF, the current block of video data based on the feature data to generate the filtered current block of video data.

Various implementations described herein include methods and systems for coding video. In one aspect, a video bitstream includes a current image frame and a first syntax element for a CCSO mode. When the CCSO mode is enabled, a plurality of candidate luma sets are identified in a filter range that includes a first luma sample and neighboring luma samples. Each candidate luma set includes respective luma samples having positions symmetric with respect to a position of the first luma sample, and each luma sample located in the filter range is used in at least one of the candidate luma sets. A set of target luma samples is selected from the candidate luma sets. A loop filter is applied to combine the set of target luma samples and the first luma sample to generate the first sample offset of a first color sample collocated with the first luma sample.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

A method of coding video data, the method comprising: obtaining input data, wherein the input data includes one or more of predicted video data, reconstructed video data, quantization parameter data, boundary strength data, or prediction mode data; converting the input data from an input domain to a transform domain to generate converted video data; applying a neural network (NN)-based in-loop filter (ILF) to the converted video data to generate filtered video data; and converting the filtered video data from the transform domain to the input domain.

A fractional-N PLL includes a reference oscillator, a multi-modulus divider-based phase-error-to-digital converter driven by the reference oscillator, a digital loop filter, and a digitally controlled oscillator. Digital-to-time to converter mismatch noise cancellation digital logic is between the phase-error-to-digital converter and the digital loop filter. Error from digital-to-time converter component mismatches is partially cancelled by the digital logic.

The invention discloses a video coding method and device, equipment and a storage medium, and relates to the technical field of video coding and decoding. The method comprises the following steps: acquiring a JND threshold value of a current block of a first video frame; selecting a compensation mode of the current block from at least two compensation modes included in the SAO mode according to the JND threshold value of the current block under the condition that the loop filtering mode of the current block comprises the SAO mode; and encoding the current block according to the compensation mode of the current block. As the JND threshold can reflect the human eye visual characteristics, consideration of the human eye visual characteristics can be introduced by selecting the compensation mode of the current block through the JND threshold of the current block, which is beneficial to improving the selection accuracy of the compensation mode, thereby being beneficial to improving the coding quality of the video frame.

The invention relates to a high-dynamic time division navigation signal tracking method assisted by adaptive Kalman filtering, and belongs to the technical field of satellite navigation. Aiming at the problems of tracking delay, precision reduction and easy lock loss caused by discontinuous loop update in a high dynamic environment in the existing time division navigation signal tracking method, the method comprises the steps of carrier and code stripping, time-slot error identification, adaptive Kalman filter AKF preprocessing and loop filtering and tracking of three-order FLL-assisted four-order PLL. And full-time-slot continuous tracking is realized. The core of the method is that process noise covariance is adaptively adjusted through AKF, optimal estimation and smoothing are carried out on errors, and then processing is carried out through a post-stage loop filter. According to the method, the tracking continuity, robustness and precision in a high dynamic environment are effectively improved.

A method and apparatus for padding out-of-boundary pixels are disclosed. According to the method, input data associated with a current block located at or near a picture boundary are received, wherein the input data comprise prediction data and reconstructed residual data related to the current block. An extended motion-compensated reconstructed block for the current block is generated based on the prediction data and the reconstructed residual data, wherein the extended motion-compensated reconstructed block for the current block is inter coded and comprises a padded area located outside the picture boundary and a reconstructed current block. At least one in-loop filter is applied to the extended motion-compensated reconstructed block.

A video encoder and video decoder are configured to perform neural network (NN)-based filtering. The video encoder and video decoder may receive a picture of video data, reconstruct the picture of video data, and perform an NN-based filter process on one or more blocks of the reconstructed picture of video data using an NN-based filter, wherein the NN-based filter includes a pair of backbone blocks, each of the pair of backbone blocks comprising a three-component one-dimensional (1D) decomposition of a multi-dimensional convolution, wherein the 1D decomposition includes at least one layer with feature channel reduction.

The present invention discloses a CSS-PD (Charge-Steering-Sampling Phase Discriminator), a DLF (Digital Loop Filter) and a CSS-ADPLL (Charge-Steering-Sampling All Digital Phase-Locked Loop) thereof The CSS-PD includes a Frac-N C-DAC, a CSS, and a SAR-ADC. The CSS-PD has a controlling method including four steps: (1) charge presetting; (2) charge-steering sampling; (3) fractional charge compensating; (4) digitalizing. Wherein when ΔVerr,pn sampled by the CSS included two errors ΔVerr,pn and ΔVerr,frac, ΔVerr,frac had fractional charge compensating by setting part of the capacitors of the Cfrac of the Frac-N C-DAC to a Vref,adc. Vref,adc was satisfied the following formula: ΔVerr,frac=Dfrac·Cunit / (Cfrac+Csar)·Vref,adc. Cunit is for capacitance of Cfrac, Cfrac is also for capacitance of Cfrac, Csar is also for capacitance of Csar of the SAR-ADC, Dfrac is the output signal of the Frac-N C-DAC. A CSS-ADPLL with the CSS-PD can obtain the performance of low jitter, low fractional division spurious and low reference spurious at the same time.

A video decoder is configured to determine, from the encoded video data, a block of a picture; apply a neural network (NN)-based filter to the block to generate a filtered block, wherein applying the NN-based filter comprises transforming the block of the picture with a transform block, wherein transforming the block of the picture with the transform block comprises rounding a floating point value to a nearest integer; determine a decoded version of the block based on the filtered block; and output a decoded version of the picture comprising the decoded version of the block.

A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.

A down-sampling function folds the thermal noise into a lower frequency band. A capacitor samples a voltage during a period of bus inactivity and supplies the sampled voltage to an input of operational amplifier in a loop filter of a phase-locked loop when the bus is active. The sampling frequency determines the reduction in thermal noise that can be achieved. The PLL generates a clock signal for a bus. A voltage generator charges the capacitor through a transistor when the bus is inactive. The transistor turns on responsive to the bus being inactive to allow the capacitor to charge and the transistor turns off responsive to the bus being active to isolate the capacitor and operational amplifier from the voltage generator. When the bus is active, the voltage across the capacitor is supplied to the operational amplifier.

Example methods and devices are described for processing video data. An example device includes one or more memories configured to store a reconstructed block of the video data and one or more processors in communication with the one or more memories. The one or more processors are configured to receive encoded video data, the encoded video data representing a block of the video data. The one or more processors are configured to reconstruct the block based on the encoded video data to generate the reconstructed block. The one or more processors are configured to perform a neural network (NN)-based filter process on the reconstructed block to generate a filtered block, wherein as part of performing the NN-based filter process, the one or more processors are configured to apply one or more residual groups to a residual group input, each of the residual groups comprising a respective attention block.

The invention relates to an improved ABSPD clock recovery method under single Baud rate sampling, clock synchronization of receiving and transmitting end signals is realized through a clock recovery loop based on a full number font, and when a provided timing error detector calculates a timing error e, symbol judgment and shift operation are used for replacing numerical multiplication; after a timing error e is calculated by the timing error detector, the timing error e is input into a loop filter for noise filtering, and a control word W is obtained; controlling the numerically controlled oscillator by using the control word W, and calculating a fractional interval mu k according to the output NCO of the numerically controlled oscillator and the control word W; and carrying out interpolation on the received signal in an interpolation filter by utilizing the integer mark mk of the symbol and the calculated fractional interval mu k so as to calculate and obtain data with correct timing. According to the invention, ABSPD clock recovery under single Baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is obviously reduced.