275 results about "Loop filter" patented technology

Embodiments of the invention provide a high density liquid cooling system including a rack, primary loop piping including a primary inlet, a primary outlet, a primary loop filter, and a primary bypass valve, and secondary loop piping including a secondary inlet, a secondary outlet, a first pump, a first filter downstream of the first pump, and a secondary bypass valve. The system includes a heat exchanger having a first side and a second side. When the primary bypass valve is open, at least a portion of the fluid in the primary loop piping flows through the primary inlet and the primary outlet without traversing the heat exchanger, and when the secondary bypass valve is open, at least a portion of the fluid in the secondary loop piping flows through the secondary inlet and the secondary outlet without traversing the heat exchanger.

Various implementations described herein include methods and systems for coding video. In one aspect, a video bitstream includes a current image frame and a first syntax element for a CCSO mode. When the CCSO mode is enabled, a plurality of candidate luma sets are identified in a filter range that includes a first luma sample and neighboring luma samples. Each candidate luma set includes respective luma samples having positions symmetric with respect to a position of the first luma sample, and each luma sample located in the filter range is used in at least one of the candidate luma sets. A set of target luma samples is selected from the candidate luma sets. A loop filter is applied to combine the set of target luma samples and the first luma sample to generate the first sample offset of a first color sample collocated with the first luma sample.

The invention relates to a high-dynamic time division navigation signal tracking method assisted by adaptive Kalman filtering, and belongs to the technical field of satellite navigation. Aiming at the problems of tracking delay, precision reduction and easy lock loss caused by discontinuous loop update in a high dynamic environment in the existing time division navigation signal tracking method, the method comprises the steps of carrier and code stripping, time-slot error identification, adaptive Kalman filter AKF preprocessing and loop filtering and tracking of three-order FLL-assisted four-order PLL. And full-time-slot continuous tracking is realized. The core of the method is that process noise covariance is adaptively adjusted through AKF, optimal estimation and smoothing are carried out on errors, and then processing is carried out through a post-stage loop filter. According to the method, the tracking continuity, robustness and precision in a high dynamic environment are effectively improved.

The utility model discloses a Ka wave band frequency source based on a phase-locked loop structure, which comprises a master controller, a crystal oscillator module, a phase-locked loop module and a frequency doubling processing module, and the phase-locked loop module is respectively connected with the master controller, the crystal oscillator module and the frequency doubling processing module. The phase-locked loop module comprises a power supply module, a phase-locked loop main chip, a loop filter module and a locking state indication module, and the phase-locked loop main chip is respectively connected with the power supply module, the loop filter module, the locking state indication module and the main controller; the frequency doubling processing module comprises a low-pass filter, a high-pass filter, a fixed frequency attenuator, a power amplifier, a frequency doubling chip and a band-pass filter which are connected in sequence, and the input end of the low-pass filter is connected with the output end of the voltage-controlled oscillator. The frequency output by the phase-locked loop module is input to the frequency multiplication processing module, and the frequency multiplication processing module carries out harmonic suppression, attenuation, amplification and frequency multiplication processing on the input frequency, so that the output frequency has the advantages of low phase noise, wide frequency band and high stability.

An amplifier device may include a signal input for receiving a reference signal and amplifier circuitry. The amplifier device has a feed-forward signal path providing a feed-forward signal. First signal combining circuitry is configured to generate an error signal representative of a difference between the reference signal and a signal proportional to an amplified signal. Signal processing circuitry is configured to process the error signal to obtain a first signal. Second signal combining circuitry is configured to combine the first signal and the feed-forward signal to obtain a combined signal which is applied to an input of the amplifier circuitry. The signal processing circuitry has a limiter coupled to a loop filter. The limiter is configured to limit an amplitude of a second signal to a predetermined value thereby obtaining a limited signal. The loop filter is configured to obtain the first signal based on the limited signal.

This invention discloses a pilot-type carrier phase recovery circuit and a reverse antenna array system, belonging to the field of 5G millimeter-wave communication. The pilot-type carrier phase recovery circuit includes a digital phase detector, a quadrature mixer, a quadrature voltage-controlled oscillator, a low-pass filter, a high-pass filter, a polyphase filter, a loop filter, a first intermediate frequency amplifier, a second intermediate frequency amplifier, a first shaping circuit, and a second shaping circuit. Applied to a reverse antenna array system, this invention performs carrier phase recovery on the data signal and pilot signal output from the receiver, separating the data signal without spatial phase information and the spatial phase information used for reverse transmission. This invention enables high-order modulation full-duplex communication and real-time tracking of moving targets, featuring high integration, small area, high communication speed, and strong anti-interference capability.

The application discloses a double feedback branch current compensation type charge pump circuit, which comprises a core circuit, a double feedback branch and a bias circuit connected in sequence, wherein the input node of the double feedback branch is connected with the core circuit for detecting the potential change of the output voltage, the first output node of the first feedback branch in the double feedback branch is connected with the gate of the bias circuit, the second output node of the second feedback branch is connected with the bias circuit, and the up and down charging and discharging currents are carried out phased current compensation through the bias circuit according to the degree of the output voltage deviating from the center potential. The application solves the mismatching problem of the up and down charging and discharging currents when the output voltage deviates from the center potential through the double feedback branch, can convert the phase error output by the frequency discriminator into the difference between the charging and discharging currents, charges and discharges the loop filter to generate the control voltage of the voltage controlled oscillator, thereby realizing the lower charging and discharging current mismatching in the wider control voltage range, the smaller ripple on the output voltage, and the optimization of the jitter performance of the output clock of the phase-locked loop.

A video encoder or a video decoder is disclosed which uses Intra Block Copy (IntraBC) mode. If IntraBC mode is enabled and a loop filter is not used for a current picture, a current decoded reference picture for the current picture is marked as a long-term reference picture before and during the decoding of the current picture. The current decoded reference picture is assigned to a reference picture list construction for IntraBC reference of the current picture, and by considering a buffer which stores only one reference picture, a buffer storage degree of a decoded picture buffer is calculated before starting to decode the current picture. According to another method, if a maximum decoded picture buffer size is 1, a variable or a syntax element is set to a target value to limit to use only one picture storage buffer in the decoded picture buffer to store a reference picture for encoding or decoding the current picture.

A control circuit for generating a control parameter that defines a state sequence of a power converter may include a loop filter configured to, based on an error signal between a reference current signal and a feedback current measurement signal, correct for unmodeled errors in the feedback current measurement signal to generate the control parameter. The control circuit may also include a first feedforward block configured to generate a first offset to the control parameter based on a slew rate of the reference current signal.

A method comprising: receiving an image block unit of a frame, the image block unit comprising samples in color channels comprising at least one chrominance channel and one luminance channel; reconstructing samples of said color channels to produce reconstructed chrominance samples and reconstructed luminance samples; determining that a picture-level model list re-ordering is used; means for determining a reference picture; determining a list of cross-component models for the reference picture; generating a re-ordered list where the cross-component models of the determined list have been re-ordered; determining an index for a cross-component model; means for deriving the cross-component model from the re-ordered list with the given index; applying a first adaptive in-loop filter for the reconstructed luminance samples; and the derived cross-component model for the reconstructed luminance samples to obtain an additional input for reconstructing the chrominance samples.

A potentiostat architecture includes one or more feedback loops configured to regulate and maintain electrode potentials while measuring a sensing current. At least one of the feedback loops include a comparator configured to sense a voltage difference and output a signal based on the voltage difference, a digital loop filter configured to receive the signal from the comparator and output feedback digital bits related to a control, and a digital to analog convertor configured to receive the signal from the comparator and output feedback digital bits related to a control.

A decoding method includes: parsing bitstream to determine value of first syntax element identification information; determining, when the identification information indicates that preset selection network model is enabled to be used to perform model decision for current block, at least two output values according to preset selection network model. The at least two output values include first value corresponding to each candidate in-loop filter network model when in-loop filter network model is used for current block, and second value when in-loop filter network model is not used; determining, according to output values, target in-loop filter network model when in-loop filter network model is used for current block, or determining according to output values that in-loop filter network model is not used; and filtering, when in-loop filter network model is used for current block, current block using target in-loop filter network model, to obtain first reconstructed picture block of current block.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

Embodiments of the present disclosure provide a solution for video processing. A method for video processing is proposed. In the method, a conversion between a current video unit of a video and a bitstream of the video is performed. A neural network (NN)-based loop filter is applied for the conversion. During a parameter selection process for the NN-based loop filter, the number of parameter candidates in a parameter candidate list for the NN-based loop filter is less than a threshold number.

A video processing method is provided, comprising: performing a conversion between a codec representation of a video comprising one or more video regions and a video, wherein the codec representation includes side information of loop shaping (ILR) applicable to some of the one or more video regions, wherein the side information provides parameters for reconstructing video units of the video regions based on representations of video units in a first domain and a second domain, and / or parameters for scaling chroma residuals of chroma video units, and wherein the side information applicable to some of the one or more video regions is encoded and decoded without direct inheritance from other video regions.

The invention provides a phase-locked loop rapid locking circuit structure and a control method thereof, the circuit structure comprises a voltage-controlled oscillator, a frequency divider, a phase discriminator and a rapid locking loop filter, and the rapid locking loop filter comprises a capacitive digital-to-analog conversion module. According to the invention, the capacitive digital-to-analog converter module is adopted, and the control voltage of the voltage-controlled oscillator can be rapidly and accurately set based on the charge sharing principle, so that rapid locking is realized; moreover, the structure multiplexes the capacitor in the loop filter, and does not need an extra area. The method has the advantages of high precision, low power consumption and low cost, and has extremely high application value and potential.

A video coding method and device using an in-loop filter adaptive to various types of noise and characteristics. The video decoding device generates an output block by inputting a reconstruction block for a current block to a deep learning-based in-loop filter. The video decoding device selects a block for retaining the in-loop filter from the reconstruction block and retrains the in-loop filter using the selected reconstruction block and a target block.

The invention relates to a device and method for evaluating the influence of a power supply noise group on phase noise of a phase-locked loop, and relates to the technical field of phase-locked loops, and the device comprises a sine phase discriminator which detects the phase difference between an external reference signal and a feedback signal of a voltage-controlled oscillator; the input end of the loop filter is connected with the output end of the sine phase discriminator; the input end of the voltage-controlled oscillator is connected with the output end of the loop filter; establishing a phase-locked loop simulation model composed of a sine phase discriminator, a loop filter and a voltage-controlled oscillator; selecting a linear voltage-stabilized power supply series, and calculating a phase noise matrix with power supply noise corresponding to each model; different types of linear voltage-stabilized power supplies are respectively used for supplying power, and actually measured phase noise data corresponding to each type are tested and recorded; power supply noise group distribution is fitted by adopting a power law function, and optimal linear voltage-stabilized power supply model selection under the phase-locked loop architecture is determined. The method has the beneficial effects that the accuracy of predicting the phase noise is improved, the optimal solution is realized, and the model most suitable for the phase-locked loop architecture in the LDO series is selected.

A mechanism for processing video data is disclosed. The mechanism determines to process video information with a high operating point (HOP) filter that includes a deep convolutional layer or a packet convolutional layer. Conversion is performed between the visual media data and the bitstream based on the HOP filter.

The utility model discloses a Ka wave band broadband transmit-receive front end comprising a local oscillator source module, an X frequency conversion module, a Ka wave band frequency conversion module and an antenna module, the local oscillator source module is respectively connected with the X frequency conversion module and the Ka wave band frequency conversion module, and the X frequency conversion module, the Ka wave band frequency conversion module and the antenna module are connected in sequence. The local oscillator source module comprises a crystal oscillator module, a phase frequency detector, a loop filter, a voltage-controlled oscillator, an N frequency divider and a frequency doubling processing module, the crystal oscillator module, the phase frequency detector, the loop filter, the voltage-controlled oscillator and the frequency doubling processing module are connected in sequence, and the N frequency divider is connected with the phase frequency detector and the voltage-controlled oscillator. The local oscillation source module can stably generate high-quality signals, the transmitting-receiving front end adopts a superheterodyne structure and uses two times of frequency conversion, the first time of frequency conversion is Ka-X wave band frequency conversion, the second time of frequency conversion is X wave band frequency conversion, and mirror image frequency interference is well inhibited by using the two times of frequency conversion.

Disclosed is a loop filter method based on an adaptive pixel classification criterion. The loop filter method based on an adaptive pixel classification criterion in an image decoding device includes a step of classifying a restored sample according to an absolute classification criterion or a relative classification criterion, a step of obtaining offset information according to a result of classifying the restored sample, a step of adding the offset value to the restored sample with reference to the obtained offset information, and a step of outputting the restored sample to which the offset value is added. Thus, errors of the restored sample can be corrected.

The application discloses a frequency modulation rate variable laser linear frequency modulation device and a frequency modulation method thereof. The device comprises a wideband tunable laser, a micro-optical lens, a beam splitter, an adjustable optical delay unbalanced MZ interferometer, a balanced photodetector, a phase discriminator, a loop filter, an up / down switch control circuit and an integrator. The adjustable optical delay unbalanced MZ interferometer comprises two couplers and an adjustable optical fiber delay line unit. According to the relationship between the linear frequency modulation light frequency and time of the upper and lower arms of the interferometer, when the delay amount of the adjustable optical fiber delay line unit changes, the frequency modulation rate of the output laser can be changed. The application changes the time delay of the light by using the adjustable optical fiber delay line, so that the frequency modulation rate can be changed.

A device for decoding video data receives a picture of video data; reconstructs a block of the picture of video data to generate a reconstructed block; and performs a neural network (NN)-based filter process on the reconstructed block to generate a filtered block, wherein the NN-based filter process includes performing a plurality of separable convolutions in parallel with a point-wise input convolution.

The invention discloses an all-digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, and the phase-locked loop comprises a time-to-digital converter which is implemented based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; the digital loop filter is realized based on high-level integration and is used for outputting a frequency control word according to the phase error signal; the numerical control oscillator is realized based on the IP core and is used for outputting a digital sine wave signal according to the frequency control word; and the feedback frequency divider is realized based on high-level integration and is used for outputting a feedback clock signal according to the digital sine wave signal. According to the all-digital phase-locked loop, the modules in the all-digital phase-locked loop are strategically divided, high-level synthesis and register transfer level design are strategically combined, the all-digital phase-locked loop which is high in performance and efficiency and can be stably locked is achieved, and the all-digital phase-locked loop can be widely applied to the technical field of digital circuit design.

The present application relates to the technical field of encoding and decoding, and discloses a decoding method, an encoding method, an apparatus, a device, a storage medium, and a program product, capable of solving the problems of poor filtering effect of a filter, which is not conducive to improving the encoding and decoding performance. The decoding method in embodiments of the present application comprises: parsing a bitstream to obtain first information, the first information being used for determining a region corresponding to a filter coefficient group in a filter coefficient set; and performing loop filtering on a reconstructed block of a current block on the basis of the first information, the filter coefficient set, and a region index of the current block, wherein the region index of the current block is determined on the basis of the size of the current block. The embodiments of the present application are applied to video encoding and decoding.

Methods and devices for the phase synchronization of a multiplex signal which are designed for: receiving a Pilot radio signal and a Data radio signal; generating in-phase and quadrature components of said signals; generating a Phase Detector (PD) signal for the Data radio signal using the in-phase component and quadrature component of the Data radio signal; generating a PD signal for the Pilot radio signal using the in-phase component and quadrature component of the Pilot radio signal; closing a feedback loop through a chain of units consisting of a loop filter, an NCO and correlators; generating a signal to reverse the polarity of the PD signal for the Data radio signal using the in-phase component of the Pilot radio signal; generating a corrected PD signal for the Data radio signal by multiplying the polarity reversal signal by the PD signal for the Data radio signal; generating an Extended Phase Detector (EDP) signal by weighted summing of the corrected PD signal for the Data radio signal and the PD signal for the Pilot radio signal to close the feedback loop.

A method comprising: receiving an image block unit of a frame, the image block unit comprising samples in color channels comprising at least one chrominance channel and one luminance channel; reconstructing samples of said colors channels to produce reconstructed chrominance samples and reconstructed luminance samples; determining a list of cross-component models; determining an index in the list of cross-component models; deriving a cross-component model from the list with the given index; applying a first adaptive in-loop filter for the reconstructed luminance samples; applying the derived cross-component model for the reconstructed luminance samples to obtain an additional input for reconstruction of samples of at least one chrominance channel.

The present application belongs to the technical field of encoding and decoding. Disclosed are a decoding method and apparatus, an encoding method and apparatus, and a device, a storage medium and a program product, which can solve the problems of the waste of encoding bits and the adverse impact on the encoding performance. The decoding method in the embodiments of the present application comprises: parsing a bit stream, so as to obtain a first filter coefficient set; and on the basis of the first filter coefficient set, performing in-loop filtering on a reconstructed block of a first chroma component, and on the basis of the first filter coefficient set, performing in-loop filtering on a reconstructed block of a second chroma component. The embodiments of the present application are applied to video encoding and decoding.

The application discloses a frequency synchronization method of coherent clock system in high-speed data transmission, and a frequency synchronization method and equipment structure for providing high-precision time-frequency reference transmission and 10Gbps data stream transmission. A high-speed modulator is used to generate a radio frequency signal at a local end and a remote end, and the radio frequency signal is received from the opposite end. A carrier tracking technology is used to recover the radio frequency carrier, and a frequency discrimination and phase discrimination value is obtained through a signal processing algorithm in a digital domain. The local frequency discrimination and phase discrimination value is sent to the remote end, the remote end uses the local value and the opposite value to realize joint phase discrimination, and then the joint phase discrimination is sent to a loop filter. The loop filter outputs a voltage control signal, and the remote end uses the voltage control signal to control a voltage-controlled crystal oscillator, so that the frequency synchronization between the remote end and the local end is realized. The method can realize single-fiber single-wavelength bidirectional time-frequency synchronization and high-speed data transmission, can fully utilize the optical wavelength resources of the optical fiber transmission system, and can save the optical wavelength resources compared with the traditional method, and has higher frequency synchronization precision.

A phase-locked loop (PLL) circuit, an operating method thereof, and a sub-range control circuit are provided. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sigma-delta modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal according to an input frequency signal and a feedback signal. The processing circuit limits a voltage level corresponding to the charging current signal within a certain voltage range according to a prediction signal to generate a digital output. The loop filter is coupled to the TDC to perform a low-pass filtering operation according to the digital output. The DCO generates a DCO frequency signal according to an output of the loop filter. The feedback circuit generates the feedback signal according to the DCO frequency signal. The sigma-delta modulator (SDM) generates a phase signal representing accumulated phase shift information to the prediction circuit according to information of the feedback circuit and fractional frequency information. The prediction circuit generates the prediction signal according to the phase signal.