53 results about "Process variation" patented technology

A system and method for designing an integrated relaxation oscillator that exhibits reduced change in the frequency of oscillation caused by process variation. Improved sensitivity to component variation due to process shift is achieved through using more than one structure type when implementing the resistors affecting the RC time constant and threshold (trip point) voltages of the oscillator. Structure types are related to the fabrication process and for a CMOS process include, but are not limited to n-diffusion, p-diffusion, n-well, p-well, pinched n-well, pinched p-well, poly-silicon and metal. Each structure type exhibits statistically independent process variations, allowing for application of Lyapunov's extension of the Central Limit Theorem for statistically uncorrelated events to desensitize the effect from different possible causes. Thus, improvement in the performance of the oscillator may be achieved with a reduced trim requirement and without using external precision resistors.

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

A method for using an identification value for a security application is disclosed. The method may include the steps of (A) generating the identification value based on a plurality of semiconductor fabrication process variations, (B) generating a key by reducing a bit error rate of the identification value, wherein the key may not be available external to the security application and (C) generating an output signal by one of (i) encoding and (ii) decoding an input signal in response to said key.

A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at least one die of a wafer and includes at least one racing path circuit having at least two paths. The method further includes collecting the race condition testing data and evaluating the collected race condition testing data. The race condition testing data is correlated to a process variation of the at least one die.

Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.

Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.

Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted. Based on the output, one or more functional blocks are modified by a control sensor component to reduce semiconductor system degredation in real-time.

A class B amplifier circuit produces a deadband that is independent of semiconductor process variations and creates a positive voltage when a differential input voltage is non-zero. A differential input amplifier couples differential currents representing the differential input voltage to a logarithmic compression circuit, which in turn creates an output voltage that is a function of the differential input voltage and is independent of semiconductor process variations. Transistor devices in the differential amplifier and the logarithmic compression circuit are biased in the non-saturated region of a transistor transfer curve in a weak inversion state. A combination of two comparator circuits compares the output voltage to a reference voltage to create a combined output voltage that is a positive when the input is non-zero.

A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case / worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual / computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.

A High Energy Beam Processing (HEBP) system provides feedback signal monitoring and feedback control for the improvement of process repeatability and three-dimensional (3D) printed part quality. Signals reflecting process parameters and the quality of the fabricated parts are analyzed by monitoring feedback signals from artifact sources with a process controller which adjusts process parameters. In this manner, fabricated parts are produced more accurately and consistently from powder feedstock by compensating for process variation in response to feedback signals.

One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

Metrology methods and respective software and module are provided, which identify and remove measurement inaccuracy which results from process variation leading to target asymmetries. The methods comprise identifying an inaccuracy contribution of process variation source(s) to a measured scatterometry signal (e.g., overlay) by measuring the signal across a range of measurement parameter(s) (e.g., wavelength, angle) and targets, and extracting a measurement variability over the range which is indicative of the inaccuracy contribution. The method may further assume certain functional dependencies of the resulting inaccuracy on the target asymmetry, estimate relative donations of different process variation sources and apply external calibration to further enhance the measurement accuracy.

The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions. An attached AI engine will infer from the model, the input signals, the usage conditions and the environmental conditions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications.

Metrology methods are provided, which comprise identifying overlay critical patterns in a device design, the overlay critical patterns having an overlay sensitivity to process variation above a specified threshold that depends on design specifications; and using metrology targets that correspond to the identified overlay critical patterns. Alternatively or complementarily, metrology methods comprise identifying yield critical patterns according to a corresponding process window narrowing due to specified process variation, wherein the narrowing is defined by a dependency of edge placement errors (EPEs) of the patterns on process parameters. Corresponding targets and measurements are provided.

A memory includes: a random seed generation circuit suitable for generating a random seed including process variation information; a random signal generator suitable for generating a random signal that is randomly activated based on the random seed; and an address sampling circuit suitable for sampling an active address while the random signal is activated.

Systems and methods for process variation power control in three- dimensional integrated circuits, 3DICs, are disclosed. In an exemplary aspect, at least one process variation sensor (324, 326) is placed in each tier (302) of a 3DIC (300). The process variation sensors report information related to a speed characteristic for elements within the respective tier to a decision logic (328). The decision logic is programmed to weight output from the process variation sensors according to relative importance of logic path segments (310, 320) in the respective tiers. The weighted outputs are combinedto generate a power control signal that is sent to a power management unit (PMU). By weighting the importance of the logic path segments, a compromise voltage may be generated by the PMU which is ''good enough'' for all the elements in the various tiers to provide acceptable performance.