26 results about "Process variation" patented technology

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

A process variation tolerant microring resonator is designed based on fabrication process variation (FPV) map data that includes one or more FPV maps that indicate a process variation in a substrate. Waveguide parameter data are estimated from the FPV map, where the waveguide parameter data include estimated waveguide parameters as they are affected by process variations. Microring resonator parameter data are generated from the FPV map data and waveguide parameter data. The microring resonator parameter data includes estimated microring resonator parameters as they are affected by process variations. The waveguide parameter data and microring resonator parameter data can be output as a design for a process variation tolerant microring resonator, which can be further optimized based on user feedback or other constraints.

The application relates to the field of photoetching technology, and particularly relates to a method and device for rapidly screening overlay mark manufacturability and computer equipment, which comprises the following steps: inputting preset range of process window conditions, selecting upper limit value and lower limit value as extreme process window conditions; calculating initial process variation bandwidth value based on the extreme process window conditions, and performing first screening on the initial process variation bandwidth value based on a preset screening ratio; calculating to-be-processed process window values corresponding to the screened process variation bandwidth values; performing second screening on the to-be-processed process window values based on a preset standard range to obtain final process window values; and screening the overlay marks corresponding to the final process window values. The application further provides a device and computer equipment. The problems of time and labor consumption in screening overlay mark manufacturability are solved.

The application belongs to the technical field of radio frequency amplifiers, and specifically discloses a CMOS common-source common-gate radio frequency amplifier with temperature and process deviation compensation, which comprises a bias circuit and an amplification stage circuit; the bias circuit adopts a temperature and process deviation compensation bias circuit; when the ambient temperature changes, the bias circuit can collect the real-time temperature of an amplifying tube and generate a new bias voltage, so that the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the temperature change is reduced; similarly, when the process parameter distribution deviation occurs in different regions of a wafer during the chip manufacturing process, the same chip bias circuit and the amplifying tube region of the amplification stage circuit are the same, the same process deviation is generated, the bias circuit can generate a new bias voltage according to the process deviation, the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the process deviation is reduced. The application is suitable for a low-noise amplifier in a WiFi radio frequency front-end module.

The present disclosure describes systems and methods for generating a superconducting electronic circuit design. The system includes a memory and a processor. The processor simulates a superconducting electronic circuit design using a first process variation to produce a first score and simulates the superconducting electronic circuit design using a second process variation to produce a second score. The processor, in response to determining that the first score is lower than the second score, simulates the superconducting electronic circuit design using the first process variation and a first design variation to produce a third score and simulates the superconducting electronic circuit design using the first process variation and a second design variation to produce a fourth score. The processor updates the superconducting electronic circuit design using the first process variation and the first design variation in response to determining that the third score is higher than the fourth score.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

A system and method for increasing the yield of manufactured integrated circuits by providing corrective circuit elements, including replacement planar transistors, fabricated by mid-off-line and / or back-end off-line processes to enable and disable corrective circuit elements that provide additional circuit functionality as needed, as determined by post-manufacturing testing of the integrated circuit and / or in-operation monitoring of circuit operation. The system and method can address the distribution of power and signals, such as clock signals and / or high-speed I / O signals, through problem areas resulting from failures due to suboptimal design, circuit aging, and / or manufacturing process variations.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

The invention discloses a method, a device and equipment for predicting circuit performance of a transistor, relates to the technical field of computer aided design of integrated circuits and semiconductor devices, and aims to solve the problem that an existing compact model constructed based on TCAD simulation is difficult to accurately map real process fluctuation of a field effect transistor. And circuit-level power consumption and performance prediction results are not accurate. The method comprises the following steps: acquiring TCAD simulation data and actual measurement data of the field effect transistor; training a neural network model according to the TCAD simulation data to obtain a TCAD prior model; according to the measured data, a transfer learning method is adopted to carry out fine tuning on the TCAD prior model, and a target prediction model is obtained; and performing circuit-level simulation on the field effect transistor based on a Verilog-A compact model to obtain a circuit-level power consumption and performance prediction result. The method for predicting the circuit performance of the transistor is used for improving the circuit-level power consumption and the performance prediction result of the field effect transistor.

The present application relates to the technical field of semiconductor manufacturing, in particular to a self-adaptive matching control method and system for plasma process. The method comprises: synchronously collecting multiple parameters such as incident wave power, reflected wave power, phase and air pressure in the process chamber in real time; inputting the parameters into a pre-trained self-adaptive algorithm model; solving the optimal cooperative adjustment amount and adjustment timing for adjusting the radio frequency power, frequency and the capacitor or inductor of the matching device by the model in real time; generating a control instruction according to the result to cooperatively drive multiple actuators to move synchronously, thereby realizing impedance matching. The system comprises corresponding functional modules. Through real-time sensing of multiple parameters and cooperative optimization algorithm combined with high-precision synchronous control, the present application realizes millisecond-level fast matching, significantly reduces power reflection and improves process consistency; and with the help of online learning and self-adaptive mechanism, the system can continuously adapt to equipment aging and process changes, and has high intelligence and reliability.

The invention relates to a plasma processing apparatus and a substrate supporting portion assembly. Techniques are provided for avoiding process variations caused by loss of a cap ring. According to one embodiment, a plasma processing apparatus includes a mounting table, a focus ring, a cap ring, a conductive ring, and a high-frequency power source. The focus ring is mounted on the mounting table and has conductivity. The conductive ring is placed on the cover ring. A first side surface positioned on the outer periphery of the focus ring and a second side surface positioned on the inner periphery of the conductive ring face each other and are separated from each other.

The invention relates to a wafer defect analysis method and system and a readable storage medium. The method comprises the following steps: dividing a wafer into a plurality of regions with different importance; evaluating and endowing the areas with different weight values so as to establish a comprehensive evaluation index system for specific areas with the weight values greater than a set value; obtaining original measurement data of the wafer, and performing weighting and dimension processing on the measurement data of the corresponding area according to the weight value to obtain optimized measurement data; processing the optimized measurement data by adopting a Kriging interpolation algorithm to generate a profile distribution diagram capable of reflecting the continuous distribution condition of the wafer surface parameters; and performing defect identification and analysis on the specific region based on the profile distribution diagram. Different weight values are given to the regions with different importance, so that the Kriging interpolation algorithm can more sensitively capture the process variation of the specific region with a higher weight value, and the effect and efficiency of defect analysis of the specific region are improved.

A method for monitoring a process variation index includes operations of: obtaining a target parameter to be monitored and a reference parameter used to increase goodness of fit among structural parameters predicted by measuring a structure in a specific location of a wafer; obtaining a reference parameter set in a reference model; and calculating a process variation index capable of confirming a structural change of the structure according to a change in process conditions using the structural parameter and the reference parameter.

A process monitoring technique for transistor-based devices is described. The technique utilizes an oscillator-based sensor and operates in two phases: calibration and measurement. During calibration, the oscillator is supplied with a calibration current, and the resulting frequency is measured. A correction factor is calculated by dividing the measured frequency by the calibration current. In the measurement phase, the oscillator is supplied with current from the device under test, such as a memory cell or other transistor-based structure. The frequency produced is measured and divided by the correction factor to determine the current from the device. This approach yields a current value independent of parasitic resistances and capacitances in the oscillator. The technique enables accurate process variation monitoring with little modification to existing circuit structures and is applicable to various transistor-based devices, including SRAM cells, logic circuits, and analog circuits.

The application belongs to the technical field of integrated circuits, and particularly relates to a process deviation automatic trimming circuit for a voltage reference source, which specifically comprises a voltage reference, a current source generation circuit, a process deviation detection circuit, a decoder and a trimming circuit, and is characterized in that the process deviation detection circuit is composed of several types of different resistors under the same process library, can accurately detect the process deviation amount, can accurately trim the reference voltage source, and realizes high-precision output of the reference voltage source. The process deviation automatic trimming circuit for the voltage reference source has simple structure, small layout area, and no external trimming pin of the chip, can automatically detect the process deviation amount, and automatically trims the reference voltage source according to the process deviation. The process deviation automatic trimming circuit for the voltage reference source can greatly reduce the chip production cost and the chip testing cost in the later stage.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

This invention discloses a voltage reference source circuit with low process deviation based on on-chip automatic adjustment, including a reference source, a core voltage reference source, an adjustment circuit, a comparator, and a digital execution logic circuit. The reference source and the core voltage reference source are respectively connected to the two input terminals of the comparator. The output terminal of the comparator is connected to the input terminal of the adjustment circuit through the digital execution logic circuit, and the output terminal of the adjustment circuit is connected to the core voltage reference source. The comparator compares the output voltage value of the core voltage reference source with a K-fold value of the output voltage value of the reference source, and controls the digital execution logic circuit to automatically adjust the output voltage of the core voltage reference source. This invention uses an additional reference source to calibrate the original design, reducing the impact of CMOS process deviation on the output voltage reference. In addition, the automatic adjustment achieved through the adjustment circuit reduces the complexity of the adjustment process, greatly reduces configuration complexity, and improves flexibility.

Embodiments herein describe relaxation oscillator circuits for physical unclonable function (PUF) circuits and / or for providing clocks to multiple dies. The relaxation oscillator circuit generates a clock having a frequency that is based in part on random process variations of the passive components of the relaxation oscillator circuit. The relaxation oscillator circuit may be distributed amongst multiple dies of an integrated circuit device, to incorporate additional sources of randomness / entropy, enhance security, to provide clocks to the multiple dies. The relaxation oscillator circuits include differential and single-ended relaxation oscillator circuits. Resistive and / or capacitive components may be configurable, which may be useful for testing purposes, altering PUF codes, and / or generating time-multiplexed clocks.

This application provides a circuit design method and related equipment applicable to the field of integrated circuit technology. The method includes: acquiring a first circuit diagram based on multiple first devices, each first device including first parameters, which are parameters with normalized names used under various processes; then acquiring the electrical parameter indices of the multiple first devices based on the first circuit diagram; and determining multiple second parameters based on the indices of the electrical parameters of the multiple first devices, with each second parameter corresponding one-to-one with the first parameter. The first parameters of the first devices are then replaced with the second parameters to obtain second devices, and a second circuit diagram constructed from the multiple second devices is output. This method reduces the process of adjusting circuit parameters due to changes in electrical parameter indices or process PDK (Power Process Key), followed by running simulations to check results and readjusting, thus reducing multiple iterations and improving circuit design efficiency.

This application provides an internal clock generation circuit, semiconductor chip, and device for tracking process variations. The circuit includes: a latch, a replica array of SRAM, a first inverting circuit, and a P-type transistor. The output of the latch is connected to the word line of the replica array, the gate of the transistor, and the clock input of the SRAM. The drain of the transistor is connected to the bit line of the replica array. The bit line is connected to the reset terminal of the latch via the first inverting circuit. The word line discharges to the bit line when it is open. The set terminal of the latch receives an external clock signal, and the latch generates a first internal clock signal for the SRAM. This ensures that the open duration of WL matches the read speed, and the pulse width of the first internal clock signal is unaffected by the external clock signal CLK, minimizing the impact on read / write functions. Furthermore, this application does not require multiple iterations to determine the optimal Td to determine the pulse width, resulting in lower cost.

This application relates to the field of semiconductor technology and provides a gradient-doped composite JTE termination structure. The structure includes: a substrate; an epitaxial layer disposed on the substrate; an active region disposed in the epitaxial layer; and an edge protection zone disposed in the epitaxial layer and surrounding the active region. The edge protection zone includes multiple JTE regions and multiple reverse-doped regions. The multiple JTE regions are spaced apart in the epitaxial layer in a direction away from the active region, and the multiple reverse-doped regions are embedded within the JTE regions. The reverse-doped regions and the JTE regions are semiconductor materials with different conductivity types, and the doping concentration of the reverse-doped regions increases in a direction away from the active region. This application effectively flattens the surface electric field distribution by dividing the electric field spike at the main junction into multiple electric field peaks, thereby improving the device's breakdown voltage and tolerance to process variations.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

In some aspects, surrogate netlists are used instead of the actual netlist of interest (the target netlist) in order to speed up the runtime for variation analysis. It is desired to characterize the distribution of a circuit's response as a function of process variation, in a tail region of the distribution. The tail region of the distribution is located by performing a variation analysis based on samples generated by circuit simulations of one or more transistor-level surrogate netlists. The circuit simulations of the surrogate netlists have shorter runtimes than circuit simulations of the target netlist, resulting in a decrease of the overall runtime. The distribution in the tail region is then characterized based on samples generated by circuit simulations of the actual target netlist.

The invention relates to linearity improvement and process variation mitigation for radio frequency power detectors. A wireless circuit is provided that includes a circuit configured to output a radio frequency signal and a power detector having an input configured to receive the radio frequency signal. The power detector includes an input transistor and an attenuation circuit coupled to a gate terminal of the input transistor and having a series capacitor and a shunt capacitor of the same capacitor type. The series capacitor and the shunt capacitor of the same capacitor type may be configured to automatically track process variations of each other for mitigating sensitivity to the process variations. The series capacitor and the shunt capacitor may have an adjustable capacitance that is tuned to adjust the linearity of the power detector.

The present invention suppresses characteristic differences caused by process differences. A semiconductor device according to the present invention includes a semiconductor substrate, a plurality of element isolators, and a field effect transistor. In plan view, the field effect transistor is provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions. The field effect transistor includes a gate electrode, a fin portion, a gate insulating film, and a convex portion. The convex portion is formed between the embedded portion of the gate electrode and a sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and has a width narrower than a width of the fin portion. The convex portion contains an impurity of an opposite conductivity type to the fin portion, and the impurity is distributed at an impurity concentration higher than an impurity concentration at other places of the semiconductor substrate.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.