8 results about "Process variation" patented technology

The present disclosure describes systems and methods for generating a superconducting electronic circuit design. The system includes a memory and a processor. The processor simulates a superconducting electronic circuit design using a first process variation to produce a first score and simulates the superconducting electronic circuit design using a second process variation to produce a second score. The processor, in response to determining that the first score is lower than the second score, simulates the superconducting electronic circuit design using the first process variation and a first design variation to produce a third score and simulates the superconducting electronic circuit design using the first process variation and a second design variation to produce a fourth score. The processor updates the superconducting electronic circuit design using the first process variation and the first design variation in response to determining that the third score is higher than the fourth score.

The invention discloses a method, a device and equipment for predicting circuit performance of a transistor, relates to the technical field of computer aided design of integrated circuits and semiconductor devices, and aims to solve the problem that an existing compact model constructed based on TCAD simulation is difficult to accurately map real process fluctuation of a field effect transistor. And circuit-level power consumption and performance prediction results are not accurate. The method comprises the following steps: acquiring TCAD simulation data and actual measurement data of the field effect transistor; training a neural network model according to the TCAD simulation data to obtain a TCAD prior model; according to the measured data, a transfer learning method is adopted to carry out fine tuning on the TCAD prior model, and a target prediction model is obtained; and performing circuit-level simulation on the field effect transistor based on a Verilog-A compact model to obtain a circuit-level power consumption and performance prediction result. The method for predicting the circuit performance of the transistor is used for improving the circuit-level power consumption and the performance prediction result of the field effect transistor.

The present application relates to the technical field of semiconductor manufacturing, in particular to a self-adaptive matching control method and system for plasma process. The method comprises: synchronously collecting multiple parameters such as incident wave power, reflected wave power, phase and air pressure in the process chamber in real time; inputting the parameters into a pre-trained self-adaptive algorithm model; solving the optimal cooperative adjustment amount and adjustment timing for adjusting the radio frequency power, frequency and the capacitor or inductor of the matching device by the model in real time; generating a control instruction according to the result to cooperatively drive multiple actuators to move synchronously, thereby realizing impedance matching. The system comprises corresponding functional modules. Through real-time sensing of multiple parameters and cooperative optimization algorithm combined with high-precision synchronous control, the present application realizes millisecond-level fast matching, significantly reduces power reflection and improves process consistency; and with the help of online learning and self-adaptive mechanism, the system can continuously adapt to equipment aging and process changes, and has high intelligence and reliability.

A process monitoring technique for transistor-based devices is described. The technique utilizes an oscillator-based sensor and operates in two phases: calibration and measurement. During calibration, the oscillator is supplied with a calibration current, and the resulting frequency is measured. A correction factor is calculated by dividing the measured frequency by the calibration current. In the measurement phase, the oscillator is supplied with current from the device under test, such as a memory cell or other transistor-based structure. The frequency produced is measured and divided by the correction factor to determine the current from the device. This approach yields a current value independent of parasitic resistances and capacitances in the oscillator. The technique enables accurate process variation monitoring with little modification to existing circuit structures and is applicable to various transistor-based devices, including SRAM cells, logic circuits, and analog circuits.

Embodiments herein describe relaxation oscillator circuits for physical unclonable function (PUF) circuits and / or for providing clocks to multiple dies. The relaxation oscillator circuit generates a clock having a frequency that is based in part on random process variations of the passive components of the relaxation oscillator circuit. The relaxation oscillator circuit may be distributed amongst multiple dies of an integrated circuit device, to incorporate additional sources of randomness / entropy, enhance security, to provide clocks to the multiple dies. The relaxation oscillator circuits include differential and single-ended relaxation oscillator circuits. Resistive and / or capacitive components may be configurable, which may be useful for testing purposes, altering PUF codes, and / or generating time-multiplexed clocks.

This application provides an internal clock generation circuit, semiconductor chip, and device for tracking process variations. The circuit includes: a latch, a replica array of SRAM, a first inverting circuit, and a P-type transistor. The output of the latch is connected to the word line of the replica array, the gate of the transistor, and the clock input of the SRAM. The drain of the transistor is connected to the bit line of the replica array. The bit line is connected to the reset terminal of the latch via the first inverting circuit. The word line discharges to the bit line when it is open. The set terminal of the latch receives an external clock signal, and the latch generates a first internal clock signal for the SRAM. This ensures that the open duration of WL matches the read speed, and the pulse width of the first internal clock signal is unaffected by the external clock signal CLK, minimizing the impact on read / write functions. Furthermore, this application does not require multiple iterations to determine the optimal Td to determine the pulse width, resulting in lower cost.

This application relates to the field of semiconductor technology and provides a gradient-doped composite JTE termination structure. The structure includes: a substrate; an epitaxial layer disposed on the substrate; an active region disposed in the epitaxial layer; and an edge protection zone disposed in the epitaxial layer and surrounding the active region. The edge protection zone includes multiple JTE regions and multiple reverse-doped regions. The multiple JTE regions are spaced apart in the epitaxial layer in a direction away from the active region, and the multiple reverse-doped regions are embedded within the JTE regions. The reverse-doped regions and the JTE regions are semiconductor materials with different conductivity types, and the doping concentration of the reverse-doped regions increases in a direction away from the active region. This application effectively flattens the surface electric field distribution by dividing the electric field spike at the main junction into multiple electric field peaks, thereby improving the device's breakdown voltage and tolerance to process variations.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.