22results about "Marginal checking" patented technology

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

The invention relates to the technical field of reliability testing of Android equipment without a built-in battery, and discloses a file damage critical time determining method, testing equipment and a system.The method comprises the steps that after a testing file is received, power-off operation is executed by delaying a preset duration, and power-on is conducted again after power-off to detect a hash value of the file, so that whether the file is damaged or not is judged; if the current hash value is matched with the original hash value, further detecting the time precision of the preset duration, adjusting the preset duration when the time precision does not reach a set value, repeating the test, and taking the preset duration at the moment as the file damage critical time after the time precision reaches the standard; the technical means of delaying the preset time length for power-off, detecting the file state in combination with the Hash value matching and then adjusting the preset time length according to the time precision is adopted, so that the problem that the control precision of the power-off time of the traditional power-off test is insufficient is solved, and compared with the prior art, the effect of accurately reproducing the damage critical time of the file system is realized.

The invention provides a test method and system, electronic equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining a test address, a test type and at least one test execution parameter of a fault injection test by receiving an instant communication message sent by first equipment or a network request sent through a preset network path; the at least one test execution parameter comprises a performance test configuration parameter of the fault injection test; based on the at least one test execution parameter, calling a fault injection task interface corresponding to the test type, and generating a test task; and performing a fault injection test on the target test equipment corresponding to the test address by executing the test task to obtain a test result corresponding to the test task. According to the invention, the complexity of the fault injection test can be reduced, and the refinement degree of the fault injection test can be improved.

A lane margin testing method for testing a plurality of Peripheral Component Interconnect Express (PCIe) lanes of an electronic system includes storing test software in a non-transitory computer-readable storage medium of the electronic system; generating a plurality of instruction files based on information of the plurality of PCIe lanes and storing the plurality of instruction files in the non-transitory computer-readable storage medium, wherein each of the plurality of instruction files includes a plurality of test instructions for a corresponding PCIe lane; and generating an auto-run file based on the plurality of instruction files and storing the auto-run file in the non-transitory computer-readable storage medium, wherein the auto-run file is used to instruct the test software to execute the plurality of test instructions recorded in each instruction file of the plurality of instruction files.

A compliance testing system (10) for testing an electronic device under test (12) is described. The compliance testing system (10) comprises a user interface (18), a machine-learning circuit (20), and a database. The database comprises compliance testing data, wherein the compliance testing data comprises information on regulations and standards for performing compliance tests on different devices under test. The user interface (18) is configured to receive a user input, wherein the user input comprises text and / or speech relating to the device under test (12) to be tested. The machine-learning circuit (20) is configured to determine which regulations and standards are applicable to the device under test (12) to be tested based on the user input. The machine-learning circuit (20) is configured to generate a set of rules describing the application of the applicable regulations and standards to the device under test (12) that is to be tested. The machine-learning circuit (20) is configured to generate test data based on the generated set of rules, wherein the test data comprises information on compliance tests to be performed on the device under test (12) in view of the applicable regulations and standards. Further, a compliance testing method is described.

Disclosed is a fail-closed conformance control layer for machine-assisted decision artifacts. The system generates replay-verifiable receipts that commit to a canonical artifact digest, evidence and snapshot identifiers, assumptions, toolchain identifiers, and a policy pack identifier and policy version digest. A deterministic validator evaluates a receipt under the versioned policy pack to output PASS, FAIL, or HOLD with reason codes from a reason-code registry, including time-stamped modeled-variability codes. Downstream side effects are gated in a control path and permitted only on PASS; otherwise they are withheld or routed to remediation or human review. The system may emit portable conformance packs and revalidate receipts over time to detect drift and manage a certification lifecycle. Conformance suites with deterministic test vectors and expected validator outputs may certify validator implementations by issuing signed conformance certificates and publishing a certificate or certificate digest to a verifiable certificate registry for independent verification and procurement acceptance testing.

The core board stress testing method, system, device, equipment, medium and program product provided by the present disclosure are related to the field of computers, in particular to the field of cloud computing, and can be applied to scenarios such as cloud servers. The specific implementation scheme is: sending a network connection request to at least two core boards in a server to be tested; and sending a stress testing command to the core boards in the case where a feedback message of the core boards is received in response to the network connection request. The technical scheme of the present disclosure can implement batch stress testing on the core boards in the server.

The invention relates to a memory border crossing detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method is applied to a first processor, and comprises the following steps: performing instruction analysis on a first heterogeneous program to obtain a reference memory address corresponding to a read-write instruction in the first heterogeneous program; acquiring an actual memory address corresponding to the read-write instruction in a process that a second processor runs the first heterogeneous program; and according to the reference memory address and the actual memory address, determining whether memory crossing exists in the first heterogeneous program. By adopting the method, the memory crossing of the heterogeneous program running on the heterogeneous chip can be effectively detected.

The invention provides a fan noise detection method which is suitable for a machine shell provided with a fan and a plurality of hard disk slots. The method comprises the following steps: taking a plurality of hard disk slots as target hard disk slots in turn, and executing the following steps: inserting an agent hard disk on which a microphone is arranged into the target hard disk slots, obtaining a critical working period of a fan corresponding to the target hard disk slots, and when the fan operates in the critical working period, measuring by using the microphone to obtain a time domain sound pressure level, and converting the time-domain sound pressure level into a frequency-domain sound pressure level, taking the frequency-domain sound pressure level as one of a plurality of frequency-domain sound pressure levels corresponding to the plurality of hard disk slots, and taking a plurality of maximum values of the plurality of frequency-domain sound pressure levels at a plurality of frequencies as a system sound pressure limit frequency spectrum, and obtaining and outputting a single fan noise spectrum according to the system sound pressure limit spectrum and the number of the fans.

Methods and systems are described herein for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements to expected ranges derived from mission profile, mode of operation, and / or historical data. If the measurement is determined to be outside the expected range, a warning is generated to prompt a corrective action.

The invention discloses a server overall power consumption testing method and system, a storage medium and computer equipment, and the method comprises the steps: obtaining a configuration file corresponding to a tested server, analyzing the configuration file, and determining a target business scene; according to the target business scene, determining a matched target pressure model from a plurality of preset business scene pressure models, obtaining a pressure toolkit corresponding to the target pressure model, and sending the pressure toolkit to the tested server; remote control is carried out on the tested server, so that a pressure toolkit in the tested server tests the tested server according to a predefined load mode in the target pressure model; in the process that the tested server executes the test, power consumption data are synchronously collected until the test is finished, according to the collected power consumption data, a whole machine power consumption test result of the tested server is generated, and the power consumption data comprise whole machine power consumption data of the tested server and component power consumption data of all components of the tested server.

The present invention relates to a body (2) which is a spacecraft and is located under space conditions, at least one control computer (3) located on the body (2) and providing for the control of the body (2), at least one power source (4) located on the body (2), connected to the control computer (3), and generating power, and a plurality of components (5) located on the body (2) to be tested under space conditions.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and / or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and / or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.

The present disclosure relates to rating memory devices based on performance metrics set based on various timing margin parameters. An operating timing condition associated with a memory device to be installed at a memory subsystem is determined. The memory device can include a cross-point array of non-volatile memory cells. The operating timing condition corresponds to a first operational delay timing margin setting for the cross-point array of non-volatile memory cells. A first set of memory access operations is performed at the cross-point array of non-volatile memory cells according to a second operational delay timing margin setting that is lower than the first operational delay timing margin setting. A first number of errors that occur during performance of the first set of memory access operations is determined. In response to determining that the first number of errors satisfies an error condition, a first quality rating is assigned to the memory device. In response to determining that the first number of errors does not satisfy the error criteria, further testing is performed for the cross-point array of non-volatile memory cells based on one or more power level settings.

The invention provides an MCU chip communication fault intelligent diagnosis method and device, equipment and a medium, and the method comprises the steps: collecting a chip communication interface signal, obtaining communication waveform data, and carrying out the preprocessing of the communication waveform data, and obtaining time series data; inputting the time sequence data into a fault detection and parameter prediction model trained by a communication waveform data set of a simulation MCU chip communication fault type, and obtaining a fault classification result and a physical parameter prediction value of fault determination; fitting a historical multi-dimensional physical parameter sample to obtain a judgment boundary; and mapping the physical parameter predicted value to a multi-dimensional physical parameter space to obtain a vector, calculating a minimum weighted distance from the vector to a judgment boundary, determining a corresponding MCU chip communication safety margin, and comparing a preset safety margin judgment threshold to determine the communication state of the MCU chip. The reliability of the final MCU chip and the overall test verification efficiency are improved, and the contradiction between efficiency and depth in the prior art is solved.

In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

A hardware exerciser can iteratively perform a plurality of runs of a first test case. For each of the plurality of runs of first test case, at least one performance metric indicating a respective performance of the microprocessor for the respective run can be determined. Responsive to completion of each of the plurality of respective runs of the first test case subsequent to a first run of the first test case, a difference between performance metric(s) determined for a most recent run of the first test case and the performance metric(s) determined for a previous run of the first test case can be determined. For a first most recent run of the first test case, responsive to the difference being greater than a first threshold value, running of the first test case on the microprocessor can be continued.

The invention discloses a verification test method for an M-PHY layer of a UFS. The verification test method comprises the following steps: step 1) setting up a test environment; configuring a multi-rate adaptive test engine; configuring an inter-channel interference simulation system; configuring a protocol perception type state machine verifier; the verification test method for testing the M-PHY layer of the UFS comprises the steps of (1) carrying out an M-PHY layer, (2) carrying out a multi-rate adaptive test, (3) carrying out an inter-channel interference simulation test, and (4) carrying out protocol perception type state machine verifier.The verification test method for testing the M-PHY layer of the UFS can verify the data integrity and reliability of UFS equipment on the M-PHY layer.

Methods, apparatus, and products for dynamic current protection for server loads include multiple computer components, a programmable eFuse (electronic fuse) coupled to the multiple computer components, and a BMC (baseboard management controller) coupled to the programmable eFuse. The BMC is configured to: during a startup procedure, program one or more limits of the eFuse based on configuration data associated with each of the plurality of computer components, enable, prior to completing the startup procedure, the programmable eFuse with the one or more limits, and perform, while the eFuse is enabled, a test on the plurality of computer components using the eFuse.

Systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. In some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., “a chiplet”) and may be configured to be controlled via an associated local controller, which may enable and / or disable the chiplet as targeted. In embodiments, the local controllers may receive instructions from a central controller and, via the enabling and / or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. As a result, the system may be configured to perform system testing without additional resources and / or without redirecting resources that may be intended for other operations.