43results about "Marginal checking" patented technology

Systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. In some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., “a chiplet”) and may be configured to be controlled via an associated local controller, which may enable and / or disable the chiplet as targeted. In embodiments, the local controllers may receive instructions from a central controller and, via the enabling and / or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. As a result, the system may be configured to perform system testing without additional resources and / or without redirecting resources that may be intended for other operations.

An electronic device according to one embodiment may comprise a PMIC, a memory, and a processor. The processor can identify, in response to an input indicating booting of the processor, whether to acquire driving information on the basis of the frequency of the processor. The processor controls the PMIC in a state designated for acquiring the driving information on the basis of the frequency of the processor, and thus can change respective frequencies of different circuits in the processor by using a designated data set. The processor can acquire the driving information about the circuits in the processor for the frequencies on the basis of a hit rate indicating the number of operations performed by the plurality of circuits for each of the changed frequencies of the circuits.

In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

The invention provides a radiator test method, equipment and a test system, which can be applied to the technical field of computers. The method comprises the following steps: in response to a test request for a to-be-tested radiator, sending a sensor simulation value corresponding to the test request to the to-be-tested radiator, so that the to-be-tested radiator outputs a heat dissipation control value for the sensor simulation value under the condition that the to-be-tested radiator determines that the sensor simulation value meets a heat dissipation condition; and comparing the heat dissipation control value obtained from the to-be-tested radiator with a preset control value to obtain a test result of the to-be-tested radiator.

A mechanism is provided for automatically detecting, diagnosing, transporting, and repairing a device that fails during an aging test. Embodiments provide a system that monitors a device undergoing an aging test and detects when the device or internal components of the device fail the aging test. Then, embodiments can alert an aging test rack operator of the device failure. Embodiments can simultaneously determine the nature of the failure by applying a machine learning-based prediction model to a log file associated with the failed device. The diagnosis can be provided to a repair center along with a recommended repair strategy to help expedite the repair process. Additionally, the diagnosis can also be used to order spare parts from a spare parts warehouse for repair. In this way, embodiments can reduce the time required to detect, diagnose, and repair the failed device.

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

The invention relates to the technical field of smart home, and provides a micro-service distributed pressure measurement method, system and device, a storage medium and a product, and the method comprises the steps that a pressure measurement control node receives a pressure measurement task issued by a user, and starts distributed pressure measurement; wherein the pressure test task comprises configuration information of a to-be-tested service interface and configuration information of a to-be-tested analog interface; the pressure applying machine cluster initiates a pressure testing request for the to-be-tested service interface according to the configuration information of the to-be-tested service interface so as to generate distributed pressure testing; the simulation cluster simulates a dependency service interface corresponding to the to-be-tested service through the to-be-tested simulation interface according to the configuration information of the to-be-tested simulation interface; wherein the to-be-tested simulation interface can be directly called by the to-be-tested service. According to the scheme of the invention, test resources are saved, and the pressure test under the micro-service architecture can be effectively carried out under the scenes that the resources are limited, the high-concurrency test capability is needed and the real service calling environment needs to be simulated.

To design a new device under test in a shorter period of time.SOLUTION: A server 212 accepts, from a plurality of test measurement devices 202 on a network 204, data such as results of electrical margin tests of a device under test (DUT) 222 and information about components of a test system 224, and constructs a database in a storage device thereof. When a user tests a new DUT 222, the server 212 accepts the test result thereof, compares the same with data of a similar DUT 222 in the past, for analyzing, and answers a soundness score of the new DUT 222.SELECTED DRAWING: Figure 2

The invention relates to the technical field of reliability testing of Android equipment without a built-in battery, and discloses a file damage critical time determining method, testing equipment and a system.The method comprises the steps that after a testing file is received, power-off operation is executed by delaying a preset duration, and power-on is conducted again after power-off to detect a hash value of the file, so that whether the file is damaged or not is judged; if the current hash value is matched with the original hash value, further detecting the time precision of the preset duration, adjusting the preset duration when the time precision does not reach a set value, repeating the test, and taking the preset duration at the moment as the file damage critical time after the time precision reaches the standard; the technical means of delaying the preset time length for power-off, detecting the file state in combination with the Hash value matching and then adjusting the preset time length according to the time precision is adopted, so that the problem that the control precision of the power-off time of the traditional power-off test is insufficient is solved, and compared with the prior art, the effect of accurately reproducing the damage critical time of the file system is realized.

An automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads, determining a minimum safe voltage for each of the one or more cores based on the user-specified workloads, and changing the voltage configuration of each of the one or more cores based on the respective minimum safe voltage.

A compliance testing system (10) for testing an electronic device under test (12) is described. The compliance testing system (10) comprises a user interface (18), a machine-learning circuit (20), and a database. The database comprises compliance testing data, wherein the compliance testing data comprises information on regulations and standards for performing compliance tests on different devices under test. The user interface (18) is configured to receive a user input, wherein the user input comprises text and / or speech relating to the device under test (12) to be tested. The machine-learning circuit (20) is configured to determine which regulations and standards are applicable to the device under test (12) to be tested based on the user input. The machine-learning circuit (20) is configured to generate a set of rules describing the application of the applicable regulations and standards to the device under test (12) that is to be tested. The machine-learning circuit (20) is configured to generate test data based on the generated set of rules, wherein the test data comprises information on compliance tests to be performed on the device under test (12) in view of the applicable regulations and standards. Further, a compliance testing method is described.

The invention provides a test method and system, electronic equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining a test address, a test type and at least one test execution parameter of a fault injection test by receiving an instant communication message sent by first equipment or a network request sent through a preset network path; the at least one test execution parameter comprises a performance test configuration parameter of the fault injection test; based on the at least one test execution parameter, calling a fault injection task interface corresponding to the test type, and generating a test task; and performing a fault injection test on the target test equipment corresponding to the test address by executing the test task to obtain a test result corresponding to the test task. According to the invention, the complexity of the fault injection test can be reduced, and the refinement degree of the fault injection test can be improved.

A lane margin testing method for testing a plurality of Peripheral Component Interconnect Express (PCIe) lanes of an electronic system includes storing test software in a non-transitory computer-readable storage medium of the electronic system; generating a plurality of instruction files based on information of the plurality of PCIe lanes and storing the plurality of instruction files in the non-transitory computer-readable storage medium, wherein each of the plurality of instruction files includes a plurality of test instructions for a corresponding PCIe lane; and generating an auto-run file based on the plurality of instruction files and storing the auto-run file in the non-transitory computer-readable storage medium, wherein the auto-run file is used to instruct the test software to execute the plurality of test instructions recorded in each instruction file of the plurality of instruction files.

A compliance testing system (10) for testing an electronic device under test (12) is described. The compliance testing system (10) comprises a user interface (18), a machine-learning circuit (20), and a database. The database comprises compliance testing data, wherein the compliance testing data comprises information on regulations and standards for performing compliance tests on different devices under test. The user interface (18) is configured to receive a user input, wherein the user input comprises text and / or speech relating to the device under test (12) to be tested. The machine-learning circuit (20) is configured to determine which regulations and standards are applicable to the device under test (12) to be tested based on the user input. The machine-learning circuit (20) is configured to generate a set of rules describing the application of the applicable regulations and standards to the device under test (12) that is to be tested. The machine-learning circuit (20) is configured to generate test data based on the generated set of rules, wherein the test data comprises information on compliance tests to be performed on the device under test (12) in view of the applicable regulations and standards. Further, a compliance testing method is described.

Disclosed is a fail-closed conformance control layer for machine-assisted decision artifacts. The system generates replay-verifiable receipts that commit to a canonical artifact digest, evidence and snapshot identifiers, assumptions, toolchain identifiers, and a policy pack identifier and policy version digest. A deterministic validator evaluates a receipt under the versioned policy pack to output PASS, FAIL, or HOLD with reason codes from a reason-code registry, including time-stamped modeled-variability codes. Downstream side effects are gated in a control path and permitted only on PASS; otherwise they are withheld or routed to remediation or human review. The system may emit portable conformance packs and revalidate receipts over time to detect drift and manage a certification lifecycle. Conformance suites with deterministic test vectors and expected validator outputs may certify validator implementations by issuing signed conformance certificates and publishing a certificate or certificate digest to a verifiable certificate registry for independent verification and procurement acceptance testing.

The core board stress testing method, system, device, equipment, medium and program product provided by the present disclosure are related to the field of computers, in particular to the field of cloud computing, and can be applied to scenarios such as cloud servers. The specific implementation scheme is: sending a network connection request to at least two core boards in a server to be tested; and sending a stress testing command to the core boards in the case where a feedback message of the core boards is received in response to the network connection request. The technical scheme of the present disclosure can implement batch stress testing on the core boards in the server.

This disclosure describes a combined DPU and server solution with integrated data processing unit (DPU) and operating system (OS). The DPU OS executes on the DPU or other computing device, wherein the DPU OS utilizes secure calls provided by a trusted firmware component of the DPU, which can be invoked by the DPU OS component to abstract DPU vendor-specific and server vendor-specific integration details. One of the secure calls made on the DPU is identified for communication with its associated server computing device. In an example where one of the secure calls is invoked, the invoked secure call is translated into an architecture-specific call or request specific to the server computing device, and the call is executed, which may include sending signals to the server computing device in a format interpretable by the server computing device.

The embodiment of the present invention provides an intelligent stress testing method, device, electronic device and computer storage medium, wherein the intelligent stress testing method includes: obtaining multiple services used by the system to be stress tested and the service relationship between the multiple services; constructing a service topology map for the multiple services according to the service relationship; stress testing the multiple services based on the service topology map, and displaying the stress testing results through the service topology map. Through the embodiment of the present invention, there is no need to be on duty specifically for the service to be stress tested, which greatly reduces the manpower cost required for stress testing, and the implementation is simple, efficient and low cost.

The present disclosure provides a pressure test method for a memory engine, a server, a product and a storage medium. In the pressure test method for the memory engine, after pressure test parameters of a stand-alone memory engine under test are obtained, test data can be generated on the basis of data generation parameters and a data format corresponding to a workload of said stand-alone memory engine; then, the test data matches the data format corresponding to the workload of said stand-alone memory engine, better simulating the storage scenario of the workload; and a read-write interface provided by said stand-alone memory engine performs a data processing operation on at least some of data blocks among a plurality of data blocks, such that a pressure device can directly act on said stand-alone memory engine, and the requirements for performing pressure test on said stand-alone memory engine are met, wherein the type of the data processing operation matches the operation type of the workload of said stand-alone memory engine.

The invention relates to a memory border crossing detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method is applied to a first processor, and comprises the following steps: performing instruction analysis on a first heterogeneous program to obtain a reference memory address corresponding to a read-write instruction in the first heterogeneous program; acquiring an actual memory address corresponding to the read-write instruction in a process that a second processor runs the first heterogeneous program; and according to the reference memory address and the actual memory address, determining whether memory crossing exists in the first heterogeneous program. By adopting the method, the memory crossing of the heterogeneous program running on the heterogeneous chip can be effectively detected.

The invention provides a fan noise detection method which is suitable for a machine shell provided with a fan and a plurality of hard disk slots. The method comprises the following steps: taking a plurality of hard disk slots as target hard disk slots in turn, and executing the following steps: inserting an agent hard disk on which a microphone is arranged into the target hard disk slots, obtaining a critical working period of a fan corresponding to the target hard disk slots, and when the fan operates in the critical working period, measuring by using the microphone to obtain a time domain sound pressure level, and converting the time-domain sound pressure level into a frequency-domain sound pressure level, taking the frequency-domain sound pressure level as one of a plurality of frequency-domain sound pressure levels corresponding to the plurality of hard disk slots, and taking a plurality of maximum values of the plurality of frequency-domain sound pressure levels at a plurality of frequencies as a system sound pressure limit frequency spectrum, and obtaining and outputting a single fan noise spectrum according to the system sound pressure limit spectrum and the number of the fans.

Methods and systems are described herein for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements to expected ranges derived from mission profile, mode of operation, and / or historical data. If the measurement is determined to be outside the expected range, a warning is generated to prompt a corrective action.

The invention discloses a server overall power consumption testing method and system, a storage medium and computer equipment, and the method comprises the steps: obtaining a configuration file corresponding to a tested server, analyzing the configuration file, and determining a target business scene; according to the target business scene, determining a matched target pressure model from a plurality of preset business scene pressure models, obtaining a pressure toolkit corresponding to the target pressure model, and sending the pressure toolkit to the tested server; remote control is carried out on the tested server, so that a pressure toolkit in the tested server tests the tested server according to a predefined load mode in the target pressure model; in the process that the tested server executes the test, power consumption data are synchronously collected until the test is finished, according to the collected power consumption data, a whole machine power consumption test result of the tested server is generated, and the power consumption data comprise whole machine power consumption data of the tested server and component power consumption data of all components of the tested server.

The present invention relates to a body (2) which is a spacecraft and is located under space conditions, at least one control computer (3) located on the body (2) and providing for the control of the body (2), at least one power source (4) located on the body (2), connected to the control computer (3), and generating power, and a plurality of components (5) located on the body (2) to be tested under space conditions.

A compliance testing system includes a user interface, a machine-learning circuit, and a database. The database includes compliance testing data including information on regulations and standards for performing compliance tests on different devices under test (DUT). The user interface is configured to receive a user input including text and / or speech relating to the DUT to be tested. The machine-learning circuit is configured to determine which regulations and standards are applicable to the DUT to be tested based on the user input. The machine-learning circuit is configured to generate a set of rules describing the application of the applicable regulations and standards to the DUT that is to be tested. The machine-learning circuit is configured to generate test data based on the generated set of rules. The test data may include information on compliance tests to be performed on the DUT in view of the applicable regulations and standards.

The present disclosure provides a pressure test method for a memory engine, a server, a product and a storage medium. In the pressure test method for the memory engine, after pressure test parameters of a stand-alone memory engine under test are obtained, test data can be generated on the basis of data generation parameters and a data format corresponding to a workload of said stand-alone memory engine; then, the test data matches the data format corresponding to the workload of said stand-alone memory engine, better simulating the storage scenario of the workload; and a read-write interface provided by said stand-alone memory engine performs a data processing operation on at least some of data blocks among a plurality of data blocks, such that a pressure device can directly act on said stand-alone memory engine, and the requirements for performing pressure test on said stand-alone memory engine are met, wherein the type of the data processing operation matches the operation type of the workload of said stand-alone memory engine.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and / or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.

The present invention relates to systems, devices, and methods for non-invasive platform telemetry reporting using an integrated connector. In one embodiment, a device includes a controller coupled between a system-on-chip (SoC) of a platform and an external connector. The controller can include: a digital converter for digitizing platform telemetry information of the platform; and a control circuit for receiving commands from a debug test system and directing the platform telemetry information to a destination in response to the commands. Other embodiments are described and claimed.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and / or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.