1071 results about "Bus mastering" patented technology

A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.

A network adapter is provided that controls the transfer of data between a host computer and a network medium in a manner which optimizes the amount of data transferred between the host computer and the buffer of the network adapter during a contemporaneous transfer of data between the network medium and the buffer. The network adapter optimizes the data transfer by dynamically determining when to make a bus request such that the buffer is capable of transferring a data packet of a particular target burst size at the end of an estimated latency period. The network adapter includes a buffer memory that transfers data between the host computer and the network medium and a buffer control logic that generates a first buffer data signal in response to the amount of data in the buffer memory. The adapter further includes a bus control logic that generates a second buffer data signal in response to previous transfers of data between the host computer and the network medium, and a dynamic bus request logic that asserts a bus request signal at a time responsive to the first and second buffer data signals to initiate an optimized data transfer between the host computer and the buffer memory during a contemporaneous transfer of data between the buffer memory and the network medium. In one instance, the target burst size is equal to the maximum amount of data transferred between the host computer and the buffer in a single transaction since the host computer has been powered on. Further, in one instance the estimated latency is set as the latency of the previous data transfer between the buffer and the host computer.

If a USB device is turned off or is not active, the device may be electrically disconnected from a USB host controller. The device may be electrically disconnected through a physical interface on the device. In some embodiments, if the device becomes active during a wait period (e.g., 2-3 seconds) prior to electrically disconnecting the device, the device may not be electrically disconnected. In some embodiments, when the device is electrically disconnected from the USB host controller and no system activity of a bus mastering peripheral is occurring, the CPU may enter a low power state if other conditions are met. In some embodiments, if the USB device becomes active after electrically disconnecting, the electrical disconnection may be discontinued.

A method and apparatus for a dual power supply on a universal serial bus system using an overcurrent detect circuit. Dual power supplies in the universal serial bus system allows for greater flexibility of operation and is based on two separate power systems. The first power system is achieved using the power line on the bus connecting to the universal serial bus controller. The second power system is a separate power supply to power the downstream ports. Moreover, the universal serial bus system has an overcurrent and thermal error detect circuit based on the power system in order to achieve an efficient and cost effective method and apparatus in which to notify the universal serial bus controller of any error in the power system.

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.

A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus controller over a bus are addressable via a memory mapped address within the address space. An address translation table is stored on at least one of the plurality of bus components. The bus translation table stores a translation between a virtual address and a real address.

A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.

A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master control unit estimates a respective time delay in transmitting messages by electronic control units on each controller area network bus. The time delay is a difference between a time when a message is generated by a respective electronic control unit for transmission on a respective controller area network bus and a time when the message is transmitted on the respective controller area network bus. The global time is adjusted for each respective controller area network bus based on the estimated time delays associated with each respective controller area network bus. Global time messages from the master control unit are transmitted to each electronic control unit that include the adjusted global times for an associated controller area network bus.

A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller. The control timing of the secondary memory controller is independent of the control timing of the general purpose peripheral bus controller. Also, a processor arbiter is coupled to the embedded processor, and a relatively high-speed peripheral bus arbiter is coupled to the peripheral bus host bridge. Aside from the microcontroller, an embedded system can include a relatively low-speed general purpose peripheral bus and a relatively high-speed peripheral bus, both external to the microcontroller. The external relatively lowspeed general purpose bus can be coupled to the relatively low-speed general purpose peripheral bus controller, and the external relatively high-speed peripheral bus can be coupled to the relatively high-speed peripheral bus host bridge.

A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.

An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a first transfer mode and priority to transfer of isochronous data during a second transfer mode. A switch selectively couples the CPU, the memory controller circuit and the interconnect bus controller.

Since a conventional information processing apparatus includes a plurality of semiconductor devices, there is a problem that sensitive information may reside on a system bus in the apparatus or a semiconductor memory device serving as main memory therein. To obviate this problem, each information processing apparatus has a CPU which includes a microprocessor, a cryptographic processing algorithm ROM, a cryptographic processing hardware circuit, a RAM, a key custody area, and an external bus controller, which are all integrated on a single semiconductor chip. Thus, encryption/decryption processing is carried out only in the CPU, and internal operations of the CPU are made non-analyzable from an external signal of the CPU.

A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen PCI peripheral component slots to have access through a single PCI host bridge to the system bus.

A processing system includes a communication bus, a controller, an Input/Output (“I/O”) block, and reconfigurable logic segments (e.g., reconfigurable units). Individually reconfigurable logic segments are part of a single chip. A communication bus is in electrical communication with the logic segments. A first logic segment communicates to a second logic segment over the communication bus. Reconfiguration can partition a first logic segment into a second and a third logic segment where the smaller logic segments are in electrical communication with the communication bus. Resources are dynamically reallocated when reconfigurable units are either combined or partitioned. More specifically, both partitioning a logic segment and combining two or more logic segments can change the bus width allocated to a reconfigurable unit and the quantity of logic gates in the reconfigured unit. The embedded resources included in a logic segment can also change as a result of reconfiguration. The processing system provides high chip utilization throughout the chip's operation.